// Use this group name for NamedRegionTimer.
static const char *TimerGroupName;
+public:
+ /// VerifyEnabled - True when -verify-regalloc is given.
+ static bool VerifyEnabled;
+
private:
void seedLiveVirtRegs(std::priority_queue<std::pair<float, unsigned> >&);
// Temporary verification option until we can put verification inside
// MachineVerifier.
-static cl::opt<bool>
-VerifyRegAlloc("verify-regalloc",
- cl::desc("Verify live intervals before renaming"));
+static cl::opt<bool, true>
+VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
+ cl::desc("Verify during register allocation"));
const char *RegAllocBase::TimerGroupName = "Register Allocation";
+bool RegAllocBase::VerifyEnabled = false;
namespace {
/// RABasic provides a minimal implementation of the basic register allocation
// make the rewriter a separate pass and override verifyAnalysis instead. When
// that happens, verification naturally falls under VerifyMachineCode.
#ifndef NDEBUG
- if (VerifyRegAlloc) {
+ if (VerifyEnabled) {
// Verify accuracy of LiveIntervals. The standard machine code verifier
// ensures that each LiveIntervals covers all uses of the virtual reg.
SplitEditor(*SA, *LIS, *VRM, *DomTree, LREdit)
.splitAroundLoop(Loop->getLoop());
+ if (VerifyEnabled)
+ MF->verify(this);
+
// We have new split regs, don't assign anything.
return 0;
}
<< ((Value*)mf.getFunction())->getName() << '\n');
MF = &mf;
+ if (VerifyEnabled)
+ MF->verify(this);
+
RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
DomTree = &getAnalysis<MachineDominatorTree>();
ReservedRegs = TRI->getReservedRegs(*MF);