[PowerPC] Add variants of "sync" instruction

This adds support for the "sync $L" instruction with operand,
and provides aliases for "lwsync" and "ptesync".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185344 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td
index b316fa6773af0e6072ae2f93159f7281b582ce5f..9f5435e17a3d4022b114043760e0c766a8ada1df 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/lib/Target/PowerPC/PPCInstrFormats.td
@@ -473,8 +473,11 @@ class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
                string asmstr, InstrItinClass itin, list<dag> pattern> 
   : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<2> L;
+
   let Pattern = pattern;
-  let Inst{6-10}  = 0;
+  let Inst{6-8}   = 0;
+  let Inst{9-10}  = L;
   let Inst{11-15} = 0;
   let Inst{16-20} = 0;
   let Inst{21-30} = xo;

diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 28396fd1d94afa4bc9bd7b0dbc8d66478e1251d0..d05bd0d5b9ea4d004e1c0744eefa46f815e22003 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1508,9 +1508,9 @@ def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
           (STFDUX $rS, $ptrreg, $ptroff)>;
 
-def SYNC : XForm_24_sync<31, 598, (outs), (ins),
-                        "sync", LdStSync,
-                        [(int_ppc_sync)]>;
+def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
+                        "sync $L", LdStSync, []>;
+def : Pat<(int_ppc_sync), (SYNC 0)>;
 
 //===----------------------------------------------------------------------===//
 // PPC32 Arithmetic Instructions.
@@ -2231,7 +2231,7 @@ def : Pat<(f64 (extloadf32 xaddr:$src)),
 def : Pat<(f64 (fextend f32:$src)),
           (COPY_TO_REGCLASS $src, F8RC)>;
 
-def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
+def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>;
 
 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
@@ -2279,6 +2279,10 @@ class PPCAsmPseudo<string asm, dag iops>
 
 def : InstAlias<"sc", (SC 0)>;
 
+def : InstAlias<"sync", (SYNC 0)>;
+def : InstAlias<"lwsync", (SYNC 1)>;
+def : InstAlias<"ptesync", (SYNC 2)>;
+
 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
 
 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;

diff --git a/test/MC/PowerPC/ppc64-encoding-bookII.s b/test/MC/PowerPC/ppc64-encoding-bookII.s
index e74c971323fb9fa3c9e6c81142afcf5576122dfd..63f3a5ac671db9e180ed6a4be58951154b9c200a 100644 (file)
--- a/test/MC/PowerPC/ppc64-encoding-bookII.s
+++ b/test/MC/PowerPC/ppc64-encoding-bookII.s
@@ -30,7 +30,8 @@
 # CHECK: stdcx. 2, 3, 4                  # encoding: [0x7c,0x43,0x21,0xad]
          stdcx. 2, 3, 4
 
-# FIXME: sync 2
+# CHECK: sync 2                          # encoding: [0x7c,0x40,0x04,0xac]
+         sync 2
 # FIXME: eieio
 # FIXME: wait 2
 
@@ -47,10 +48,12 @@
 # CHECK: ldarx 2, 3, 4                   # encoding: [0x7c,0x43,0x20,0xa8]
          ldarx 2, 3, 4
 
-# CHECK: sync                            # encoding: [0x7c,0x00,0x04,0xac]
+# CHECK: sync 0                          # encoding: [0x7c,0x00,0x04,0xac]
          sync
-# FIXME: lwsync
-# FIXME: ptesync
+# CHECK: sync 1                          # encoding: [0x7c,0x20,0x04,0xac]
+         lwsync
+# CHECK: sync 2                          # encoding: [0x7c,0x40,0x04,0xac]
+         ptesync
 
 # FIXME: wait
 # FIXME: waitrsv