drm/msm: update generated headers
authorRob Clark <robdclark@gmail.com>
Wed, 20 May 2015 14:50:30 +0000 (10:50 -0400)
committerRob Clark <robdclark@gmail.com>
Thu, 11 Jun 2015 17:11:01 +0000 (13:11 -0400)
Signed-off-by: Rob Clark <robdclark@gmail.com>
17 files changed:
drivers/gpu/drm/msm/adreno/a2xx.xml.h
drivers/gpu/drm/msm/adreno/a3xx.xml.h
drivers/gpu/drm/msm/adreno/a4xx.xml.h
drivers/gpu/drm/msm/adreno/adreno_common.xml.h
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
drivers/gpu/drm/msm/dsi/dsi.xml.h
drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
drivers/gpu/drm/msm/dsi/sfpb.xml.h
drivers/gpu/drm/msm/edp/edp.xml.h
drivers/gpu/drm/msm/hdmi/hdmi.xml.h
drivers/gpu/drm/msm/hdmi/qfprom.xml.h
drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c
drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
drivers/gpu/drm/msm/mdp/mdp_common.xml.h
drivers/gpu/drm/msm/mdp/mdp_kms.h

index edc845fffdf4e4574501952ca3fd290c4b3fb028..23176e402796f4a3eb925c1c5fe02ec6cd666ceb 100644 (file)
@@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64344 bytes, from 2014-12-12 20:22:26)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51069 bytes, from 2014-12-21 15:51:54)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14895 bytes, from 2015-04-19 15:23:28)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  66709 bytes, from 2015-04-12 18:16:35)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  60633 bytes, from 2015-05-20 14:48:19)
 
 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
index e91a739452d7309653728991f8526197e38bd3b7..1c599e5cf318626f04c198271e69656d03046a36 100644 (file)
@@ -12,11 +12,11 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64344 bytes, from 2014-12-12 20:22:26)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51069 bytes, from 2014-12-21 15:51:54)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14895 bytes, from 2015-04-19 15:23:28)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  66709 bytes, from 2015-04-12 18:16:35)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  60633 bytes, from 2015-05-20 14:48:19)
 
-Copyright (C) 2013-2014 by the following authors:
+Copyright (C) 2013-2015 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
 
 Permission is hereby granted, free of charge, to any person obtaining
@@ -130,6 +130,10 @@ enum a3xx_tex_fmt {
        TFMT_I420_Y = 24,
        TFMT_I420_U = 26,
        TFMT_I420_V = 27,
+       TFMT_ATC_RGB = 32,
+       TFMT_ATC_RGBA_EXPLICIT = 33,
+       TFMT_ETC1 = 34,
+       TFMT_ATC_RGBA_INTERPOLATED = 35,
        TFMT_DXT1 = 36,
        TFMT_DXT3 = 37,
        TFMT_DXT5 = 38,
@@ -178,10 +182,13 @@ enum a3xx_tex_fmt {
        TFMT_32_SINT = 92,
        TFMT_32_32_SINT = 93,
        TFMT_32_32_32_32_SINT = 95,
-       TFMT_RGTC2_SNORM = 112,
-       TFMT_RGTC2_UNORM = 113,
-       TFMT_RGTC1_SNORM = 114,
-       TFMT_RGTC1_UNORM = 115,
+       TFMT_ETC2_RG11_SNORM = 112,
+       TFMT_ETC2_RG11_UNORM = 113,
+       TFMT_ETC2_R11_SNORM = 114,
+       TFMT_ETC2_R11_UNORM = 115,
+       TFMT_ETC2_RGBA8 = 116,
+       TFMT_ETC2_RGB8A1 = 117,
+       TFMT_ETC2_RGB8 = 118,
 };
 
 enum a3xx_tex_fetchsize {
@@ -209,14 +216,24 @@ enum a3xx_color_fmt {
        RB_R10G10B10A2_UNORM = 16,
        RB_A8_UNORM = 20,
        RB_R8_UNORM = 21,
+       RB_R16_FLOAT = 24,
+       RB_R16G16_FLOAT = 25,
        RB_R16G16B16A16_FLOAT = 27,
        RB_R11G11B10_FLOAT = 28,
+       RB_R16_SNORM = 32,
+       RB_R16G16_SNORM = 33,
+       RB_R16G16B16A16_SNORM = 35,
+       RB_R16_UNORM = 36,
+       RB_R16G16_UNORM = 37,
+       RB_R16G16B16A16_UNORM = 39,
        RB_R16_SINT = 40,
        RB_R16G16_SINT = 41,
        RB_R16G16B16A16_SINT = 43,
        RB_R16_UINT = 44,
        RB_R16G16_UINT = 45,
        RB_R16G16B16A16_UINT = 47,
+       RB_R32_FLOAT = 48,
+       RB_R32G32_FLOAT = 49,
        RB_R32G32B32A32_FLOAT = 51,
        RB_R32_SINT = 52,
        RB_R32G32_SINT = 53,
@@ -265,6 +282,12 @@ enum a3xx_intp_mode {
        FLAT = 1,
 };
 
+enum a3xx_repl_mode {
+       S = 1,
+       T = 2,
+       ONE_T = 3,
+};
+
 enum a3xx_tex_filter {
        A3XX_TEX_NEAREST = 0,
        A3XX_TEX_LINEAR = 1,
@@ -751,7 +774,7 @@ static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val)
 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT                 0
 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
 {
-       return ((((int32_t)(val * 16384.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
+       return ((((int32_t)(val * 64.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
 }
 
 #define REG_A3XX_GRAS_SU_MODE_CONTROL                          0x00002070
@@ -854,6 +877,12 @@ static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode va
 {
        return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK;
 }
+#define A3XX_RB_MODE_CONTROL_MRT__MASK                         0x00003000
+#define A3XX_RB_MODE_CONTROL_MRT__SHIFT                                12
+static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val)
+{
+       return ((val) << A3XX_RB_MODE_CONTROL_MRT__SHIFT) & A3XX_RB_MODE_CONTROL_MRT__MASK;
+}
 #define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE             0x00008000
 #define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE               0x00010000
 
@@ -1246,9 +1275,21 @@ static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op v
 
 #define REG_A3XX_RB_STENCIL_CLEAR                              0x00002105
 
-#define REG_A3XX_RB_STENCIL_BUF_INFO                           0x00002106
+#define REG_A3XX_RB_STENCIL_INFO                               0x00002106
+#define A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK                        0xfffff800
+#define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT               11
+static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
+{
+       return ((val >> 12) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
+}
 
-#define REG_A3XX_RB_STENCIL_BUF_PITCH                          0x00002107
+#define REG_A3XX_RB_STENCIL_PITCH                              0x00002107
+#define A3XX_RB_STENCIL_PITCH__MASK                            0xffffffff
+#define A3XX_RB_STENCIL_PITCH__SHIFT                           0
+static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val)
+{
+       return ((val >> 3) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK;
+}
 
 #define REG_A3XX_RB_STENCILREFMASK                             0x00002108
 #define A3XX_RB_STENCILREFMASK_STENCILREF__MASK                        0x000000ff
@@ -1356,6 +1397,7 @@ static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_
 {
        return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK;
 }
+#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE                  0x00001000
 #define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART                        0x00100000
 #define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST               0x02000000
 #define A3XX_PC_PRIM_VTX_CNTL_PSIZE                            0x04000000
@@ -1805,6 +1847,102 @@ static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val)
 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; }
 
 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; }
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK                 0x00000003
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT                        0
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK                 0x0000000c
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT                        2
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK                 0x00000030
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT                        4
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK                 0x000000c0
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT                        6
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK                 0x00000300
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT                        8
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK                 0x00000c00
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT                        10
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK                 0x00003000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT                        12
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK                 0x0000c000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT                        14
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK                 0x00030000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT                        16
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK                 0x000c0000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT                        18
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK                 0x00300000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT                        20
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK                 0x00c00000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT                        22
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK                 0x03000000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT                        24
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK                 0x0c000000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT                        26
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK                 0x30000000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT                        28
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK                 0xc0000000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT                        30
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK;
+}
 
 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0                     0x0000228a
 
@@ -2107,6 +2245,12 @@ static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1                    0x000022e9
 
 #define REG_A3XX_SP_FS_OUTPUT_REG                              0x000022ec
+#define A3XX_SP_FS_OUTPUT_REG_MRT__MASK                                0x00000003
+#define A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT                       0
+static inline uint32_t A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
+{
+       return ((val) << A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A3XX_SP_FS_OUTPUT_REG_MRT__MASK;
+}
 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE                     0x00000080
 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK                        0x0000ff00
 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT               8
@@ -2661,7 +2805,7 @@ static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
 }
 
 #define REG_A3XX_TEX_CONST_3                                   0x00000003
-#define A3XX_TEX_CONST_3_LAYERSZ1__MASK                                0x0000000f
+#define A3XX_TEX_CONST_3_LAYERSZ1__MASK                                0x00007fff
 #define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT                       0
 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val)
 {
index 755723fd8ba5472473bee61b3153af2ecf5af069..3f06ecf62583af3e1c247abdbc4bf47dd5850a44 100644 (file)
@@ -12,11 +12,11 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64344 bytes, from 2014-12-12 20:22:26)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51069 bytes, from 2014-12-21 15:51:54)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14895 bytes, from 2015-04-19 15:23:28)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  66709 bytes, from 2015-04-12 18:16:35)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  60633 bytes, from 2015-05-20 14:48:19)
 
-Copyright (C) 2013-2014 by the following authors:
+Copyright (C) 2013-2015 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
 
 Permission is hereby granted, free of charge, to any person obtaining
@@ -43,10 +43,40 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 enum a4xx_color_fmt {
        RB4_A8_UNORM = 1,
+       RB4_R8_UNORM = 2,
+       RB4_R4G4B4A4_UNORM = 8,
+       RB4_R5G5B5A1_UNORM = 10,
        RB4_R5G6R5_UNORM = 14,
-       RB4_Z16_UNORM = 15,
+       RB4_R8G8_UNORM = 15,
+       RB4_R8G8_SNORM = 16,
+       RB4_R8G8_UINT = 17,
+       RB4_R8G8_SINT = 18,
+       RB4_R16_FLOAT = 21,
+       RB4_R16_UINT = 22,
+       RB4_R16_SINT = 23,
        RB4_R8G8B8_UNORM = 25,
        RB4_R8G8B8A8_UNORM = 26,
+       RB4_R8G8B8A8_SNORM = 28,
+       RB4_R8G8B8A8_UINT = 29,
+       RB4_R8G8B8A8_SINT = 30,
+       RB4_R10G10B10A2_UNORM = 31,
+       RB4_R10G10B10A2_UINT = 34,
+       RB4_R11G11B10_FLOAT = 39,
+       RB4_R16G16_FLOAT = 42,
+       RB4_R16G16_UINT = 43,
+       RB4_R16G16_SINT = 44,
+       RB4_R32_FLOAT = 45,
+       RB4_R32_UINT = 46,
+       RB4_R32_SINT = 47,
+       RB4_R16G16B16A16_FLOAT = 54,
+       RB4_R16G16B16A16_UINT = 55,
+       RB4_R16G16B16A16_SINT = 56,
+       RB4_R32G32_FLOAT = 57,
+       RB4_R32G32_UINT = 58,
+       RB4_R32G32_SINT = 59,
+       RB4_R32G32B32A32_FLOAT = 60,
+       RB4_R32G32B32A32_UINT = 61,
+       RB4_R32G32B32A32_SINT = 62,
 };
 
 enum a4xx_tile_mode {
@@ -91,7 +121,14 @@ enum a4xx_vtx_fmt {
        VFMT4_16_16_UNORM = 29,
        VFMT4_16_16_16_UNORM = 30,
        VFMT4_16_16_16_16_UNORM = 31,
+       VFMT4_32_UINT = 32,
+       VFMT4_32_32_UINT = 33,
+       VFMT4_32_32_32_UINT = 34,
+       VFMT4_32_32_32_32_UINT = 35,
+       VFMT4_32_SINT = 36,
        VFMT4_32_32_SINT = 37,
+       VFMT4_32_32_32_SINT = 38,
+       VFMT4_32_32_32_32_SINT = 39,
        VFMT4_8_UINT = 40,
        VFMT4_8_8_UINT = 41,
        VFMT4_8_8_8_UINT = 42,
@@ -125,12 +162,57 @@ enum a4xx_tex_fmt {
        TFMT4_8_UNORM = 4,
        TFMT4_8_8_UNORM = 14,
        TFMT4_8_8_8_8_UNORM = 28,
+       TFMT4_8_8_SNORM = 15,
+       TFMT4_8_8_8_8_SNORM = 29,
+       TFMT4_8_8_UINT = 16,
+       TFMT4_8_8_8_8_UINT = 30,
+       TFMT4_8_8_SINT = 17,
+       TFMT4_8_8_8_8_SINT = 31,
+       TFMT4_16_UINT = 21,
+       TFMT4_16_16_UINT = 41,
+       TFMT4_16_16_16_16_UINT = 54,
+       TFMT4_16_SINT = 22,
+       TFMT4_16_16_SINT = 42,
+       TFMT4_16_16_16_16_SINT = 55,
+       TFMT4_32_UINT = 44,
+       TFMT4_32_32_UINT = 57,
+       TFMT4_32_32_32_32_UINT = 64,
+       TFMT4_32_SINT = 45,
+       TFMT4_32_32_SINT = 58,
+       TFMT4_32_32_32_32_SINT = 65,
        TFMT4_16_FLOAT = 20,
        TFMT4_16_16_FLOAT = 40,
        TFMT4_16_16_16_16_FLOAT = 53,
        TFMT4_32_FLOAT = 43,
        TFMT4_32_32_FLOAT = 56,
        TFMT4_32_32_32_32_FLOAT = 63,
+       TFMT4_9_9_9_E5_FLOAT = 32,
+       TFMT4_11_11_10_FLOAT = 37,
+       TFMT4_ATC_RGB = 100,
+       TFMT4_ATC_RGBA_EXPLICIT = 101,
+       TFMT4_ATC_RGBA_INTERPOLATED = 102,
+       TFMT4_ETC2_RG11_UNORM = 103,
+       TFMT4_ETC2_RG11_SNORM = 104,
+       TFMT4_ETC2_R11_UNORM = 105,
+       TFMT4_ETC2_R11_SNORM = 106,
+       TFMT4_ETC1 = 107,
+       TFMT4_ETC2_RGB8 = 108,
+       TFMT4_ETC2_RGBA8 = 109,
+       TFMT4_ETC2_RGB8A1 = 110,
+       TFMT4_ASTC_4x4 = 111,
+       TFMT4_ASTC_5x4 = 112,
+       TFMT4_ASTC_5x5 = 113,
+       TFMT4_ASTC_6x5 = 114,
+       TFMT4_ASTC_6x6 = 115,
+       TFMT4_ASTC_8x5 = 116,
+       TFMT4_ASTC_8x6 = 117,
+       TFMT4_ASTC_8x8 = 118,
+       TFMT4_ASTC_10x5 = 119,
+       TFMT4_ASTC_10x6 = 120,
+       TFMT4_ASTC_10x8 = 121,
+       TFMT4_ASTC_10x10 = 122,
+       TFMT4_ASTC_12x10 = 123,
+       TFMT4_ASTC_12x12 = 124,
 };
 
 enum a4xx_tex_fetchsize {
@@ -147,9 +229,16 @@ enum a4xx_depth_format {
        DEPTH4_24_8 = 2,
 };
 
+enum a4xx_tess_spacing {
+       EQUAL_SPACING = 0,
+       ODD_SPACING = 2,
+       EVEN_SPACING = 3,
+};
+
 enum a4xx_tex_filter {
        A4XX_TEX_NEAREST = 0,
        A4XX_TEX_LINEAR = 1,
+       A4XX_TEX_ANISO = 2,
 };
 
 enum a4xx_tex_clamp {
@@ -159,6 +248,14 @@ enum a4xx_tex_clamp {
        A4XX_TEX_CLAMP_NONE = 3,
 };
 
+enum a4xx_tex_aniso {
+       A4XX_TEX_ANISO_1 = 0,
+       A4XX_TEX_ANISO_2 = 1,
+       A4XX_TEX_ANISO_4 = 2,
+       A4XX_TEX_ANISO_8 = 3,
+       A4XX_TEX_ANISO_16 = 4,
+};
+
 enum a4xx_tex_swiz {
        A4XX_TEX_X = 0,
        A4XX_TEX_Y = 1,
@@ -279,13 +376,16 @@ static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
 #define A4XX_RB_RENDER_CONTROL2_YCOORD                         0x00000002
 #define A4XX_RB_RENDER_CONTROL2_ZCOORD                         0x00000004
 #define A4XX_RB_RENDER_CONTROL2_WCOORD                         0x00000008
+#define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK                     0x00000010
 #define A4XX_RB_RENDER_CONTROL2_FACENESS                       0x00000020
+#define A4XX_RB_RENDER_CONTROL2_SAMPLEID                       0x00000040
 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK             0x00000380
 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT            7
 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val)
 {
        return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK;
 }
+#define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR                    0x00000800
 #define A4XX_RB_RENDER_CONTROL2_VARYING                                0x00001000
 
 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
@@ -310,6 +410,12 @@ static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val
 {
        return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
 }
+#define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK             0x000000c0
+#define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT            6
+static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val)
+{
+       return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
+}
 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK                 0x00000600
 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT                        9
 static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
@@ -322,6 +428,7 @@ static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
 {
        return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
 }
+#define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB                                0x00002000
 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK             0x007fc000
 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT            14
 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
@@ -449,7 +556,12 @@ static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare
 }
 
 #define REG_A4XX_RB_FS_OUTPUT                                  0x000020f9
-#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND                         0x00000001
+#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK                   0x000000ff
+#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT                  0
+static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val)
+{
+       return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK;
+}
 #define A4XX_RB_FS_OUTPUT_FAST_CLEAR                           0x00000100
 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK                    0xffff0000
 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT                   16
@@ -458,12 +570,54 @@ static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
        return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK;
 }
 
-#define REG_A4XX_RB_RENDER_CONTROL3                            0x000020fb
-#define A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__MASK         0x0000001f
-#define A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__SHIFT                0
-static inline uint32_t A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE(uint32_t val)
+#define REG_A4XX_RB_RENDER_COMPONENTS                          0x000020fb
+#define A4XX_RB_RENDER_COMPONENTS_RT0__MASK                    0x0000000f
+#define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT                   0
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
 {
-       return ((val) << A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__SHIFT) & A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__MASK;
+       return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK;
+}
+#define A4XX_RB_RENDER_COMPONENTS_RT1__MASK                    0x000000f0
+#define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT                   4
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
+{
+       return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK;
+}
+#define A4XX_RB_RENDER_COMPONENTS_RT2__MASK                    0x00000f00
+#define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT                   8
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
+{
+       return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK;
+}
+#define A4XX_RB_RENDER_COMPONENTS_RT3__MASK                    0x0000f000
+#define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT                   12
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
+{
+       return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK;
+}
+#define A4XX_RB_RENDER_COMPONENTS_RT4__MASK                    0x000f0000
+#define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT                   16
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
+{
+       return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK;
+}
+#define A4XX_RB_RENDER_COMPONENTS_RT5__MASK                    0x00f00000
+#define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT                   20
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
+{
+       return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK;
+}
+#define A4XX_RB_RENDER_COMPONENTS_RT6__MASK                    0x0f000000
+#define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT                   24
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
+{
+       return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK;
+}
+#define A4XX_RB_RENDER_COMPONENTS_RT7__MASK                    0xf0000000
+#define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT                   28
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
+{
+       return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK;
 }
 
 #define REG_A4XX_RB_COPY_CONTROL                               0x000020fc
@@ -547,7 +701,12 @@ static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val)
 }
 
 #define REG_A4XX_RB_FS_OUTPUT_REG                              0x00002100
-#define A4XX_RB_FS_OUTPUT_REG_COLOR_PIPE_ENABLE                        0x00000001
+#define A4XX_RB_FS_OUTPUT_REG_MRT__MASK                                0x0000000f
+#define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT                       0
+static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val)
+{
+       return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK;
+}
 #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z                    0x00000020
 
 #define REG_A4XX_RB_DEPTH_CONTROL                              0x00002101
@@ -930,6 +1089,10 @@ static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0)
 
 #define REG_A4XX_CP_IB2_BUFSZ                                  0x00000209
 
+#define REG_A4XX_CP_ME_NRT_ADDR                                        0x0000020c
+
+#define REG_A4XX_CP_ME_NRT_DATA                                        0x0000020d
+
 #define REG_A4XX_CP_ME_RB_DONE_DATA                            0x00000217
 
 #define REG_A4XX_CP_QUEUE_THRESH2                              0x00000219
@@ -940,9 +1103,9 @@ static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0)
 
 #define REG_A4XX_CP_ROQ_DATA                                   0x0000021d
 
-#define REG_A4XX_CP_MEQ_ADDR                                   0x0000021e
+#define REG_A4XX_CP_MEQ_ADDR                                   0x0000021e
 
-#define REG_A4XX_CP_MEQ_DATA                                   0x0000021f
+#define REG_A4XX_CP_MEQ_DATA                                   0x0000021f
 
 #define REG_A4XX_CP_MERCIU_ADDR                                        0x00000220
 
@@ -1004,12 +1167,17 @@ static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578
 
 #define REG_A4XX_SP_VS_STATUS                                  0x00000ec0
 
+#define REG_A4XX_SP_MODE_CONTROL                               0x00000ec3
+
 #define REG_A4XX_SP_PERFCTR_SP_SEL_11                          0x00000ecf
 
 #define REG_A4XX_SP_SP_CTRL_REG                                        0x000022c0
 #define A4XX_SP_SP_CTRL_REG_BINNING_PASS                       0x00080000
 
 #define REG_A4XX_SP_INSTR_CACHE_CTRL                           0x000022c1
+#define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER                     0x00000080
+#define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER                     0x00000100
+#define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER                  0x00000400
 
 #define REG_A4XX_SP_VS_CTRL_REG0                               0x000022c4
 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK                  0x00000001
@@ -1229,6 +1397,12 @@ static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
 #define REG_A4XX_SP_FS_LENGTH_REG                              0x000022ef
 
 #define REG_A4XX_SP_FS_OUTPUT_REG                              0x000022f0
+#define A4XX_SP_FS_OUTPUT_REG_MRT__MASK                                0x0000000f
+#define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT                       0
+static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
+{
+       return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK;
+}
 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE                     0x00000080
 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK                        0x0000ff00
 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT               8
@@ -1236,6 +1410,12 @@ static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
 {
        return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
 }
+#define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK           0xff000000
+#define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT          24
+static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val)
+{
+       return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK;
+}
 
 static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
 
@@ -1254,6 +1434,20 @@ static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)
        return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK;
 }
 
+#define REG_A4XX_SP_CS_CTRL_REG0                               0x00002300
+
+#define REG_A4XX_SP_CS_OBJ_OFFSET_REG                          0x00002301
+
+#define REG_A4XX_SP_CS_OBJ_START                               0x00002302
+
+#define REG_A4XX_SP_CS_PVT_MEM_PARAM                           0x00002303
+
+#define REG_A4XX_SP_CS_PVT_MEM_ADDR                            0x00002304
+
+#define REG_A4XX_SP_CS_PVT_MEM_SIZE                            0x00002305
+
+#define REG_A4XX_SP_CS_LENGTH_REG                              0x00002306
+
 #define REG_A4XX_SP_HS_OBJ_OFFSET_REG                          0x0000230d
 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK      0x01ff0000
 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT     16
@@ -1268,6 +1462,14 @@ static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
        return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
 }
 
+#define REG_A4XX_SP_HS_OBJ_START                               0x0000230e
+
+#define REG_A4XX_SP_HS_PVT_MEM_PARAM                           0x0000230f
+
+#define REG_A4XX_SP_HS_PVT_MEM_ADDR                            0x00002310
+
+#define REG_A4XX_SP_HS_LENGTH_REG                              0x00002312
+
 #define REG_A4XX_SP_DS_OBJ_OFFSET_REG                          0x00002334
 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK      0x01ff0000
 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT     16
@@ -1282,6 +1484,14 @@ static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
        return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
 }
 
+#define REG_A4XX_SP_DS_OBJ_START                               0x00002335
+
+#define REG_A4XX_SP_DS_PVT_MEM_PARAM                           0x00002336
+
+#define REG_A4XX_SP_DS_PVT_MEM_ADDR                            0x00002337
+
+#define REG_A4XX_SP_DS_LENGTH_REG                              0x00002339
+
 #define REG_A4XX_SP_GS_OBJ_OFFSET_REG                          0x0000235b
 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK      0x01ff0000
 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT     16
@@ -1296,6 +1506,12 @@ static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
        return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
 }
 
+#define REG_A4XX_SP_GS_OBJ_START                               0x0000235c
+
+#define REG_A4XX_SP_GS_PVT_MEM_PARAM                           0x0000235d
+
+#define REG_A4XX_SP_GS_PVT_MEM_ADDR                            0x0000235e
+
 #define REG_A4XX_SP_GS_LENGTH_REG                              0x00002360
 
 #define REG_A4XX_VPC_DEBUG_RAM_SEL                             0x00000e60
@@ -1418,6 +1634,10 @@ static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0
 
 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7                         0x00000e4a
 
+#define REG_A4XX_VGT_CL_INITIATOR                              0x000021d0
+
+#define REG_A4XX_VGT_EVENT_INITIATOR                           0x000021d9
+
 #define REG_A4XX_VFD_CONTROL_0                                 0x00002200
 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK                 0x000000ff
 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT                        0
@@ -1554,10 +1774,54 @@ static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
 
 #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL                                0x00000f00
 
+#define REG_A4XX_TPL1_TP_MODE_CONTROL                          0x00000f03
+
 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7                         0x00000f0b
 
 #define REG_A4XX_TPL1_TP_TEX_OFFSET                            0x00002380
 
+#define REG_A4XX_TPL1_TP_TEX_COUNT                             0x00002381
+#define A4XX_TPL1_TP_TEX_COUNT_VS__MASK                                0x000000ff
+#define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT                       0
+static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val)
+{
+       return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK;
+}
+#define A4XX_TPL1_TP_TEX_COUNT_HS__MASK                                0x0000ff00
+#define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT                       8
+static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val)
+{
+       return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK;
+}
+#define A4XX_TPL1_TP_TEX_COUNT_DS__MASK                                0x00ff0000
+#define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT                       16
+static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val)
+{
+       return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK;
+}
+#define A4XX_TPL1_TP_TEX_COUNT_GS__MASK                                0xff000000
+#define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT                       24
+static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val)
+{
+       return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK;
+}
+
+#define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR             0x00002384
+
+#define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR             0x00002387
+
+#define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR             0x0000238a
+
+#define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR             0x0000238d
+
+#define REG_A4XX_TPL1_TP_FS_TEX_COUNT                          0x000023a0
+
+#define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR             0x000023a1
+
+#define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR             0x000023a4
+
+#define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR                  0x000023a5
+
 #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR                        0x000023a6
 
 #define REG_A4XX_GRAS_TSE_STATUS                               0x00000c80
@@ -1676,6 +1940,14 @@ static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
        return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
 }
 
+#define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP                     0x00002076
+#define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK                   0xffffffff
+#define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT                  0
+static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val)
+{
+       return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK;
+}
+
 #define REG_A4XX_GRAS_DEPTH_CONTROL                            0x00002077
 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK                   0x00000003
 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT                  0
@@ -1828,6 +2100,8 @@ static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val)
 
 #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL                                0x00000e04
 
+#define REG_A4XX_HLSQ_MODE_CONTROL                             0x00000e05
+
 #define REG_A4XX_HLSQ_PERF_PIPE_MASK                           0x00000e0e
 
 #define REG_A4XX_HLSQ_CONTROL_0_REG                            0x000023c0
@@ -1867,7 +2141,12 @@ static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val)
 {
        return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK;
 }
-#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORD                                0x02000000
+#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK             0xff000000
+#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT            24
+static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val)
+{
+       return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK;
+}
 
 #define REG_A4XX_HLSQ_CONTROL_2_REG                            0x000023c2
 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK       0xfc000000
@@ -1882,6 +2161,18 @@ static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
 {
        return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
 }
+#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK           0x0003fc00
+#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT          10
+static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val)
+{
+       return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK;
+}
+#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK         0x03fc0000
+#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT                18
+static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val)
+{
+       return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK;
+}
 
 #define REG_A4XX_HLSQ_CONTROL_3_REG                            0x000023c3
 #define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK                    0x000000ff
@@ -1891,6 +2182,8 @@ static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
        return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK;
 }
 
+#define REG_A4XX_HLSQ_CONTROL_4_REG                            0x000023c4
+
 #define REG_A4XX_HLSQ_VS_CONTROL_REG                           0x000023c5
 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK             0x000000ff
 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT            0
@@ -1904,6 +2197,7 @@ static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
 {
        return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
 }
+#define A4XX_HLSQ_VS_CONTROL_REG_ENABLED                       0x00010000
 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK         0x00fe0000
 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT                17
 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
@@ -1930,6 +2224,7 @@ static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
 {
        return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
 }
+#define A4XX_HLSQ_FS_CONTROL_REG_ENABLED                       0x00010000
 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK         0x00fe0000
 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT                17
 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
@@ -1956,6 +2251,7 @@ static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
 {
        return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
 }
+#define A4XX_HLSQ_HS_CONTROL_REG_ENABLED                       0x00010000
 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK         0x00fe0000
 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT                17
 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
@@ -1982,6 +2278,7 @@ static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
 {
        return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
 }
+#define A4XX_HLSQ_DS_CONTROL_REG_ENABLED                       0x00010000
 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK         0x00fe0000
 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT                17
 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
@@ -2008,6 +2305,7 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
 {
        return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
 }
+#define A4XX_HLSQ_GS_CONTROL_REG_ENABLED                       0x00010000
 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK         0x00fe0000
 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT                17
 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
@@ -2021,6 +2319,36 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
        return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK;
 }
 
+#define REG_A4XX_HLSQ_CS_CONTROL                               0x000023ca
+
+#define REG_A4XX_HLSQ_CL_NDRANGE_0                             0x000023cd
+
+#define REG_A4XX_HLSQ_CL_NDRANGE_1                             0x000023ce
+
+#define REG_A4XX_HLSQ_CL_NDRANGE_2                             0x000023cf
+
+#define REG_A4XX_HLSQ_CL_NDRANGE_3                             0x000023d0
+
+#define REG_A4XX_HLSQ_CL_NDRANGE_4                             0x000023d1
+
+#define REG_A4XX_HLSQ_CL_NDRANGE_5                             0x000023d2
+
+#define REG_A4XX_HLSQ_CL_NDRANGE_6                             0x000023d3
+
+#define REG_A4XX_HLSQ_CL_CONTROL_0                             0x000023d4
+
+#define REG_A4XX_HLSQ_CL_CONTROL_1                             0x000023d5
+
+#define REG_A4XX_HLSQ_CL_KERNEL_CONST                          0x000023d6
+
+#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X                                0x000023d7
+
+#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y                                0x000023d8
+
+#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z                                0x000023d9
+
+#define REG_A4XX_HLSQ_CL_WG_OFFSET                             0x000023da
+
 #define REG_A4XX_HLSQ_UPDATE_CONTROL                           0x000023db
 
 #define REG_A4XX_PC_BINNING_COMMAND                            0x00000d00
@@ -2035,7 +2363,13 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
 #define REG_A4XX_PC_BIN_BASE                                   0x000021c0
 
 #define REG_A4XX_PC_PRIM_VTX_CNTL                              0x000021c4
-#define A4XX_PC_PRIM_VTX_CNTL_VAROUT                           0x00000001
+#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK                     0x0000000f
+#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT                    0
+static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
+{
+       return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK;
+}
+#define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART                        0x00100000
 #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST               0x02000000
 #define A4XX_PC_PRIM_VTX_CNTL_PSIZE                            0x04000000
 
@@ -2044,8 +2378,45 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
 #define REG_A4XX_PC_RESTART_INDEX                              0x000021c6
 
 #define REG_A4XX_PC_GS_PARAM                                   0x000021e5
+#define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK                    0x000003ff
+#define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT                   0
+static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
+{
+       return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK;
+}
+#define A4XX_PC_GS_PARAM_INVOCATIONS__MASK                     0x0000f800
+#define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT                    11
+static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
+{
+       return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK;
+}
+#define A4XX_PC_GS_PARAM_PRIMTYPE__MASK                                0x01800000
+#define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT                       23
+static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
+{
+       return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK;
+}
+#define A4XX_PC_GS_PARAM_LAYER                                 0x80000000
 
 #define REG_A4XX_PC_HS_PARAM                                   0x000021e7
+#define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK                    0x0000003f
+#define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT                   0
+static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
+{
+       return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK;
+}
+#define A4XX_PC_HS_PARAM_SPACING__MASK                         0x00600000
+#define A4XX_PC_HS_PARAM_SPACING__SHIFT                                21
+static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
+{
+       return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK;
+}
+#define A4XX_PC_HS_PARAM_PRIMTYPE__MASK                                0x01800000
+#define A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT                       23
+static inline uint32_t A4XX_PC_HS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
+{
+       return ((val) << A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_HS_PARAM_PRIMTYPE__MASK;
+}
 
 #define REG_A4XX_VBIF_VERSION                                  0x00003000
 
@@ -2074,16 +2445,10 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
 
 #define REG_A4XX_UNKNOWN_0D01                                  0x00000d01
 
-#define REG_A4XX_UNKNOWN_0E05                                  0x00000e05
-
 #define REG_A4XX_UNKNOWN_0E42                                  0x00000e42
 
 #define REG_A4XX_UNKNOWN_0EC2                                  0x00000ec2
 
-#define REG_A4XX_UNKNOWN_0EC3                                  0x00000ec3
-
-#define REG_A4XX_UNKNOWN_0F03                                  0x00000f03
-
 #define REG_A4XX_UNKNOWN_2001                                  0x00002001
 
 #define REG_A4XX_UNKNOWN_209B                                  0x0000209b
@@ -2124,10 +2489,6 @@ static inline uint32_t A4XX_UNKNOWN_20F7(float val)
 
 #define REG_A4XX_UNKNOWN_22D7                                  0x000022d7
 
-#define REG_A4XX_UNKNOWN_2381                                  0x00002381
-
-#define REG_A4XX_UNKNOWN_23A0                                  0x000023a0
-
 #define REG_A4XX_TEX_SAMP_0                                    0x00000000
 #define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR                  0x00000001
 #define A4XX_TEX_SAMP_0_XY_MAG__MASK                           0x00000006
@@ -2160,6 +2521,12 @@ static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val)
 {
        return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK;
 }
+#define A4XX_TEX_SAMP_0_ANISO__MASK                            0x0001c000
+#define A4XX_TEX_SAMP_0_ANISO__SHIFT                           14
+static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val)
+{
+       return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK;
+}
 
 #define REG_A4XX_TEX_SAMP_1                                    0x00000001
 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK                     0x0000000e
@@ -2185,6 +2552,7 @@ static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val)
 
 #define REG_A4XX_TEX_CONST_0                                   0x00000000
 #define A4XX_TEX_CONST_0_TILED                                 0x00000001
+#define A4XX_TEX_CONST_0_SRGB                                  0x00000004
 #define A4XX_TEX_CONST_0_SWIZ_X__MASK                          0x00000070
 #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT                         4
 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val)
index 8531beb982e778d3d4b0051050281920856d19b1..9562a1fa552b7319ce5b2af45f34377484db25d0 100644 (file)
@@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64344 bytes, from 2014-12-12 20:22:26)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51069 bytes, from 2014-12-21 15:51:54)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14895 bytes, from 2015-04-19 15:23:28)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  66709 bytes, from 2015-04-12 18:16:35)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  60633 bytes, from 2015-05-20 14:48:19)
 
 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
index 6ffc4f6c8af13d6b3fc4b049b8a715a6dbb0aec6..bd5b23bf9041eff30c85f924a024b458452b83ba 100644 (file)
@@ -12,11 +12,11 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64344 bytes, from 2014-12-12 20:22:26)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51069 bytes, from 2014-12-21 15:51:54)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14895 bytes, from 2015-04-19 15:23:28)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  66709 bytes, from 2015-04-12 18:16:35)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  60633 bytes, from 2015-05-20 14:48:19)
 
-Copyright (C) 2013-2014 by the following authors:
+Copyright (C) 2013-2015 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
 
 Permission is hereby granted, free of charge, to any person obtaining
@@ -76,16 +76,11 @@ enum pc_di_primtype {
        DI_PT_LINELOOP = 7,
        DI_PT_RECTLIST = 8,
        DI_PT_POINTLIST_A3XX = 9,
-       DI_PT_QUADLIST = 13,
-       DI_PT_QUADSTRIP = 14,
-       DI_PT_POLYGON = 15,
-       DI_PT_2D_COPY_RECT_LIST_V0 = 16,
-       DI_PT_2D_COPY_RECT_LIST_V1 = 17,
-       DI_PT_2D_COPY_RECT_LIST_V2 = 18,
-       DI_PT_2D_COPY_RECT_LIST_V3 = 19,
-       DI_PT_2D_FILL_RECT_LIST = 20,
-       DI_PT_2D_LINE_STRIP = 21,
-       DI_PT_2D_TRI_STRIP = 22,
+       DI_PT_LINE_ADJ = 10,
+       DI_PT_LINESTRIP_ADJ = 11,
+       DI_PT_TRI_ADJ = 12,
+       DI_PT_TRISTRIP_ADJ = 13,
+       DI_PT_PATCHES = 34,
 };
 
 enum pc_di_src_sel {
@@ -192,6 +187,7 @@ enum adreno_state_block {
        SB_FRAG_TEX = 2,
        SB_FRAG_MIPADDR = 3,
        SB_VERT_SHADER = 4,
+       SB_GEOM_SHADER = 5,
        SB_FRAG_SHADER = 6,
 };
 
@@ -382,12 +378,19 @@ static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel va
 {
        return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
 }
+#define CP_DRAW_INDX_OFFSET_0_TESSELLATE                       0x00000100
 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK                 0x00000c00
 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT                        10
 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
 {
        return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
 }
+#define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK                  0x01f00000
+#define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT                 20
+static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)
+{
+       return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK;
+}
 
 #define REG_CP_DRAW_INDX_OFFSET_1                              0x00000001
 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK              0xffffffff
index 1dcfae265e984723f6843fe93461796663e220e6..9791ea04bcbcf632a01a2bf978e0cfd0672eb05f 100644 (file)
@@ -8,8 +8,17 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /usr2/hali/local/envytools/envytools/rnndb/dsi/dsi.xml             (  18681 bytes, from 2015-03-04 23:08:31)
-- /usr2/hali/local/envytools/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2015-01-28 21:43:22)
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2014-12-05 15:34:49)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20915 bytes, from 2015-03-24 22:05:22)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2352 bytes, from 2015-04-12 15:02:42)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  35083 bytes, from 2015-04-12 15:04:03)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  22094 bytes, from 2015-05-12 12:45:23)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2014-10-31 16:48:57)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  29012 bytes, from 2015-05-12 12:45:23)
+- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (  10416 bytes, from 2015-05-12 12:45:23)
 
 Copyright (C) 2013-2015 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -394,6 +403,9 @@ static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val)
 #define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND                      0x00000001
 #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE                      0x00000010
 
+#define REG_DSI_LANE_CTRL                                      0x000000a8
+#define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST                   0x10000000
+
 #define REG_DSI_LANE_SWAP_CTRL                                 0x000000ac
 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK                  0x00000007
 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT                 0
@@ -835,5 +847,152 @@ static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
 
 #define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG                 0x00000018
 
+#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG                                0x00000000
+#define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR                       0x00000001
+
+#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG                      0x00000004
+
+#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG                       0x00000008
+
+#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG                                0x0000000c
+
+#define REG_DSI_28nm_PHY_PLL_VREG_CFG                          0x00000010
+#define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B            0x00000002
+
+#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG                                0x00000014
+
+#define REG_DSI_28nm_PHY_PLL_DMUX_CFG                          0x00000018
+
+#define REG_DSI_28nm_PHY_PLL_AMUX_CFG                          0x0000001c
+
+#define REG_DSI_28nm_PHY_PLL_GLB_CFG                           0x00000020
+#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B                   0x00000001
+#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B               0x00000002
+#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B            0x00000004
+#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE                    0x00000008
+
+#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG                      0x00000024
+
+#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG                      0x00000028
+
+#define REG_DSI_28nm_PHY_PLL_LPFR_CFG                          0x0000002c
+
+#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG                         0x00000030
+
+#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG                         0x00000034
+
+#define REG_DSI_28nm_PHY_PLL_SDM_CFG0                          0x00000038
+#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK                        0x0000003f
+#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT               0
+static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)
+{
+       return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK;
+}
+#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP                          0x00000040
+
+#define REG_DSI_28nm_PHY_PLL_SDM_CFG1                          0x0000003c
+#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK              0x0000003f
+#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT             0
+static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)
+{
+       return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
+}
+#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK              0x00000040
+#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT             6
+static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)
+{
+       return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK;
+}
+
+#define REG_DSI_28nm_PHY_PLL_SDM_CFG2                          0x00000040
+#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK          0x000000ff
+#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT         0
+static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)
+{
+       return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK;
+}
+
+#define REG_DSI_28nm_PHY_PLL_SDM_CFG3                          0x00000044
+#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK         0x000000ff
+#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT                0
+static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)
+{
+       return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK;
+}
+
+#define REG_DSI_28nm_PHY_PLL_SDM_CFG4                          0x00000048
+
+#define REG_DSI_28nm_PHY_PLL_SSC_CFG0                          0x0000004c
+
+#define REG_DSI_28nm_PHY_PLL_SSC_CFG1                          0x00000050
+
+#define REG_DSI_28nm_PHY_PLL_SSC_CFG2                          0x00000054
+
+#define REG_DSI_28nm_PHY_PLL_SSC_CFG3                          0x00000058
+
+#define REG_DSI_28nm_PHY_PLL_LKDET_CFG0                                0x0000005c
+
+#define REG_DSI_28nm_PHY_PLL_LKDET_CFG1                                0x00000060
+
+#define REG_DSI_28nm_PHY_PLL_LKDET_CFG2                                0x00000064
+
+#define REG_DSI_28nm_PHY_PLL_TEST_CFG                          0x00000068
+#define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET                 0x00000001
+
+#define REG_DSI_28nm_PHY_PLL_CAL_CFG0                          0x0000006c
+
+#define REG_DSI_28nm_PHY_PLL_CAL_CFG1                          0x00000070
+
+#define REG_DSI_28nm_PHY_PLL_CAL_CFG2                          0x00000074
+
+#define REG_DSI_28nm_PHY_PLL_CAL_CFG3                          0x00000078
+
+#define REG_DSI_28nm_PHY_PLL_CAL_CFG4                          0x0000007c
+
+#define REG_DSI_28nm_PHY_PLL_CAL_CFG5                          0x00000080
+
+#define REG_DSI_28nm_PHY_PLL_CAL_CFG6                          0x00000084
+
+#define REG_DSI_28nm_PHY_PLL_CAL_CFG7                          0x00000088
+
+#define REG_DSI_28nm_PHY_PLL_CAL_CFG8                          0x0000008c
+
+#define REG_DSI_28nm_PHY_PLL_CAL_CFG9                          0x00000090
+
+#define REG_DSI_28nm_PHY_PLL_CAL_CFG10                         0x00000094
+
+#define REG_DSI_28nm_PHY_PLL_CAL_CFG11                         0x00000098
+
+#define REG_DSI_28nm_PHY_PLL_EFUSE_CFG                         0x0000009c
+
+#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL                     0x000000a0
+
+#define REG_DSI_28nm_PHY_PLL_CTRL_42                           0x000000a4
+
+#define REG_DSI_28nm_PHY_PLL_CTRL_43                           0x000000a8
+
+#define REG_DSI_28nm_PHY_PLL_CTRL_44                           0x000000ac
+
+#define REG_DSI_28nm_PHY_PLL_CTRL_45                           0x000000b0
+
+#define REG_DSI_28nm_PHY_PLL_CTRL_46                           0x000000b4
+
+#define REG_DSI_28nm_PHY_PLL_CTRL_47                           0x000000b8
+
+#define REG_DSI_28nm_PHY_PLL_CTRL_48                           0x000000bc
+
+#define REG_DSI_28nm_PHY_PLL_STATUS                            0x000000c0
+#define DSI_28nm_PHY_PLL_STATUS_PLL_RDY                                0x00000001
+
+#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0                                0x000000c4
+
+#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1                                0x000000c8
+
+#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2                                0x000000cc
+
+#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3                                0x000000d0
+
+#define REG_DSI_28nm_PHY_PLL_CTRL_54                           0x000000d4
+
 
 #endif /* DSI_XML */
index 695f99d4bec27a34557490c68923982a15236510..728152f3ef48b6b2fbfabe5185b4f3dfa39d697b 100644 (file)
@@ -10,15 +10,15 @@ git clone https://github.com/freedreno/envytools.git
 The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2014-12-05 15:34:49)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20908 bytes, from 2014-12-08 16:13:00)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2357 bytes, from 2014-12-08 16:13:00)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  27208 bytes, from 2015-01-13 23:56:11)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20915 bytes, from 2015-03-24 22:05:22)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2352 bytes, from 2015-04-12 15:02:42)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  35083 bytes, from 2015-04-12 15:04:03)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  22094 bytes, from 2015-05-12 12:45:23)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2014-10-31 16:48:57)
 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  26848 bytes, from 2015-01-13 23:55:57)
-- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (   8253 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  29012 bytes, from 2015-05-12 12:45:23)
+- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (  10416 bytes, from 2015-05-12 12:45:23)
 
 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
index 50ff9851d73d138b119cfcf938485712465ecee7..26f268e2dd3d944a56471a174506d21febc6e079 100644 (file)
@@ -10,15 +10,15 @@ git clone https://github.com/freedreno/envytools.git
 The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2014-12-05 15:34:49)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20908 bytes, from 2014-12-08 16:13:00)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2357 bytes, from 2014-12-08 16:13:00)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  27208 bytes, from 2015-01-13 23:56:11)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20915 bytes, from 2015-03-24 22:05:22)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2352 bytes, from 2015-04-12 15:02:42)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  35083 bytes, from 2015-04-12 15:04:03)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  22094 bytes, from 2015-05-12 12:45:23)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2014-10-31 16:48:57)
 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  26848 bytes, from 2015-01-13 23:55:57)
-- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (   8253 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  29012 bytes, from 2015-05-12 12:45:23)
+- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (  10416 bytes, from 2015-05-12 12:45:23)
 
 Copyright (C) 2013 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
index a29f1df15143922a5ed8198e95fbfd447a7c0843..f9c71dceb5e296c89f93262baa3740e9c29e6ecb 100644 (file)
@@ -10,17 +10,17 @@ git clone https://github.com/freedreno/envytools.git
 The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2014-12-05 15:34:49)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20908 bytes, from 2014-12-08 16:13:00)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2357 bytes, from 2014-12-08 16:13:00)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  27208 bytes, from 2015-01-13 23:56:11)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20915 bytes, from 2015-03-24 22:05:22)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2352 bytes, from 2015-04-12 15:02:42)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  35083 bytes, from 2015-04-12 15:04:03)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  22094 bytes, from 2015-05-12 12:45:23)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2014-10-31 16:48:57)
 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  26848 bytes, from 2015-01-13 23:55:57)
-- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (   8253 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  29012 bytes, from 2015-05-12 12:45:23)
+- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (  10416 bytes, from 2015-05-12 12:45:23)
 
-Copyright (C) 2013-2014 by the following authors:
+Copyright (C) 2013-2015 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
 
 Permission is hereby granted, free of charge, to any person obtaining
@@ -288,5 +288,92 @@ static inline uint32_t REG_EDP_PHY_LN_PD_CTL(uint32_t i0) { return 0x00000404 +
 
 #define REG_EDP_PHY_GLB_PHY_STATUS                             0x00000598
 
+#define REG_EDP_28nm_PHY_PLL_REFCLK_CFG                                0x00000000
+
+#define REG_EDP_28nm_PHY_PLL_POSTDIV1_CFG                      0x00000004
+
+#define REG_EDP_28nm_PHY_PLL_CHGPUMP_CFG                       0x00000008
+
+#define REG_EDP_28nm_PHY_PLL_VCOLPF_CFG                                0x0000000c
+
+#define REG_EDP_28nm_PHY_PLL_VREG_CFG                          0x00000010
+
+#define REG_EDP_28nm_PHY_PLL_PWRGEN_CFG                                0x00000014
+
+#define REG_EDP_28nm_PHY_PLL_DMUX_CFG                          0x00000018
+
+#define REG_EDP_28nm_PHY_PLL_AMUX_CFG                          0x0000001c
+
+#define REG_EDP_28nm_PHY_PLL_GLB_CFG                           0x00000020
+#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B                   0x00000001
+#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B               0x00000002
+#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B            0x00000004
+#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE                    0x00000008
+
+#define REG_EDP_28nm_PHY_PLL_POSTDIV2_CFG                      0x00000024
+
+#define REG_EDP_28nm_PHY_PLL_POSTDIV3_CFG                      0x00000028
+
+#define REG_EDP_28nm_PHY_PLL_LPFR_CFG                          0x0000002c
+
+#define REG_EDP_28nm_PHY_PLL_LPFC1_CFG                         0x00000030
+
+#define REG_EDP_28nm_PHY_PLL_LPFC2_CFG                         0x00000034
+
+#define REG_EDP_28nm_PHY_PLL_SDM_CFG0                          0x00000038
+
+#define REG_EDP_28nm_PHY_PLL_SDM_CFG1                          0x0000003c
+
+#define REG_EDP_28nm_PHY_PLL_SDM_CFG2                          0x00000040
+
+#define REG_EDP_28nm_PHY_PLL_SDM_CFG3                          0x00000044
+
+#define REG_EDP_28nm_PHY_PLL_SDM_CFG4                          0x00000048
+
+#define REG_EDP_28nm_PHY_PLL_SSC_CFG0                          0x0000004c
+
+#define REG_EDP_28nm_PHY_PLL_SSC_CFG1                          0x00000050
+
+#define REG_EDP_28nm_PHY_PLL_SSC_CFG2                          0x00000054
+
+#define REG_EDP_28nm_PHY_PLL_SSC_CFG3                          0x00000058
+
+#define REG_EDP_28nm_PHY_PLL_LKDET_CFG0                                0x0000005c
+
+#define REG_EDP_28nm_PHY_PLL_LKDET_CFG1                                0x00000060
+
+#define REG_EDP_28nm_PHY_PLL_LKDET_CFG2                                0x00000064
+
+#define REG_EDP_28nm_PHY_PLL_TEST_CFG                          0x00000068
+#define EDP_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET                 0x00000001
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG0                          0x0000006c
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG1                          0x00000070
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG2                          0x00000074
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG3                          0x00000078
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG4                          0x0000007c
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG5                          0x00000080
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG6                          0x00000084
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG7                          0x00000088
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG8                          0x0000008c
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG9                          0x00000090
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG10                         0x00000094
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG11                         0x00000098
+
+#define REG_EDP_28nm_PHY_PLL_EFUSE_CFG                         0x0000009c
+
+#define REG_EDP_28nm_PHY_PLL_DEBUG_BUS_SEL                     0x000000a0
+
 
 #endif /* EDP_XML */
index 350988740e9fd2f21701e243489f002e8e7d1743..e6f03480837132efb239c5f5ff99cd52eceffa12 100644 (file)
@@ -10,15 +10,15 @@ git clone https://github.com/freedreno/envytools.git
 The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2014-12-05 15:34:49)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20908 bytes, from 2014-12-08 16:13:00)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2357 bytes, from 2014-12-08 16:13:00)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  27208 bytes, from 2015-01-13 23:56:11)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20915 bytes, from 2015-03-24 22:05:22)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2352 bytes, from 2015-04-12 15:02:42)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  35083 bytes, from 2015-04-12 15:04:03)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  22094 bytes, from 2015-05-12 12:45:23)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2014-10-31 16:48:57)
 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  26848 bytes, from 2015-01-13 23:55:57)
-- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (   8253 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  29012 bytes, from 2015-05-12 12:45:23)
+- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (  10416 bytes, from 2015-05-12 12:45:23)
 
 Copyright (C) 2013-2015 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -750,5 +750,92 @@ static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
 
 #define REG_HDMI_8x74_BIST_PATN3                               0x00000048
 
+#define REG_HDMI_28nm_PHY_PLL_REFCLK_CFG                       0x00000000
+
+#define REG_HDMI_28nm_PHY_PLL_POSTDIV1_CFG                     0x00000004
+
+#define REG_HDMI_28nm_PHY_PLL_CHGPUMP_CFG                      0x00000008
+
+#define REG_HDMI_28nm_PHY_PLL_VCOLPF_CFG                       0x0000000c
+
+#define REG_HDMI_28nm_PHY_PLL_VREG_CFG                         0x00000010
+
+#define REG_HDMI_28nm_PHY_PLL_PWRGEN_CFG                       0x00000014
+
+#define REG_HDMI_28nm_PHY_PLL_DMUX_CFG                         0x00000018
+
+#define REG_HDMI_28nm_PHY_PLL_AMUX_CFG                         0x0000001c
+
+#define REG_HDMI_28nm_PHY_PLL_GLB_CFG                          0x00000020
+#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B                  0x00000001
+#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B              0x00000002
+#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B           0x00000004
+#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE                   0x00000008
+
+#define REG_HDMI_28nm_PHY_PLL_POSTDIV2_CFG                     0x00000024
+
+#define REG_HDMI_28nm_PHY_PLL_POSTDIV3_CFG                     0x00000028
+
+#define REG_HDMI_28nm_PHY_PLL_LPFR_CFG                         0x0000002c
+
+#define REG_HDMI_28nm_PHY_PLL_LPFC1_CFG                                0x00000030
+
+#define REG_HDMI_28nm_PHY_PLL_LPFC2_CFG                                0x00000034
+
+#define REG_HDMI_28nm_PHY_PLL_SDM_CFG0                         0x00000038
+
+#define REG_HDMI_28nm_PHY_PLL_SDM_CFG1                         0x0000003c
+
+#define REG_HDMI_28nm_PHY_PLL_SDM_CFG2                         0x00000040
+
+#define REG_HDMI_28nm_PHY_PLL_SDM_CFG3                         0x00000044
+
+#define REG_HDMI_28nm_PHY_PLL_SDM_CFG4                         0x00000048
+
+#define REG_HDMI_28nm_PHY_PLL_SSC_CFG0                         0x0000004c
+
+#define REG_HDMI_28nm_PHY_PLL_SSC_CFG1                         0x00000050
+
+#define REG_HDMI_28nm_PHY_PLL_SSC_CFG2                         0x00000054
+
+#define REG_HDMI_28nm_PHY_PLL_SSC_CFG3                         0x00000058
+
+#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG0                       0x0000005c
+
+#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG1                       0x00000060
+
+#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG2                       0x00000064
+
+#define REG_HDMI_28nm_PHY_PLL_TEST_CFG                         0x00000068
+#define HDMI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET                        0x00000001
+
+#define REG_HDMI_28nm_PHY_PLL_CAL_CFG0                         0x0000006c
+
+#define REG_HDMI_28nm_PHY_PLL_CAL_CFG1                         0x00000070
+
+#define REG_HDMI_28nm_PHY_PLL_CAL_CFG2                         0x00000074
+
+#define REG_HDMI_28nm_PHY_PLL_CAL_CFG3                         0x00000078
+
+#define REG_HDMI_28nm_PHY_PLL_CAL_CFG4                         0x0000007c
+
+#define REG_HDMI_28nm_PHY_PLL_CAL_CFG5                         0x00000080
+
+#define REG_HDMI_28nm_PHY_PLL_CAL_CFG6                         0x00000084
+
+#define REG_HDMI_28nm_PHY_PLL_CAL_CFG7                         0x00000088
+
+#define REG_HDMI_28nm_PHY_PLL_CAL_CFG8                         0x0000008c
+
+#define REG_HDMI_28nm_PHY_PLL_CAL_CFG9                         0x00000090
+
+#define REG_HDMI_28nm_PHY_PLL_CAL_CFG10                                0x00000094
+
+#define REG_HDMI_28nm_PHY_PLL_CAL_CFG11                                0x00000098
+
+#define REG_HDMI_28nm_PHY_PLL_EFUSE_CFG                                0x0000009c
+
+#define REG_HDMI_28nm_PHY_PLL_DEBUG_BUS_SEL                    0x000000a0
+
 
 #endif /* HDMI_XML */
index 43bb54a9afbf1c5503bec3896df4887fa402e6bf..978c3f70872aa877ffb6001647926094a9630d19 100644 (file)
@@ -10,15 +10,15 @@ git clone https://github.com/freedreno/envytools.git
 The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2014-12-05 15:34:49)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20908 bytes, from 2014-12-08 16:13:00)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2357 bytes, from 2014-12-08 16:13:00)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  27208 bytes, from 2015-01-13 23:56:11)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20915 bytes, from 2015-03-24 22:05:22)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2352 bytes, from 2015-04-12 15:02:42)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  35083 bytes, from 2015-04-12 15:04:03)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  22094 bytes, from 2015-05-12 12:45:23)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2014-10-31 16:48:57)
 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  26848 bytes, from 2015-01-13 23:55:57)
-- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (   8253 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  29012 bytes, from 2015-05-12 12:45:23)
+- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (  10416 bytes, from 2015-05-12 12:45:23)
 
 Copyright (C) 2013 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
index 1d39174d91fba3455b03a5a0c4654ff7bc779750..153fc487d683c7310f4b1b4bb9f1f748ff9f0016 100644 (file)
@@ -10,17 +10,17 @@ git clone https://github.com/freedreno/envytools.git
 The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2014-12-05 15:34:49)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20908 bytes, from 2014-12-08 16:13:00)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2357 bytes, from 2014-12-08 16:13:00)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  27208 bytes, from 2015-01-13 23:56:11)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20915 bytes, from 2015-03-24 22:05:22)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2352 bytes, from 2015-04-12 15:02:42)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  35083 bytes, from 2015-04-12 15:04:03)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  22094 bytes, from 2015-05-12 12:45:23)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2014-10-31 16:48:57)
 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  26848 bytes, from 2015-01-13 23:55:57)
-- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (   8253 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  29012 bytes, from 2015-05-12 12:45:23)
+- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (  10416 bytes, from 2015-05-12 12:45:23)
 
-Copyright (C) 2013-2014 by the following authors:
+Copyright (C) 2013-2015 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
 
 Permission is hereby granted, free of charge, to any person obtaining
@@ -680,18 +680,18 @@ static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val)
        return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK;
 }
 
-static inline uint32_t REG_MDP4_PIPE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; }
-#define MDP4_PIPE_FRAME_SIZE_HEIGHT__MASK                      0xffff0000
-#define MDP4_PIPE_FRAME_SIZE_HEIGHT__SHIFT                     16
-static inline uint32_t MDP4_PIPE_FRAME_SIZE_HEIGHT(uint32_t val)
+static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; }
+#define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK               0xffff0000
+#define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT              16
+static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val)
 {
-       return ((val) << MDP4_PIPE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_FRAME_SIZE_HEIGHT__MASK;
+       return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK;
 }
-#define MDP4_PIPE_FRAME_SIZE_WIDTH__MASK                       0x0000ffff
-#define MDP4_PIPE_FRAME_SIZE_WIDTH__SHIFT                      0
-static inline uint32_t MDP4_PIPE_FRAME_SIZE_WIDTH(uint32_t val)
+#define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK                        0x0000ffff
+#define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT               0
+static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val)
 {
-       return ((val) << MDP4_PIPE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_FRAME_SIZE_WIDTH__MASK;
+       return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK;
 }
 
 static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; }
index b9a4ded6e400d089a92977f3fa69b0e19f7984a5..50e17527e2e56f80bda717d1588a8eda1891e0f7 100644 (file)
@@ -8,9 +8,17 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml            (  29312 bytes, from 2015-03-23 21:18:48)
-- /local/mnt2/workspace2/sviau/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2014-06-02 18:31:15)
-- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml      (   2357 bytes, from 2015-03-23 20:38:49)
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2014-12-05 15:34:49)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20915 bytes, from 2015-03-24 22:05:22)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2352 bytes, from 2015-04-12 15:02:42)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  35083 bytes, from 2015-04-12 15:04:03)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  22094 bytes, from 2015-05-12 12:45:23)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2014-10-31 16:48:57)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  29012 bytes, from 2015-05-12 12:45:23)
+- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (  10416 bytes, from 2015-05-12 12:45:23)
 
 Copyright (C) 2013-2015 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -120,6 +128,21 @@ enum mdp5_data_format {
        DATA_FORMAT_YUV = 1,
 };
 
+enum mdp5_block_size {
+       BLOCK_SIZE_64 = 0,
+       BLOCK_SIZE_128 = 1,
+};
+
+enum mdp5_rotate_mode {
+       ROTATE_0 = 0,
+       ROTATE_90 = 1,
+};
+
+enum mdp5_chroma_downsample_method {
+       DS_MTHD_NO_PIXEL_DROP = 0,
+       DS_MTHD_PIXEL_DROP = 1,
+};
+
 #define MDP5_IRQ_WB_0_DONE                                     0x00000001
 #define MDP5_IRQ_WB_1_DONE                                     0x00000002
 #define MDP5_IRQ_WB_2_DONE                                     0x00000010
@@ -314,19 +337,19 @@ static inline uint32_t MDP5_MDP_IGC_LUT_REG_VAL(uint32_t val)
 #define MDP5_MDP_IGC_LUT_REG_DISABLE_PIPE_1                    0x20000000
 #define MDP5_MDP_IGC_LUT_REG_DISABLE_PIPE_2                    0x40000000
 
-#define REG_MDP5_SPLIT_DPL_EN                                  0x000003f4
+static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_EN(uint32_t i0) { return 0x000002f4 + __offset_MDP(i0); }
 
-#define REG_MDP5_SPLIT_DPL_UPPER                               0x000003f8
-#define MDP5_SPLIT_DPL_UPPER_SMART_PANEL                       0x00000002
-#define MDP5_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN              0x00000004
-#define MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX                  0x00000010
-#define MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX                  0x00000100
+static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_UPPER(uint32_t i0) { return 0x000002f8 + __offset_MDP(i0); }
+#define MDP5_MDP_SPLIT_DPL_UPPER_SMART_PANEL                   0x00000002
+#define MDP5_MDP_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN          0x00000004
+#define MDP5_MDP_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX              0x00000010
+#define MDP5_MDP_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX              0x00000100
 
-#define REG_MDP5_SPLIT_DPL_LOWER                               0x000004f0
-#define MDP5_SPLIT_DPL_LOWER_SMART_PANEL                       0x00000002
-#define MDP5_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN              0x00000004
-#define MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC                     0x00000010
-#define MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC                     0x00000100
+static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_LOWER(uint32_t i0) { return 0x000003f0 + __offset_MDP(i0); }
+#define MDP5_MDP_SPLIT_DPL_LOWER_SMART_PANEL                   0x00000002
+#define MDP5_MDP_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN          0x00000004
+#define MDP5_MDP_SPLIT_DPL_LOWER_INTF1_TG_SYNC                 0x00000010
+#define MDP5_MDP_SPLIT_DPL_LOWER_INTF2_TG_SYNC                 0x00000100
 
 static inline uint32_t __offset_CTL(uint32_t idx)
 {
@@ -782,7 +805,7 @@ static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
 #define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB                  0x00040000
 #define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK                  0x00180000
 #define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT                 19
-static inline uint32_t MDP5_PIPE_SRC_FORMAT_NUM_PLANES(enum mdp_sspp_fetch_type val)
+static inline uint32_t MDP5_PIPE_SRC_FORMAT_NUM_PLANES(enum mdp_fetch_type val)
 {
        return ((val) << MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT) & MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK;
 }
@@ -1234,6 +1257,351 @@ static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x000000
 
 static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0); }
 
+static inline uint32_t __offset_WB(uint32_t idx)
+{
+       switch (idx) {
+               default: return INVALID_IDX(idx);
+       }
+}
+static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
+
+static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
+#define MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK                     0x00000003
+#define MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT                    0
+static inline uint32_t MDP5_WB_DST_FORMAT_DSTC0_OUT(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK;
+}
+#define MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK                     0x0000000c
+#define MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT                    2
+static inline uint32_t MDP5_WB_DST_FORMAT_DSTC1_OUT(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK;
+}
+#define MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK                     0x00000030
+#define MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT                    4
+static inline uint32_t MDP5_WB_DST_FORMAT_DSTC2_OUT(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK;
+}
+#define MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK                     0x000000c0
+#define MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT                    6
+static inline uint32_t MDP5_WB_DST_FORMAT_DSTC3_OUT(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK;
+}
+#define MDP5_WB_DST_FORMAT_DSTC3_EN                            0x00000100
+#define MDP5_WB_DST_FORMAT_DST_BPP__MASK                       0x00000600
+#define MDP5_WB_DST_FORMAT_DST_BPP__SHIFT                      9
+static inline uint32_t MDP5_WB_DST_FORMAT_DST_BPP(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_FORMAT_DST_BPP__SHIFT) & MDP5_WB_DST_FORMAT_DST_BPP__MASK;
+}
+#define MDP5_WB_DST_FORMAT_PACK_COUNT__MASK                    0x00003000
+#define MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT                   12
+static inline uint32_t MDP5_WB_DST_FORMAT_PACK_COUNT(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT) & MDP5_WB_DST_FORMAT_PACK_COUNT__MASK;
+}
+#define MDP5_WB_DST_FORMAT_DST_ALPHA_X                         0x00004000
+#define MDP5_WB_DST_FORMAT_PACK_TIGHT                          0x00020000
+#define MDP5_WB_DST_FORMAT_PACK_ALIGN_MSB                      0x00040000
+#define MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK                  0x00180000
+#define MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT                 19
+static inline uint32_t MDP5_WB_DST_FORMAT_WRITE_PLANES(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT) & MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK;
+}
+#define MDP5_WB_DST_FORMAT_DST_DITHER_EN                       0x00400000
+#define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK               0x03800000
+#define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT              23
+static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK;
+}
+#define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK               0x3c000000
+#define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT              26
+static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SITE(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK;
+}
+#define MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK                  0xc0000000
+#define MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT                 30
+static inline uint32_t MDP5_WB_DST_FORMAT_FRAME_FORMAT(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT) & MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK;
+}
+
+static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); }
+#define MDP5_WB_DST_OP_MODE_BWC_ENC_EN                         0x00000001
+#define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK                   0x00000006
+#define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT                  1
+static inline uint32_t MDP5_WB_DST_OP_MODE_BWC_ENC_OP(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT) & MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK;
+}
+#define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK                   0x00000010
+#define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT                  4
+static inline uint32_t MDP5_WB_DST_OP_MODE_BLOCK_SIZE(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT) & MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK;
+}
+#define MDP5_WB_DST_OP_MODE_ROT_MODE__MASK                     0x00000020
+#define MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT                    5
+static inline uint32_t MDP5_WB_DST_OP_MODE_ROT_MODE(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT) & MDP5_WB_DST_OP_MODE_ROT_MODE__MASK;
+}
+#define MDP5_WB_DST_OP_MODE_ROT_EN                             0x00000040
+#define MDP5_WB_DST_OP_MODE_CSC_EN                             0x00000100
+#define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK          0x00000200
+#define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT         9
+static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
+}
+#define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK          0x00000400
+#define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT         10
+static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
+}
+#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_EN               0x00000800
+#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK     0x00001000
+#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT    12
+static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK;
+}
+#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK     0x00002000
+#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT    13
+static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK;
+}
+#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK     0x00004000
+#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT    14
+static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK;
+}
+
+static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(i0); }
+#define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK                        0x00000003
+#define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT               0
+static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT0(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK;
+}
+#define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK                        0x00000300
+#define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT               8
+static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT1(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK;
+}
+#define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK                        0x00030000
+#define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT               16
+static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT2(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK;
+}
+#define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK                        0x03000000
+#define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT               24
+static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT3(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK;
+}
+
+static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); }
+
+static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); }
+
+static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); }
+
+static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); }
+
+static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0); }
+#define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK                        0x0000ffff
+#define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT               0
+static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK;
+}
+#define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK                        0xffff0000
+#define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT               16
+static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK;
+}
+
+static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0); }
+#define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK                        0x0000ffff
+#define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT               0
+static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK;
+}
+#define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK                        0xffff0000
+#define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT               16
+static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(uint32_t val)
+{
+       return ((val) << MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK;
+}
+
+static inline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_WB(i0); }
+
+static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_WB(i0); }
+
+static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_WB(i0); }
+
+static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_WB(i0); }
+
+static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_WB(i0); }
+
+static inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(i0); }
+
+static inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB(i0); }
+
+static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset_WB(i0); }
+
+static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset_WB(i0); }
+
+static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset_WB(i0); }
+
+static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset_WB(i0); }
+
+static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); }
+#define MDP5_WB_OUT_SIZE_DST_W__MASK                           0x0000ffff
+#define MDP5_WB_OUT_SIZE_DST_W__SHIFT                          0
+static inline uint32_t MDP5_WB_OUT_SIZE_DST_W(uint32_t val)
+{
+       return ((val) << MDP5_WB_OUT_SIZE_DST_W__SHIFT) & MDP5_WB_OUT_SIZE_DST_W__MASK;
+}
+#define MDP5_WB_OUT_SIZE_DST_H__MASK                           0xffff0000
+#define MDP5_WB_OUT_SIZE_DST_H__SHIFT                          16
+static inline uint32_t MDP5_WB_OUT_SIZE_DST_H(uint32_t val)
+{
+       return ((val) << MDP5_WB_OUT_SIZE_DST_H__SHIFT) & MDP5_WB_OUT_SIZE_DST_H__MASK;
+}
+
+static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0); }
+
+static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_WB(i0); }
+#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK              0x00001fff
+#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT             0
+static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(uint32_t val)
+{
+       return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK;
+}
+#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK              0x1fff0000
+#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT             16
+static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(uint32_t val)
+{
+       return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK;
+}
+
+static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_WB(i0); }
+#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK              0x00001fff
+#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT             0
+static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(uint32_t val)
+{
+       return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK;
+}
+#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK              0x1fff0000
+#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT             16
+static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(uint32_t val)
+{
+       return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK;
+}
+
+static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_WB(i0); }
+#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK              0x00001fff
+#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT             0
+static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(uint32_t val)
+{
+       return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK;
+}
+#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK              0x1fff0000
+#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT             16
+static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(uint32_t val)
+{
+       return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK;
+}
+
+static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_WB(i0); }
+#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK              0x00001fff
+#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT             0
+static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(uint32_t val)
+{
+       return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK;
+}
+#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK              0x1fff0000
+#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT             16
+static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(uint32_t val)
+{
+       return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK;
+}
+
+static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_WB(i0); }
+#define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK              0x00001fff
+#define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT             0
+static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(uint32_t val)
+{
+       return ((val) << MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK;
+}
+
+static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
+#define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK               0x000000ff
+#define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT              0
+static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(uint32_t val)
+{
+       return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK;
+}
+#define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK                        0x0000ff00
+#define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT               8
+static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(uint32_t val)
+{
+       return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK;
+}
+
+static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
+#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK              0x000000ff
+#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT             0
+static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(uint32_t val)
+{
+       return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK;
+}
+#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK               0x0000ff00
+#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT              8
+static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(uint32_t val)
+{
+       return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK;
+}
+
+static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
+#define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK               0x000001ff
+#define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT              0
+static inline uint32_t MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(uint32_t val)
+{
+       return ((val) << MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK;
+}
+
+static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
+#define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK              0x000001ff
+#define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT             0
+static inline uint32_t MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(uint32_t val)
+{
+       return ((val) << MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK;
+}
+
 static inline uint32_t __offset_INTF(uint32_t idx)
 {
        switch (idx) {
index e4e89567f51d51924f8ff6c4804125b7aa131c87..f4eeaf032f2e1f755716c35142a1735a74441e0e 100644 (file)
@@ -281,22 +281,22 @@ int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder,
         * start signal for the slave encoder
         */
        if (intf_num == 1)
-               data |= MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX;
+               data |= MDP5_MDP_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX;
        else if (intf_num == 2)
-               data |= MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX;
+               data |= MDP5_MDP_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX;
        else
                return -EINVAL;
 
        /* Smart Panel, Sync mode */
-       data |= MDP5_SPLIT_DPL_UPPER_SMART_PANEL;
+       data |= MDP5_MDP_SPLIT_DPL_UPPER_SMART_PANEL;
 
        /* Make sure clocks are on when connectors calling this function. */
        mdp5_enable(mdp5_kms);
-       mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, data);
+       mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_UPPER(0), data);
 
-       mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER,
-                       MDP5_SPLIT_DPL_LOWER_SMART_PANEL);
-       mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1);
+       mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_LOWER(0),
+                       MDP5_MDP_SPLIT_DPL_LOWER_SMART_PANEL);
+       mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_EN(0), 1);
        mdp5_disable(mdp5_kms);
 
        return 0;
index 1188f4bf1e603853e1d872dd0ad06ee55de9cceb..f58c9b63a710882c6e6721798b8e96f20b518fe2 100644 (file)
@@ -304,9 +304,9 @@ int mdp5_encoder_set_split_display(struct drm_encoder *encoder,
         * to use the master's enable signal for the slave encoder.
         */
        if (intf_num == 1)
-               data |= MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC;
+               data |= MDP5_MDP_SPLIT_DPL_LOWER_INTF2_TG_SYNC;
        else if (intf_num == 2)
-               data |= MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC;
+               data |= MDP5_MDP_SPLIT_DPL_LOWER_INTF1_TG_SYNC;
        else
                return -EINVAL;
 
@@ -315,9 +315,9 @@ int mdp5_encoder_set_split_display(struct drm_encoder *encoder,
        mdp5_write(mdp5_kms, REG_MDP5_MDP_SPARE_0(0),
                MDP5_MDP_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN);
        /* Dumb Panel, Sync mode */
-       mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, 0);
-       mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, data);
-       mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1);
+       mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_UPPER(0), 0);
+       mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_LOWER(0), data);
+       mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_EN(0), 1);
        mdp5_disable(mdp5_kms);
 
        return 0;
index a1d35f162c7f85d0ad827e9fe967a871e9accb44..641d036c5bcb620185e9bf3caaf2f120f7013168 100644 (file)
@@ -10,17 +10,17 @@ git clone https://github.com/freedreno/envytools.git
 The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2014-12-05 15:34:49)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20908 bytes, from 2014-12-08 16:13:00)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2357 bytes, from 2014-12-08 16:13:00)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  27208 bytes, from 2015-01-13 23:56:11)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20915 bytes, from 2015-03-24 22:05:22)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2352 bytes, from 2015-04-12 15:02:42)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  35083 bytes, from 2015-04-12 15:04:03)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  22094 bytes, from 2015-05-12 12:45:23)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2014-10-31 16:48:57)
 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  26848 bytes, from 2015-01-13 23:55:57)
-- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (   8253 bytes, from 2014-12-08 16:13:00)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  29012 bytes, from 2015-05-12 12:45:23)
+- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (  10416 bytes, from 2015-05-12 12:45:23)
 
-Copyright (C) 2013-2014 by the following authors:
+Copyright (C) 2013-2015 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
 
 Permission is hereby granted, free of charge, to any person obtaining
@@ -52,7 +52,7 @@ enum mdp_chroma_samp_type {
        CHROMA_420 = 3,
 };
 
-enum mdp_sspp_fetch_type {
+enum mdp_fetch_type {
        MDP_PLANE_INTERLEAVED = 0,
        MDP_PLANE_PLANAR = 1,
        MDP_PLANE_PSEUDO_PLANAR = 2,
index 5ae4039d68e498c5b37361811db5e50a2a56dc6a..2d3428cb74d024fda97d64a53ae02f8b6d7c4daf 100644 (file)
@@ -88,7 +88,7 @@ struct mdp_format {
        uint8_t unpack[4];
        bool alpha_enable, unpack_tight;
        uint8_t cpp, unpack_count;
-       enum mdp_sspp_fetch_type fetch_type;
+       enum mdp_fetch_type fetch_type;
        enum mdp_chroma_samp_type chroma_sample;
 };
 #define to_mdp_format(x) container_of(x, struct mdp_format, base)