ARM Remove a bit of dead code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152061 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td
index b0ab9941f96ae83a3713b77dde4ae8ec2ce56c15..1fa3979b3d3bf7dbd32330fba309a51b876afd1f 100644 (file)
--- a/lib/Target/ARM/ARMInstrNEON.td
+++ b/lib/Target/ARM/ARMInstrNEON.td
@@ -89,15 +89,6 @@ def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
   let ParserMatchClass = VecListOneDAsmOperand;
 }
 // Register list of two sequential D registers.
-def VecListTwoDAsmOperand : AsmOperandClass {
-  let Name = "VecListTwoD";
-  let ParserMethod = "parseVectorList";
-  let RenderMethod = "addVecListOperands";
-}
-def VecListTwoD : RegisterOperand<DPR, "printVectorListTwo"> {
-  let ParserMatchClass = VecListTwoDAsmOperand;
-}
-// FIXME: Replace all VecListTwoD with VecListDPair
 def VecListDPairAsmOperand : AsmOperandClass {
   let Name = "VecListDPair";
   let ParserMethod = "parseVectorList";

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 845f0a329965fbcf5a98293794a1c1341f9540cf..b3e7e45b8c0d10ee160ae644b72087782110cba5 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -1085,11 +1085,6 @@ public:
     return VectorList.Count == 1;
   }
 
-  bool isVecListTwoD() const {
-    if (!isSingleSpacedVectorList()) return false;
-    return VectorList.Count == 2;
-  }
-
   bool isVecListDPair() const {
     if (!isSingleSpacedVectorList()) return false;
     return (ARMMCRegisterClasses[ARM::DPairRegClassID]