rk312x dts: add fb/screen/lcdc/lvds dt node
authorzwl <zwl@rockchips.com>
Tue, 29 Jul 2014 03:30:00 +0000 (11:30 +0800)
committerzwl <zwl@rockchips.com>
Tue, 29 Jul 2014 03:30:26 +0000 (11:30 +0800)
arch/arm/boot/dts/rk3126-fpga.dts
arch/arm/boot/dts/rk3126-sdk.dts
arch/arm/boot/dts/rk312x-pinctrl.dtsi
arch/arm/boot/dts/rk312x.dtsi

index 8eca906530170b520859cdb151e0fc997a156b68..01e7dc1eec0fae32c46a28b4e4e49ad2003f6f11 100755 (executable)
        fiq-debugger {
                status = "okay";
        };
+
+       &fb {
+               rockchip,disp-mode = <ONE_DUAL>;
+        };
+
+       &rk_screen {
+               display-timings = <&disp_timings>;
+       };
+
+       &lcdc {
+               status = "okay";
+       };
+
 };
index 87e4b706cad4f76c22d1bef22649dcae7c48071e..d57bf64a61b42fa00d298824742854a5ceb7ee66 100755 (executable)
        };
 };
 
+       &fb {
+               rockchip,disp-mode = <ONE_DUAL>;
+               rockchip,uboot-logo-on = <0>;
+       };
+
+       &rk_screen {
+               //display-timings = <&disp_timings>;
+       };
+
+       &lcdc {
+               status = "okay";
+
+               power_ctr: power_ctr {
+                       rockchip,debug = <0>;
+                       lcd_en: lcd_en {
+                               rockchip,power_type = <GPIO>;
+                               gpios = <&gpio1 GPIO_B3 GPIO_ACTIVE_HIGH>;
+                               rockchip,delay = <10>;
+                       };
+               };
+       };
+
 /include/ "rk818.dtsi"
 &rk818 {
        gpios =<&gpio1 GPIO_B1 GPIO_ACTIVE_HIGH>,<&gpio1 GPIO_A1 GPIO_ACTIVE_LOW>;
index 91e1e7ab570e51a6a43ff115719bf9f71816bc7e..7a189857da9eba15519a87449cb5640117db31b0 100755 (executable)
 
                };
 
+               gpio2_lcdc0 {
+                       lcdc0_lcdc:lcdc0-lcdc {
+                               rockchip,pins =
+                                               <LCDC0_DCLK>,
+                                               <LCDC0_DEN>,
+                                               <LCDC0_HSYNC>,
+                                               <LCDC0_VSYNC>;
+                               rockchip,pull = <VALUE_PULL_DISABLE>;
+                               rockchip,drive = <VALUE_DRV_DEFAULT>;
+                       };
+
+                       lcdc0_gpio:lcdc0-gpio {
+                               rockchip,pins =
+                                               <FUNC_TO_GPIO(LCDC0_DCLK)>,
+                                               <FUNC_TO_GPIO(LCDC0_DEN)>,
+                                               <FUNC_TO_GPIO(LCDC0_HSYNC)>,
+                                               <FUNC_TO_GPIO(LCDC0_VSYNC)>;
+                               rockchip,pull = <VALUE_PULL_DISABLE>;
+                               rockchip,drive = <VALUE_DRV_DEFAULT>;
+                       };
+
+               };
 
                //to add 
 
index c25b9237113bdca61c31216ea606a42cfa7945ee..f4afa4422c21447d59361a8b81578bdf65861c6e 100755 (executable)
@@ -2,6 +2,7 @@
 #include <dt-bindings/suspend/rockchip-pm.h>
 #include <dt-bindings/sensor-dev.h>
 #include <dt-bindings/clock/rk_system_status.h>
+#include <dt-bindings/rkfb/rk_fb.h>
 
 #include "skeleton.dtsi"
 #include "rk312x-clocks.dtsi"
@@ -19,6 +20,7 @@
                i2c1 = &i2c1;
                i2c2 = &i2c2;
                i2c3 = &i2c3;
+               lcdc = &lcdc;
        //      spi0 = &spi0;
        };
 
                 status = "disabled";
         };
 
+       fb: fb{
+               compatible = "rockchip,rk-fb";
+               rockchip,disp-mode = <ONE_DUAL>;
+       };
+
+       rk_screen: rk_screen{
+               compatible = "rockchip,screen";
+       };
+
+       lvds: lvds@20038000 {
+               compatible = "rockchip,rk31xx-lvds";
+               reg = <0x20038000 0x4000>;
+               clocks = <&clk_gates5 0>;
+               clock-names = "pclk_lvds";
+       };
+
+       lcdc: lcdc@1010e000 {
+               compatible = "rockchip,rk312x-lcdc";
+               rockchip,prop = <PRMRY>;
+               reg = <0x1010e000 0x2000>;
+               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+               pinctrl-names = "default", "gpio";
+               pinctrl-0 = <&lcdc0_lcdc>;
+               pinctrl-1 = <&lcdc0_gpio>;
+               clocks = <&clk_gates6 0>, <&dclk_lcdc0>, <&clk_gates6 1>, <&sclk_lcdc0>;
+               clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk";
+               rockchip,iommu-enabled = <1>;
+               status = "disabled";
+       };
+
         vpu: vpu_service@10104000 {
                compatible = "vpu_service";
                reg = <0x10104000 0x800>;