drm/rockchip: vop: add dual-channel dsi support

Change-Id: Ibddc064c6c588d0733a238b08b7ba4c5bd4518a2
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index 4379bb971844726aaab39abc3b0bc0d2c5ce3216..8b23b30472396519a000367bf168880b58f89e5a 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -94,6 +94,7 @@ struct rockchip_crtc_state {
        int dsp_layer_sel;
        int output_type;
        int output_mode;
+       int output_flags;
        int bus_format;
 };
 

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 80438d2ec50e7118ebe5899da1edf0d07689ec51..174002ca0f1b65f7f462d8d133fd44112fd7d47e 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1733,6 +1733,10 @@ static void vop_crtc_enable(struct drm_crtc *crtc)
                VOP_CTRL_SET(vop, mipi_en, 1);
                VOP_CTRL_SET(vop, mipi_pin_pol, val);
                VOP_CTRL_SET(vop, mipi_dclk_pol, 1);
+               if (s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL)
+                       VOP_CTRL_SET(vop, mipi_dual_channel_en, 1);
+               else
+                       VOP_CTRL_SET(vop, mipi_dual_channel_en, 0);
                break;
        case DRM_MODE_CONNECTOR_DisplayPort:
                VOP_CTRL_SET(vop, dp_dclk_pol, 0);

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 0782d1b3fb297719450c190da8f7e6491e8e0278..466137550f2349abd1eef921fc2d2a77fa2cbc53 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -23,6 +23,8 @@
 #define VOP_MAJOR(version)     ((version) >> 8)
 #define VOP_MINOR(version)     ((version) & 0xff)
 
+#define ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL       BIT(0)
+
 #define AFBDC_FMT_RGB565       0x0
 #define AFBDC_FMT_U8U8U8U8     0x5
 #define AFBDC_FMT_U8U8U8       0x4
@@ -110,6 +112,7 @@ struct vop_ctrl {
        struct vop_reg edp_en;
        struct vop_reg hdmi_en;
        struct vop_reg mipi_en;
+       struct vop_reg mipi_dual_channel_en;
        struct vop_reg dp_en;
        struct vop_reg dclk_pol;
        struct vop_reg pin_pol;

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index e252738d19aedfb6dd688323d15c703948c503d0..8fb1cff0bc5596d3199120d87c4c264ca82bd375 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -196,6 +196,7 @@ static const struct vop_ctrl rk3288_ctrl_data = {
        .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
        .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
        .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
+       .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3),
        .dclk_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0x1, 7, 3, 0, 1),
        .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0x7, 4, 3, 0, 1),
        .dp_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL0, 0x1, 19, 3, 0, 1),