rk3026: usb: config usb fifo for device mode
authorlyz <lyz@rock-chips.com>
Thu, 1 Aug 2013 15:39:25 +0000 (23:39 +0800)
committerlyz <lyz@rock-chips.com>
Thu, 1 Aug 2013 15:39:25 +0000 (23:39 +0800)
drivers/usb/dwc_otg/dwc_otg_cil.c

index 5ea7ffa02a27d66929671fc3e0622367ca07c643..9f02d63ee66f77056b07d444bc6684e4ef131638 100755 (executable)
@@ -743,6 +743,17 @@ void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if)
     dwc_write_reg32( &global_regs->dptxfsiz_dieptxf[3], 0x00800330 );   //ep7 tx fifo 128*4Byte
     dwc_write_reg32( &global_regs->dptxfsiz_dieptxf[4], 0x001003b0 );   //ep9 tx fifo 16*4Byte
 #endif
+#ifdef CONFIG_ARCH_RK3026  
+        /* Configure data FIFO sizes, RK30 otg has 0x3cc dwords total */
+    dwc_write_reg32( &global_regs->grxfsiz, 0x00000120 );
+    dwc_write_reg32( &global_regs->gnptxfsiz, 0x00100120 );             //ep0 tx fifo 
+    dwc_write_reg32( &global_regs->dptxfsiz_dieptxf[0], 0x01000130 );   //ep1 tx fifo 256*4Byte
+    dwc_write_reg32( &global_regs->dptxfsiz_dieptxf[1], 0x00800230 );   //ep3 tx fifo 128*4Byte
+    dwc_write_reg32( &global_regs->dptxfsiz_dieptxf[2], 0x008002b0 );   //ep5 tx fifo 128*4Byte
+    dwc_write_reg32( &global_regs->dptxfsiz_dieptxf[3], 0x00800330 );   //ep7 tx fifo 128*4Byte
+    dwc_write_reg32( &global_regs->dptxfsiz_dieptxf[4], 0x001003b0 );   //ep9 tx fifo 16*4Byte
+#endif
+
        if(_core_if->en_multiple_tx_fifo && _core_if->dma_enable)
        {
                dev_if->non_iso_tx_thr_en = _core_if->core_params->thr_ctl & 0x1;