} else if (AArch64::FPR16RegClass.contains(DestReg, SrcReg)) {
// The copy of two FPR16 registers is implemented by the copy of two FPR32
const TargetRegisterInfo *TRI = &getRegisterInfo();
- unsigned Dst = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_16,
+ unsigned Dst = TRI->getMatchingSuperReg(DestReg, AArch64::sub_16,
&AArch64::FPR32RegClass);
- unsigned Src = TRI->getMatchingSuperReg(DestReg, AArch64::sub_16,
+ unsigned Src = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_16,
&AArch64::FPR32RegClass);
BuildMI(MBB, I, DL, get(AArch64::FMOVss), Dst)
.addReg(Src);
%vecext1 = extractelement <1 x i64> %y, i32 0
%vecinit2 = insertelement <2 x i64> %vecinit, i64 %vecext1, i32 1
ret <2 x i64> %vecinit2
-}
\ No newline at end of file
+}
+
+declare <1 x i16> @llvm.aarch64.neon.vsqadd.v1i16(<1 x i16>, <1 x i16>)
+
+define <1 x i16> @test_copy_FPR16_FPR16(<1 x i16> %a, <1 x i16> %b) {
+; CHECK-LABEL: test_copy_FPR16_FPR16:
+; CHECK: usqadd h1, h0
+; CHECK-NEXT: fmov s0, s1
+entry:
+ %vsqadd2.i = call <1 x i16> @llvm.aarch64.neon.vsqadd.v1i16(<1 x i16> %b, <1 x i16> %a)
+ ret <1 x i16> %vsqadd2.i
+}