/*
* SRAM memory whereabouts
*/
-#define SRAM_CODE_OFFSET 0xff400000
-#define SRAM_CODE_END 0xff401fff
-#define SRAM_DATA_OFFSET 0xff402000
-#define SRAM_DATA_END 0xff403fff
+#define SRAM_CODE_OFFSET 0xFEF00000
+#define SRAM_CODE_END 0xFEF01FFF
+#define SRAM_DATA_OFFSET 0xFEF02000
+#define SRAM_DATA_END 0xFEF03FFF
#endif
#include <asm/sizes.h>
-/* defines */
-#define SZ_22K 0x5800
-/*IOÓ³É䷽ʽ¶¨Ò壬ÒÔÎïÀíµØÖ·0x20000000Ϊ»ùµØÖ·
- *ºÍÒÔ0x10000000Ϊ»ùµØÖ··ÖÁíÓ³ÉäΪ£º0xf5000000,
- *0xf4000000
+/*
+ * RK29 IO memory map:
+ *
+ * Virt Phys Size What
+ * ---------------------------------------------------------------------------
+ * 10000000 1M CPU L1 AXI Interconnect
+ * FEA00000 10100000 1200K
+ * 10300000 1M Peri AXI Interconnect
+ * FEC00000 10500000 16K NANDC
+ * 11000000 1M SMC Bank0
+ * 12000000 1M SMC Bank1
+ * 15000000 1M CPU L2 AXI Interconnect
+ * FED00000 20000000 640K APB
+ * FEF00000 0 16K SRAM
*/
-
-#define RK29_ADDR_BASE1 0xF5000000
-#define RK29_ADDR_BASE0 0xF4000000
+#define RK29_ADDR_BASE0 0xFEA00000
+#define RK29_ADDR_BASE1 0xFED00000
#define RK29_SDRAM_PHYS 0x60000000U
#define RK29_AXI1_PHYS 0x10000000
#define RK29_ARBITER1_PHYS 0x10228000
#define RK29_ARBITER1_SIZE SZ_16K
#define RK29_PERI_AXI_BUS0_PHYS 0x10300000
+
#define RK29_NANDC_PHYS 0x10500000
-#define RK29_NANDC_BASE (RK29_ADDR_BASE0+0x500000)
+#define RK29_NANDC_BASE 0xFEC00000
#define RK29_NANDC_SIZE SZ_16K
//CPU AXI 1 APB