Make typesafe that which isn't: FCMOVxx

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24536 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index debc41dfcdc3b681c7d8eb515b21434f291a3529..6f0ca41450166697b15fc25133659644e397700e 100644 (file)
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -335,6 +335,7 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
       unsigned Opc = Alpha::WTF;
       ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
       bool rev = false;
+      bool isNE = false;
       switch(CC) {
       default: N->dump(); assert(0 && "Unknown FP comparison!");
       case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
@@ -342,13 +343,17 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
       case ISD::SETLE: Opc = Alpha::CMPTLE; break;
       case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
       case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
-        //case ISD::SETNE: Opc = Alpha::CMPTEQ; inv = true; break;
+      case ISD::SETNE: Opc = Alpha::CMPTEQ; isNE = true; break;
       };
       SDOperand tmp1 = Select(N->getOperand(0)),
         tmp2 = Select(N->getOperand(1));
       SDOperand cmp = CurDAG->getTargetNode(Opc, MVT::f64, 
                                             rev?tmp2:tmp1,
                                             rev?tmp1:tmp2);
+      if (isNE) 
+        cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, cmp, 
+                                    CurDAG->getRegister(Alpha::F31, MVT::f64));
+      
       SDOperand LD;
       if (AlphaLowering.hasITOF()) {
         LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, cmp);
@@ -372,6 +377,7 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
   case ISD::SELECT:
     if (MVT::isFloatingPoint(N->getValueType(0))) {
       //move int to fp
+      bool isDouble = N->getValueType(0) == MVT::f64;
       SDOperand LD,
         cond = Select(N->getOperand(0)),
         TV = Select(N->getOperand(1)),
@@ -389,12 +395,12 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
                                    CurDAG->getRegister(Alpha::R31, MVT::i64),
                                    ST);
       }
-      SDOperand FP = CurDAG->getTargetNode(Alpha::FCMOVEQ, MVT::f64, TV, FV, LD);
+      SDOperand FP = CurDAG->getTargetNode(isDouble?Alpha::FCMOVEQT:Alpha::FCMOVEQS,
+                                           MVT::f64, TV, FV, LD);
       return FP;
     }
     break;
 
-
   }
 
   return SelectCode(Op);

diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 3ebb046ff9fe064c80c848e2cb88446947ca03a9..e86e25bf772d07327de5e0e828aa2304589b9c89 100644 (file)
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -98,8 +98,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
   setOperationAction(ISD::FCOS , MVT::f32, Expand);
   setOperationAction(ISD::FSQRT, MVT::f32, Expand);
 
-  //Doesn't work yet
-  setOperationAction(ISD::SETCC, MVT::f32,   Promote);
+  setOperationAction(ISD::SETCC, MVT::f32, Promote);
 
   // We don't have line number support yet.
   setOperationAction(ISD::LOCATION, MVT::Other, Expand);

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 415cd2ed8b91a6d3bf9aad275bf80994ea7b0a16..a5cc3ac73725752788cc9b42c1a834334a936e3d 100644 (file)
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1317,7 +1317,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
 
         bool invTest = false;
         unsigned Tmp3;
-
+        bool isD = CC.getOperand(0).getValueType() == MVT::f64;
         ConstantFPSDNode *CN;
         if ((CN = dyn_cast<ConstantFPSDNode>(CC.getOperand(1)))
             && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
@@ -1332,21 +1332,31 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
         {
           unsigned Tmp1 = SelectExpr(CC.getOperand(0));
           unsigned Tmp2 = SelectExpr(CC.getOperand(1));
-          bool isD = CC.getOperand(0).getValueType() == MVT::f64;
           Tmp3 = MakeReg(isD ? MVT::f64 : MVT::f32);
           BuildMI(BB, isD ? Alpha::SUBT : Alpha::SUBS, 2, Tmp3)
             .addReg(Tmp1).addReg(Tmp2);
         }
 
-        switch (cast<CondCodeSDNode>(CC.getOperand(2))->get()) {
-        default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
-        case ISD::SETEQ: Opc = invTest ? Alpha::FCMOVNE : Alpha::FCMOVEQ; break;
-        case ISD::SETLT: Opc = invTest ? Alpha::FCMOVGT : Alpha::FCMOVLT; break;
-        case ISD::SETLE: Opc = invTest ? Alpha::FCMOVGE : Alpha::FCMOVLE; break;
-        case ISD::SETGT: Opc = invTest ? Alpha::FCMOVLT : Alpha::FCMOVGT; break;
-        case ISD::SETGE: Opc = invTest ? Alpha::FCMOVLE : Alpha::FCMOVGE; break;
-        case ISD::SETNE: Opc = invTest ? Alpha::FCMOVEQ : Alpha::FCMOVNE; break;
-        }
+        if(isD)
+          switch (cast<CondCodeSDNode>(CC.getOperand(2))->get()) {
+          default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
+          case ISD::SETEQ: Opc = invTest ? Alpha::FCMOVNET : Alpha::FCMOVEQT; break;
+          case ISD::SETLT: Opc = invTest ? Alpha::FCMOVGTT : Alpha::FCMOVLTT; break;
+          case ISD::SETLE: Opc = invTest ? Alpha::FCMOVGET : Alpha::FCMOVLET; break;
+          case ISD::SETGT: Opc = invTest ? Alpha::FCMOVLTT : Alpha::FCMOVGTT; break;
+          case ISD::SETGE: Opc = invTest ? Alpha::FCMOVLET : Alpha::FCMOVGET; break;
+          case ISD::SETNE: Opc = invTest ? Alpha::FCMOVEQT : Alpha::FCMOVNET; break;
+          }
+        else
+          switch (cast<CondCodeSDNode>(CC.getOperand(2))->get()) {
+          default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
+          case ISD::SETEQ: Opc = invTest ? Alpha::FCMOVNES : Alpha::FCMOVEQS; break;
+          case ISD::SETLT: Opc = invTest ? Alpha::FCMOVGTS : Alpha::FCMOVLTS; break;
+          case ISD::SETLE: Opc = invTest ? Alpha::FCMOVGES : Alpha::FCMOVLES; break;
+          case ISD::SETGT: Opc = invTest ? Alpha::FCMOVLTS : Alpha::FCMOVGTS; break;
+          case ISD::SETGE: Opc = invTest ? Alpha::FCMOVLES : Alpha::FCMOVGES; break;
+          case ISD::SETNE: Opc = invTest ? Alpha::FCMOVEQS : Alpha::FCMOVNES; break;
+          }
         BuildMI(BB, Opc, 3, Result).addReg(FV).addReg(TV).addReg(Tmp3);
         return Result;
       }

diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td
index 8cbb11369599d167161cf204181a14eaabde85d0..a1f520a3c6e8eb77ddb98cdb8af317c320ec42ad 100644 (file)
--- a/lib/Target/Alpha/AlphaInstrInfo.td
+++ b/lib/Target/Alpha/AlphaInstrInfo.td
@@ -162,16 +162,6 @@ def CMOVNEi  : OForm4L< 0x11, 0x26, "cmovne $RCOND,$L,$RDEST">; //CMOVE if RCOND
 def : Pat<(select GPRC:$which, GPRC:$src1, GPRC:$src2),
       (CMOVEQ GPRC:$src1, GPRC:$src2, GPRC:$which)>;
 
-//conditional moves, fp
-let OperandList = (ops F8RC:$RDEST, F8RC:$RSRC2, F8RC:$RSRC, F8RC:$RCOND),
-    isTwoAddress = 1 in {
-def FCMOVEQ : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if = zero
-def FCMOVGE : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if >= zero
-def FCMOVGT : FPForm<0x17, 0x02F, "fcmovgt $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if > zero
-def FCMOVLE : FPForm<0x17, 0x02E, "fcmovle $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if <= zero
-def FCMOVLT : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RSRC,$RDEST",[]>; // FCMOVE if < zero
-def FCMOVNE : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if != zero
-}
 
 def ADDL     : OForm< 0x10, 0x00, "addl $RA,$RB,$RC",
                       [(set GPRC:$RC, (intop (add GPRC:$RA, GPRC:$RB)))]>;
@@ -555,6 +545,27 @@ def CMPTUN : FPForm<0x16, 0x5A4, "cmptun/su $RA,$RB,$RC", []>;
 }
 //TODO: Add lots more FP patterns
 
+//conditional moves, floats
+let OperandList = (ops F4RC:$RDEST, F4RC:$RSRC2, F4RC:$RSRC, F8RC:$RCOND),
+    isTwoAddress = 1 in {
+def FCMOVEQS : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if = zero
+def FCMOVGES : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if >= zero
+def FCMOVGTS : FPForm<0x17, 0x02F, "fcmovgt $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if > zero
+def FCMOVLES : FPForm<0x17, 0x02E, "fcmovle $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if <= zero
+def FCMOVLTS : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RSRC,$RDEST",[]>; // FCMOVE if < zero
+def FCMOVNES : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if != zero
+}
+//conditional moves, doubles
+let OperandList = (ops F8RC:$RDEST, F8RC:$RSRC2, F8RC:$RSRC, F8RC:$RCOND),
+    isTwoAddress = 1 in {
+def FCMOVEQT : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if = zero
+def FCMOVGET : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if >= zero
+def FCMOVGTT : FPForm<0x17, 0x02F, "fcmovgt $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if > zero
+def FCMOVLET : FPForm<0x17, 0x02E, "fcmovle $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if <= zero
+def FCMOVLTT : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RSRC,$RDEST",[]>; // FCMOVE if < zero
+def FCMOVNET : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if != zero
+}
+
 
 
 let OperandList = (ops GPRC:$RC, F4RC:$RA), Fb = 31 in