In X86DAGToDAGISel::MatchWrapper, if base or index are set, avoid matching

only if symbolic addresses are RIP relatives.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68924 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index f82e9f3514a9d60fad7d92c91a1470e65b6a7e78..bb8061fed8d487c5e84388daabb2dafebe2b568f 100644 (file)
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -787,11 +787,16 @@ bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
   bool is64Bit = Subtarget->is64Bit();
   DOUT << "Wrapper: 64bit " << is64Bit;
   DOUT << " AM "; DEBUG(AM.dump()); DOUT << "\n";
+
   // Under X86-64 non-small code model, GV (and friends) are 64-bits.
-  // Also, base and index reg must be 0 in order to use rip as base.
-  if (is64Bit && (TM.getCodeModel() != CodeModel::Small ||
-                  AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
+  if (is64Bit && (TM.getCodeModel() != CodeModel::Small))
+    return true;
+
+  // Base and index reg must be 0 in order to use rip as base.
+  bool canUsePICRel = !AM.Base.Reg.getNode() && !AM.IndexReg.getNode();
+  if (is64Bit && !canUsePICRel && TM.symbolicAddressesAreRIPRel())
     return true;
+
   if (AM.hasSymbolicDisplacement())
     return true;
   // If value is available in a register both base and index components have

diff --git a/test/CodeGen/X86/2009-04-12-picrel.ll b/test/CodeGen/X86/2009-04-12-picrel.ll
new file mode 100644 (file)
index 0000000..73062ab
--- /dev/null
+++ b/test/CodeGen/X86/2009-04-12-picrel.ll
@@ -0,0 +1,13 @@
+; RUN: llvm-as < %s | llc -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=static -code-model=small > %t
+; RUN: grep leaq %t | count 1
+
+@dst = external global [131072 x i32]
+@ptr = external global i32*
+
+define void @off01(i64 %i) nounwind {
+entry:
+       %.sum = add i64 %i, 16
+       %0 = getelementptr [131072 x i32]* @dst, i64 0, i64 %.sum
+       store i32* %0, i32** @ptr, align 8
+       ret void
+}

diff --git a/test/CodeGen/X86/abi-isel.ll b/test/CodeGen/X86/abi-isel.ll
index 5efa63cde93dbb67289009a9d4064154527472a7..f1fec3f8b94da7bb20709e05169eafa82fef13eb 100644 (file)
--- a/test/CodeGen/X86/abi-isel.ll
+++ b/test/CodeGen/X86/abi-isel.ll
@@ -43,7 +43,7 @@
 ; RUN: grep movl %t | count 91
 ; RUN: not grep addl %t
 ; RUN: not grep subl %t
-; RUN: grep leaq %t | count 93
+; RUN: grep leaq %t | count 70
 ; RUN: grep movq %t | count 56
 ; RUN: grep addq %t | count 20
 ; RUN: grep subq %t | count 14
@@ -57,7 +57,7 @@
 ; RUN: not grep @PLT %t
 ; RUN: not grep @PLTOFF %t
 ; RUN: grep {call      \\\*} %t | count 10
-; RUN: grep {%rip} %t | count 162
+; RUN: grep {%rip} %t | count 139
 ; RUN: llvm-as < %s | llc -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=pic -code-model=small > %t
 ; RUN: not grep leal %t
 ; RUN: grep movl %t | count 98
@@ -146,7 +146,7 @@
 ; RUN: grep movl %t | count 91
 ; RUN: not grep addl %t
 ; RUN: not grep subl %t
-; RUN: grep leaq %t | count 93
+; RUN: grep leaq %t | count 70
 ; RUN: grep movq %t | count 56
 ; RUN: grep addq %t | count 20
 ; RUN: grep subq %t | count 14
@@ -160,7 +160,7 @@
 ; RUN: not grep @PLT %t
 ; RUN: not grep @PLTOFF %t
 ; RUN: grep {call      \\\*} %t | count 10
-; RUN: grep {%rip} %t | count 162
+; RUN: grep {%rip} %t | count 139
 ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small > %t
 ; RUN: not grep leal %t
 ; RUN: grep movl %t | count 95