Add code generator support for VSELECT
authorChris Lattner <sabre@nondot.org>
Sat, 8 Apr 2006 22:22:57 +0000 (22:22 +0000)
committerChris Lattner <sabre@nondot.org>
Sat, 8 Apr 2006 22:22:57 +0000 (22:22 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27542 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

index 225d2b39dfa7c60d9cffaa387e93898428e753b9..9cdbb910303fa7fb9c4639d2e86fdc8106a738a1 100644 (file)
@@ -4773,6 +4773,11 @@ SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
         assert(0 && "Cast from unsupported vector type not implemented yet!");
       }
     }
+  case ISD::VSELECT:
+    Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
+                         PackVectorOp(Op.getOperand(1), NewVT),
+                         PackVectorOp(Op.getOperand(2), NewVT));
+    break;
   }
 
   if (TLI.isTypeLegal(NewVT))
index a2b575ff31d83eec5e13c024c4c65eebd332c0ca..b58b67ed5346487be9e25988ded5cb81c22bf186 100644 (file)
@@ -2760,15 +2760,16 @@ const char *SDNode::getOperationName(const SelectionDAG *G) const {
   case ISD::SETCC:       return "setcc";
   case ISD::SELECT:      return "select";
   case ISD::SELECT_CC:   return "select_cc";
-  case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt";
-  case ISD::VINSERT_VECTOR_ELT: return "vinsert_vector_elt";
-  case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt";
+  case ISD::VSELECT:     return "vselect";
+  case ISD::INSERT_VECTOR_ELT:   return "insert_vector_elt";
+  case ISD::VINSERT_VECTOR_ELT:  return "vinsert_vector_elt";
+  case ISD::EXTRACT_VECTOR_ELT:  return "extract_vector_elt";
   case ISD::VEXTRACT_VECTOR_ELT: return "vextract_vector_elt";
-  case ISD::SCALAR_TO_VECTOR:   return "scalar_to_vector";
-  case ISD::VBUILD_VECTOR: return "vbuild_vector";
-  case ISD::VECTOR_SHUFFLE: return "vector_shuffle";
-  case ISD::VVECTOR_SHUFFLE: return "vvector_shuffle";
-  case ISD::VBIT_CONVERT: return "vbit_convert";
+  case ISD::SCALAR_TO_VECTOR:    return "scalar_to_vector";
+  case ISD::VBUILD_VECTOR:       return "vbuild_vector";
+  case ISD::VECTOR_SHUFFLE:      return "vector_shuffle";
+  case ISD::VVECTOR_SHUFFLE:     return "vvector_shuffle";
+  case ISD::VBIT_CONVERT:        return "vbit_convert";
   case ISD::ADDC:        return "addc";
   case ISD::ADDE:        return "adde";
   case ISD::SUBC:        return "subc";
index dba4c736b70f4a03f22ef1b8c35633b2cdb68f10..c02654175e1332b4227b64aa1f63a202fbd9ca66 100644 (file)
@@ -992,8 +992,14 @@ void SelectionDAGLowering::visitSelect(User &I) {
   SDOperand Cond     = getValue(I.getOperand(0));
   SDOperand TrueVal  = getValue(I.getOperand(1));
   SDOperand FalseVal = getValue(I.getOperand(2));
-  setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
-                           TrueVal, FalseVal));
+  if (!isa<PackedType>(I.getType())) {
+    setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
+                             TrueVal, FalseVal));
+  } else {
+    setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal,
+                             *(TrueVal.Val->op_end()-2),
+                             *(TrueVal.Val->op_end()-1)));
+  }
 }
 
 void SelectionDAGLowering::visitCast(User &I) {