bool isDummyPhiInstr(MachineOpCode opCode) const {
return get(opCode).Flags & M_DUMMY_PHI_FLAG;
}
- // Check if an instruction can be issued before its operands are ready,
- // or if a subsequent instruction that uses its result can be issued
- // before the results are ready.
- // Default to true since most instructions on many architectures allow this.
- //
- virtual bool hasOperandInterlock(MachineOpCode opCode) const {
- return true;
- }
+
virtual bool hasResultInterlock(MachineOpCode opCode) const {
return true;
}
-
+
//
// Latencies for individual instructions and instruction pairs
//
&& (*EI)->getDepType() == SchedGraphEdge::CtrlDep)
return false;
- // for now, don't put an instruction that does not have operand
- // interlocks in the delay slot of a branch
- if (! S.getInstrInfo().hasOperandInterlock(node->getOpcode()))
- return false;
-
// Finally, if the instruction precedes the branch, we make sure the
// instruction can be reordered relative to the branch. We simply check
// if the instr. has only 1 outgoing edge, viz., a CD edge to the branch.
const SchedGraphNode* dnode = delayNodeVec[i];
if ( ! S.isScheduled(dnode)
&& S.schedInfo.instrCanUseSlot(dnode->getOpcode(), nextSlot)
- && instrIsFeasible(S, dnode->getOpcode()))
- {
- assert(S.getInstrInfo().hasOperandInterlock(dnode->getOpcode())
- && "Instructions without interlocks not yet supported "
- "when filling branch delay slots");
+ && instrIsFeasible(S, dnode->getOpcode())) {
S.scheduleInstr(dnode, nextSlot, nextTime);
break;
}
&& (*EI)->getDepType() == SchedGraphEdge::CtrlDep)
return false;
- // for now, don't put an instruction that does not have operand
- // interlocks in the delay slot of a branch
- if (! S.getInstrInfo().hasOperandInterlock(node->getOpcode()))
- return false;
-
// Finally, if the instruction precedes the branch, we make sure the
// instruction can be reordered relative to the branch. We simply check
// if the instr. has only 1 outgoing edge, viz., a CD edge to the branch.
const SchedGraphNode* dnode = delayNodeVec[i];
if ( ! S.isScheduled(dnode)
&& S.schedInfo.instrCanUseSlot(dnode->getOpcode(), nextSlot)
- && instrIsFeasible(S, dnode->getOpcode()))
- {
- assert(S.getInstrInfo().hasOperandInterlock(dnode->getOpcode())
- && "Instructions without interlocks not yet supported "
- "when filling branch delay slots");
+ && instrIsFeasible(S, dnode->getOpcode())) {
S.scheduleInstr(dnode, nextSlot, nextTime);
break;
}