UPSTREAM: ARM: dts: rockchip: support the spi for rk3036

This patch adds the needed spi node for rk3036 dts.

We have to use the 4 bus emmc to work if someone want to support
the spi devices, since the pins are re-used by emmc data[5-8] and spi.
In some caseswe need to support the spi devices, that will waste the
emmc performance.

Moment, the kylin/evb hasn't the spi devices to work, so maybe we need wait
the new required to enable in kylin/evb board.

Anyway, the spi should be needed land in rk3036 dts.

Change-Id: I5bace7efcc2aa214be22a9b3009440c053b4c5e7
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org next/linux-next.git master
 commit f629fcfab2cd8a2f1a571fbc83e76a81ee3470db)

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 78974492cb1190b49b3f42b8678dee10e3df8d27..28fa2f848df8933d15bf946d2069353d4e3e4e2b 100644 (file)
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -60,6 +60,7 @@
                serial0 = &uart0;
                serial1 = &uart1;
                serial2 = &uart2;
+               spi = &spi;
        };
 
        memory {
@@ -407,6 +408,21 @@
                status = "disabled";
        };
 
+       spi: spi@20074000 {
+               compatible = "rockchip,rockchip-spi";
+               reg = <0x20074000 0x1000>;
+               interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+               clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
+               clock-names = "apb-pclk","spi_pclk";
+               dmas = <&pdma 8>, <&pdma 9>;
+               dma-names = "tx", "rx";
+               pinctrl-names = "default";
+               pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
        pinctrl: pinctrl {
                compatible = "rockchip,rk3036-pinctrl";
                rockchip,grf = <&grf>;
@@ -618,5 +634,29 @@
                        };
                        /* no rts / cts for uart2 */
                };
+
+               spi {
+                       spi_txd:spi-txd {
+                               rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
+                       };
+
+                       spi_rxd:spi-rxd {
+                               rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
+                       };
+
+                       spi_clk:spi-clk {
+                               rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
+                       };
+
+                       spi_cs0:spi-cs0 {
+                               rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
+
+                       };
+
+                       spi_cs1:spi-cs1 {
+                               rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;
+
+                       };
+               };
        };
 };