struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
priv->irq_enabled = 1;
-#ifdef RTL8192CE
- write_nic_dword(dev, REG_HIMR, priv->irq_mask[0]&0xFFFFFFFF);
-#else
write_nic_dword(dev,INTA_MASK, priv->irq_mask[0]);
-#endif
}
{
struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
-#ifdef RTL8192CE
- write_nic_dword(dev, REG_HIMR, IMR8190_DISABLED);
-#else
write_nic_dword(dev,INTA_MASK,0);
-#endif
priv->irq_enabled = 0;
}
void rtl8192_ClearInterrupt(struct net_device *dev)
{
u32 tmp = 0;
-#ifdef RTL8192CE
- tmp = read_nic_dword(dev, REG_HISR);
- write_nic_dword(dev, REG_HISR, tmp);
-#else
tmp = read_nic_dword(dev, ISR);
write_nic_dword(dev, ISR, tmp);
-#endif
-
}
struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
u32 reg;
-#ifdef RTL8192CE
- reg = read_nic_dword(priv->rtllib->dev,REG_HIMR);
-
- reg &= ~(IMR_BcnInt | IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
- write_nic_dword(priv->rtllib->dev, REG_HIMR, reg);
-#else
reg = read_nic_dword(priv->rtllib->dev,INTA_MASK);
reg &= ~(IMR_BcnInt | IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
write_nic_dword(priv->rtllib->dev, INTA_MASK, reg);
-#endif
}
void rtl8192_interrupt_recognized(struct net_device *dev, u32 *p_inta, u32 *p_intb)
{
PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
-#ifdef RTL8192CE
- pHTInfo->bRDGEnable = 0;
-#endif
-
pHTInfo->bAcceptAddbaReq = 1;
pHTInfo->bRegShortGI20MHz= 1;
retValue = false;
}
}
-#endif
-#if defined(RTL8192SU) || defined RTL8192CE
- PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
- if (ieee->rtllib_ap_sec_type &&
- (ieee->rtllib_ap_sec_type(ieee)&(SEC_ALG_WEP|SEC_ALG_TKIP)))
- {
- if ( (pHTInfo->IOTPeer != HT_IOT_PEER_ATHEROS) &&
- (pHTInfo->IOTPeer != HT_IOT_PEER_UNKNOWN) &&
- (pHTInfo->IOTPeer != HT_IOT_PEER_MARVELL) &&
- (pHTInfo->IOTPeer != HT_IOT_PEER_REALTEK_92SE) &&
- (pHTInfo->IOTPeer != HT_IOT_PEER_RALINK) )
- retValue = true;
- }
#endif
return retValue;
}
#if defined RTL8192SU
if (ieee->mode == IEEE_G)
retValue = true;
-#elif defined RTL8192CE
- if (ieee->mode == IEEE_G ||
- (ieee->rtllib_ap_sec_type(ieee)&(SEC_ALG_WEP|SEC_ALG_TKIP)))
- retValue = true;
#endif
return retValue;
pHTInfo->IOTPeer==HT_IOT_PEER_RALINK)
return 1;
- }
-#elif defined RTL8192CE
- PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
- {
- if (pHTInfo->IOTPeer==HT_IOT_PEER_ATHEROS ||
- pHTInfo->IOTPeer==HT_IOT_PEER_RALINK)
- return 1;
-
}
#endif
return retValue;
*posRT2RTAgg++ = 0x02;
*posRT2RTAgg++ = 0x01;
-#ifdef RTL8192CE
- *posRT2RTAgg = 0x70;
-#else
*posRT2RTAgg = 0x30;
-#endif
if (ieee->bSupportRemoteWakeUp) {
*posRT2RTAgg |= RT_HT_CAP_USE_WOW;
#include "r8192E_cmdpkt.h"
#include "rtl_wx.h"
-#ifndef RTL8192CE
#include "rtl_dm.h"
-#endif
#ifdef CONFIG_PM_RTL
#include "rtl_pm.h"
writeb(y,(u8*)dev->mem_start +x);
udelay(20);
-
-#if defined RTL8192CE
- read_nic_byte(dev, x);
-#endif
}
void write_nic_dword(struct net_device *dev, int x,u32 y)
writel(y,(u8*)dev->mem_start +x);
udelay(20);
-
-#if defined RTL8192CE
- read_nic_dword(dev, x);
-#endif
}
void write_nic_word(struct net_device *dev, int x,u16 y)
writew(y,(u8*)dev->mem_start +x);
udelay(20);
-
-#if defined RTL8192CE
- read_nic_word(dev, x);
-#endif
}
/****************************************************************************
unsigned long flag;
RT_TRACE((COMP_PS | COMP_RF), "===>MgntActSet_RF_State(): StateToSet(%d)\n",StateToSet);
-#ifndef RTL8192CE
ProtectOrNot = false;
-#endif
if (!ProtectOrNot)
memcpy(ieee->Regdot11HTOperationalRateSet, ieee->RegHTSuppRateSet, 16);
memcpy(ieee->Regdot11TxHTOperationalRateSet, ieee->RegHTSuppRateSet, 16);
-#ifdef RTL8192CE
- if (priv->rf_type == RF_1T1R) {
- ieee->Regdot11HTOperationalRateSet[1] = 0;
- }
-#endif
-
} else {
memset(ieee->Regdot11HTOperationalRateSet, 0, 16);
}
pPSC->RegMaxLPSAwakeIntvl = 5;
-#ifdef RTL8192CE
- priv->bWEPinNmodeFromReg = 0;
- priv->bTKIPinNmodeFromReg = 0;
-
- priv->RegAMDPciASPM = 0;
-
- priv->RegPciASPM = 3;
-
- priv->RegDevicePciASPMSetting = 0x03;
-
- priv->RegHostPciASPMSetting = 0x02;
-
- priv->RegHwSwRfOffD3 = 0;
-
- priv->RegSupportPciASPM = 1;
-
-#elif defined RTL8192E
priv->RegPciASPM = 2;
priv->RegDevicePciASPMSetting = 0x03;
priv->RegHwSwRfOffD3 = 2;
priv->RegSupportPciASPM = 2;
-
-#endif
}
spin_unlock_irqrestore(&priv->irq_th_lock,flags);
dev->trans_start = jiffies;
-#ifdef RTL8192CE
- if (tcb_desc->queue_index == BEACON_QUEUE){
- write_nic_word(dev, REG_PCIE_CTRL_REG, BIT4);
- }else{
- write_nic_word(dev, REG_PCIE_CTRL_REG, BIT0<<(tcb_desc->queue_index));
- }
-#else
- write_nic_word(dev,TPPoll,0x01<<tcb_desc->queue_index);
-#endif
+ write_nic_word(dev,TPPoll,0x01<<tcb_desc->queue_index);
return 0;
}
skb_len = skb->len;
-#ifdef RTL8192CE
- if (!stats.bCRC)
-#else
if (1)
-#endif
{
if (!rtllib_rx(priv->rtllib, skb, &stats)){
dev_kfree_skb_any(skb);
if (MAX_RX_QUEUE > 1)
rtl8192_rx_cmd(priv->rtllib->dev);
-#ifndef RTL8192CE
write_nic_dword(priv->rtllib->dev, INTA_MASK,read_nic_dword(priv->rtllib->dev, INTA_MASK) | IMR_RDU);
-#endif
}
/****************************************************************************
spin_lock_irqsave(&priv->irq_th_lock,flags);
}
-#ifndef RTL8192CE
if (inta & IMR_COMDOK) {
priv->stats.txcmdpktokint++;
rtl8192_tx_isr(dev,TXCMD_QUEUE);
}
-#endif
if (inta & IMR_HIGHDOK) {
rtl8192_tx_isr(dev,HIGH_QUEUE);
if (inta & IMR_RDU) {
RT_TRACE(COMP_INTR, "rx descriptor unavailable!\n");
priv->stats.rxrdu++;
-#ifndef RTL8192CE
write_nic_dword(dev,INTA_MASK,read_nic_dword(dev, INTA_MASK) & ~IMR_RDU);
-#endif
tasklet_schedule(&priv->irq_rx_tasklet);
}
else
priv->rtllib->bSupportRemoteWakeUp = 0;
-#ifdef RTL8192CE
- pmem_start = pci_resource_start(pdev, 2);
- pmem_len = pci_resource_len(pdev, 2);
- pmem_flags = pci_resource_flags (pdev, 2);
-#else
pmem_start = pci_resource_start(pdev, 1);
pmem_len = pci_resource_len(pdev, 1);
pmem_flags = pci_resource_flags (pdev, 1);
-#endif
if (!(pmem_flags & IORESOURCE_MEM)) {
RT_TRACE(COMP_ERR,"region #1 not a MMIO resource, aborting");