rk3036:clk:modify init clocks

diff --git a/arch/arm/boot/dts/rk3036-clocks.dtsi b/arch/arm/boot/dts/rk3036-clocks.dtsi
index 8e98257b6c1371fc2f04d31045fb8525e6caff75..aa9c1675b95762e604b1c4861bb35eefb66b4357 100755 (executable)
--- a/arch/arm/boot/dts/rk3036-clocks.dtsi
+++ b/arch/arm/boot/dts/rk3036-clocks.dtsi
@@ -94,6 +94,16 @@
                                clock-mult = <20>;
                                #clock-cells = <0>;
                        };
+
+                       hclk_vcodec: hclk_vcodec {
+                               compatible = "rockchip,rk-fixed-factor-clock";
+                               clocks = <&aclk_vcodec_pre>;
+                               clock-output-names = "hclk_vcodec";
+                               clock-div = <4>;
+                               clock-mult = <1>;
+                               #clock-cells = <0>;
+                       };
+
                };
 
                clock_regs {
@@ -830,6 +840,7 @@
                                                clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
                                                clock-output-names = "clk_mac_pll";
                                                #clock-cells = <0>;
+                                               #clock-init-cells = <1>;
                                        };
 
                                        /* reg[2]: reserved */

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 8e49b79881d0774616a14d372a62fd3b255f2c4e..4cf02a369ae93d21b14e6d70d67de3910f3ffab8 100755 (executable)
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -187,15 +187,17 @@
                rockchip,clocks-init-parent =
                        <&clk_core_pre &clk_apll>, <&aclk_cpu_pre &clk_gpll>,
                        <&aclk_peri_pre &clk_gpll>, <&clk_uart_pll &clk_gpll>,  
-                       <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>;
+                       <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
+                       <&aclk_vcodec_pre &clk_gpll>, <&clk_hevc_core &clk_gpll>,
+                       <&clk_mac_pll &clk_apll>;
                rockchip,clocks-init-rate =
-                       <&clk_core_pre 1464000000>, <&clk_gpll 297000000>,
-                       <&aclk_cpu_pre 300000000>, <&hclk_cpu_pre 150000000>,   
-                       <&pclk_cpu_pre 75000000>,        <&aclk_peri_pre 300000000>,
-                       <&hclk_peri_pre 150000000>, <&pclk_peri_pre 75000000>,
-                       <&clk_gpu_pre 200000000>,        <&aclk_vio_pre 300000000>,
-                       <&hclk_vio_pre 150000000>,       <&aclk_vcodec_pre 400000000>,
-                       <&clk_hevc_core 300000000>,  <&clk_mac_ref_div 125000000>;
+                       <&clk_core_pre 816000000>, <&clk_gpll 594000000>,
+                       <&aclk_cpu_pre 150000000>, <&hclk_cpu_pre 75000000>,    
+                       <&pclk_cpu_pre 75000000>,        <&aclk_peri_pre 150000000>,
+                       <&hclk_peri_pre 75000000>, <&pclk_peri_pre 75000000>,
+                       <&clk_gpu_pre 300000000>,        <&aclk_vio_pre 300000000>,
+                       <&hclk_vio_pre 150000000>, <&aclk_vcodec_pre 300000000>,
+                       <&clk_hevc_core 300000000>, <&clk_mac_ref_div 50000000>;
        /*      rockchip,clocks-uboot-has-init =
                        <&aclk_vio1>;*/
        };

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index dee39a0edebe520d0383e81a3083a2dec45e42c2..e2521217f63d4f0807fd975d94f75005d7c633ae 100755 (executable)
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -216,8 +216,9 @@ static const struct apll_clk_set rk3036_apll_table[] = {
 };
 
 static const struct pll_clk_set rk3036plus_pll_com_table[] = {
-       _RK3036_PLL_SET_CLKS(297000, 2, 99, 4, 1, 1, 0),
-       _RK3036_PLL_SET_CLKS(768000, 1, 32, 1, 1, 1, 0),
+//     _RK3036_PLL_SET_CLKS(297000, 2, 99, 4, 1, 1, 0),
+       _RK3036_PLL_SET_CLKS(594000, 2, 99, 2, 1, 1, 0),
+       _RK3036_PLL_SET_CLKS(1188000, 2, 99, 1, 1, 1, 0),
 
 };