UPSTREAM: phy: xgene: rename "enum phy_mode" to "enum xgene_phy_mode"

No functional change. Rename "enum phy_mode" to
"enum xgene_phy_mode" in xgene phy driver in
preparation for adding set_mode callback in
phy core.

Change-Id: I7e569e1fb82a308e79d30a80323e0c3c338dd68c
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Loc Ho <lho@apm.com>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 65048f4dd9fae7335b48ab23a879119c0e7fa105)

diff --git a/drivers/phy/phy-xgene.c b/drivers/phy/phy-xgene.c
index 385362e5b2f6fbee91a14ff9ba2afb9b14edcb7c..ae266e0c8368b1bb8595f50ff748daf6fc70f140 100644 (file)
--- a/drivers/phy/phy-xgene.c
+++ b/drivers/phy/phy-xgene.c
@@ -518,7 +518,7 @@ enum clk_type_t {
        CLK_INT_SING = 2,       /* Internal single ended */
 };
 
-enum phy_mode {
+enum xgene_phy_mode {
        MODE_SATA       = 0,    /* List them for simple reference */
        MODE_SGMII      = 1,
        MODE_PCIE       = 2,
@@ -542,7 +542,7 @@ struct xgene_sata_override_param {
 struct xgene_phy_ctx {
        struct device *dev;
        struct phy *phy;
-       enum phy_mode mode;             /* Mode of operation */
+       enum xgene_phy_mode mode;               /* Mode of operation */
        enum clk_type_t clk_type;       /* Input clock selection */
        void __iomem *sds_base;         /* PHY CSR base addr */
        struct clk *clk;                /* Optional clock */