clk: rockchip: add clock ids for isp of RK3366 SoCs

Change-Id: Ia1c1ef34eebcaa8f29d537b291c45654252444b8
Signed-off-by: Feng Xiao <xf@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3366.c b/drivers/clk/rockchip/clk-rk3366.c
index 8d631e9120972ae4b6a4b6722f20d94c59bc9852..fb45fcac947d9530f7bfeedc18fb9023dc33df0c 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3366.c
+++ b/drivers/clk/rockchip/clk-rk3366.c
@@ -407,6 +407,9 @@ static struct rockchip_clk_branch rk3366_clk_branches[] __initdata = {
                        RK3368_CLKSEL_CON(22), 6, 2, MFLAGS, 0, 6, DFLAGS,
                        RK3368_CLKGATE_CON(4), 9, GFLAGS),
 
+       GATE(PCLK_ISP, "pclk_isp", "ext_isp", 0,
+                       RK3368_CLKGATE_CON(17), 2, GFLAGS),
+
        GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
                        RK3368_CLKGATE_CON(4), 13, GFLAGS),
        GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "clk_32k", 0,

diff --git a/include/dt-bindings/clock/rk3366-cru.h b/include/dt-bindings/clock/rk3366-cru.h
index 8c7bf158fdcffcaad6e4e0e0552de7d9fd86a2a1..f3d99b854e39d111f35b7d46905a566a881210eb 100644 (file)
--- a/include/dt-bindings/clock/rk3366-cru.h
+++ b/include/dt-bindings/clock/rk3366-cru.h
@@ -163,6 +163,7 @@
 #define PCLK_PERI0             362
 #define PCLK_PERI1             363
 #define PCLK_MIPI_DSI0         364
+#define PCLK_ISP               365
 
 /* hclk gates */
 #define HCLK_I2S_8CH           448