rk3168_86v: 2in1 IO
authorhjc <hjc@rock-chips.com>
Mon, 18 Mar 2013 03:00:12 +0000 (11:00 +0800)
committerhjc <hjc@rock-chips.com>
Mon, 18 Mar 2013 03:00:12 +0000 (11:00 +0800)
arch/arm/mach-rk30/board-rk3168-86v-sdmmc-config.c

index b873bba667bbdd2600c49a9a0dd7b454a8dca86a..6badb11fe0d79009da833612f52f4c537a8153c2 100755 (executable)
@@ -97,11 +97,11 @@ int rk31sdk_get_sdmmc0_pin_io_voltage(void)
        #endif
 
 #elif defined(CONFIG_MT6620)
-    #define COMBO_MODULE_MT6620_CDT    1  // to control antsel2,antsel3 and gps_lan foot when using AcSip or Cdtech chip. 
+    #define COMBO_MODULE_MT6620_CDT    0  // to control antsel2,antsel3 and gps_lan foot when using AcSip or Cdtech chip. 
                                              //- 1--use Cdtech chip; 0--unuse CDT chip
 
     //power, PMU_EN
-    #define RK30SDK_WIFI_GPIO_POWER_N                   RK30_PIN3_PC7            
+    #define RK30SDK_WIFI_GPIO_POWER_N                   RK30_PIN3_PD0             
     #define RK30SDK_WIFI_GPIO_POWER_ENABLE_VALUE        GPIO_HIGH        
     //reset, DAIRST,SYSRST_B
     #define RK30SDK_WIFI_GPIO_RESET_N                   RK30_PIN3_PD1
@@ -113,10 +113,10 @@ int rk31sdk_get_sdmmc0_pin_io_voltage(void)
     #define RK30SDK_WIFI_GPIO_WIFI_INT_B                RK30_PIN3_PD2
     #define RK30SDK_WIFI_GPIO_WIFI_INT_B_ENABLE_VALUE   GPIO_HIGH 
     //BGF_INT_B
-    #define RK30SDK_WIFI_GPIO_BGF_INT_B                 RK30_PIN6_PA7
+    #define RK30SDK_WIFI_GPIO_BGF_INT_B                 RK30_PIN0_PA5
     #define RK30SDK_WIFI_GPIO_BGF_INT_B_ENABLE_VALUE    GPIO_HIGH 
     //GPS_SYNC
-    #define RK30SDK_WIFI_GPIO_GPS_SYNC                  RK30_PIN3_PD0
+    #define RK30SDK_WIFI_GPIO_GPS_SYNC                  RK30_PIN3_PC6
     #define RK30SDK_WIFI_GPIO_GPS_SYNC_ENABLE_VALUE     GPIO_HIGH 
 
     #if COMBO_MODULE_MT6620_CDT