PM / devfreq: get lcdc type from vop drivers for rk3368

Change-Id: I9205286f7b4c0d7ecba3bb08a45af3f49225abe5
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c
index c6ba4eae18be34048e1f9b4ffcf558336388c33e..860e58a043031a55615012f459bf7c32b35c6ac4 100644 (file)
--- a/drivers/clk/rockchip/clk-ddr.c
+++ b/drivers/clk/rockchip/clk-ddr.c
@@ -162,7 +162,9 @@ static int rockchip_ddrclk_scpi_set_rate(struct clk_hw *hw, unsigned long drate,
                                         unsigned long prate)
 {
        u32 ret;
-       u32 lcdc_type = 7;
+       u32 lcdc_type;
+
+       lcdc_type = rk_drm_get_lcdc_type();
 
        ret = scpi_ddr_set_clk_rate(drate / MHZ, lcdc_type);
        if (ret) {

diff --git a/drivers/devfreq/rockchip_dmc.c b/drivers/devfreq/rockchip_dmc.c
index 53ea367059001e30115f757d5d765391f27520a4..921c9dee8b7acb3bbc18cc009334d60d988ab713 100644 (file)
--- a/drivers/devfreq/rockchip_dmc.c
+++ b/drivers/devfreq/rockchip_dmc.c
@@ -747,12 +747,18 @@ static int rk3368_dmc_init(struct platform_device *pdev,
        struct arm_smccc_res res;
        struct rk3368_dram_timing *dram_timing;
        struct clk *pclk_phy, *pclk_upctl;
+       struct drm_device *drm = drm_device_get_by_name("rockchip");
        int ret;
        u32 dram_spd_bin;
        u32 addr_mcu_el3;
        u32 dclk_mode;
        u32 lcdc_type;
 
+       if (!drm) {
+               dev_err(dev, "Get drm_device fail\n");
+               return -EPROBE_DEFER;
+       }
+
        pclk_phy = devm_clk_get(dev, "pclk_phy");
        if (IS_ERR(pclk_phy)) {
                dev_err(dev, "Cannot get the clk pclk_phy\n");
@@ -800,7 +806,7 @@ static int rk3368_dmc_init(struct platform_device *pdev,
        if (of_property_read_u32(np, "vop-dclk-mode", &dclk_mode) == 0)
                scpi_ddr_dclk_mode(dclk_mode);
 
-       lcdc_type = 7;
+       lcdc_type = rk_drm_get_lcdc_type();
 
        if (scpi_ddr_init(dram_spd_bin, 0, lcdc_type,
                          addr_mcu_el3))