ARM: EXYNOS: SWRESET is needed to boot secondary CPU on exynos3250

Without software reset the secondary CPU does not power up and
exynos_boot_secondary() ends with pen_release equal to 1. This can be
observed in dmesg:
	CPU1: failed to come online
	Brought up 1 CPUs
	SMP: Total of 1 processors activated.
	CPU: All CPU(s) started in SVC mode.

When booting the secondary CPU on Exynos3250 execute also software
reset for core 1.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 41ae28d69e6f7e2012fe86d006e6d8151f26927d..8543064dc445440b194cd692861584a1d713297f 100644 (file)
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -120,6 +120,26 @@ static inline void __iomem *cpu_boot_reg(int cpu)
        return boot_reg;
 }
 
+/*
+ * Set wake up by local power mode and execute software reset for given core.
+ *
+ * Currently this is needed only when booting secondary CPU on Exynos3250.
+ */
+static void exynos_core_restart(u32 core_id)
+{
+       u32 val;
+
+       if (!of_machine_is_compatible("samsung,exynos3250"))
+               return;
+
+       val = pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(core_id));
+       val |= S5P_CORE_WAKEUP_FROM_LOCAL_CFG;
+       pmu_raw_writel(val, EXYNOS_ARM_CORE_STATUS(core_id));
+
+       pr_info("CPU%u: Software reset\n", core_id);
+       pmu_raw_writel(EXYNOS_CORE_PO_RESET(core_id), EXYNOS_SWRESET);
+}
+
 /*
  * Write pen_release in a way that is guaranteed to be visible to all
  * observers, irrespective of whether they're taking part in coherency
@@ -196,6 +216,9 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
                        return -ETIMEDOUT;
                }
        }
+
+       exynos_core_restart(core_id);
+
        /*
         * Send the secondary CPU a soft interrupt, thereby causing
         * the boot monitor to read the system wide flags register,

diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 30c03017aa6a65440b41cc99ae496faf1aed6bbf..4ea5e320c6d1387c8b210f72af2523fa45213b3c 100644 (file)
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -21,6 +21,7 @@
 #define S5P_USE_STANDBY_WFI0                   (1 << 16)
 #define S5P_USE_STANDBY_WFE0                   (1 << 24)
 
+#define EXYNOS_CORE_PO_RESET(n)                        ((1 << 4) << n)
 #define EXYNOS_WAKEUP_FROM_LOWPWR              (1 << 28)
 #define EXYNOS_SWRESET                         0x0400
 #define EXYNOS5440_SWRESET                     0x00C4
@@ -125,6 +126,7 @@
 #define S5P_PAD_RET_EBIB_OPTION                        0x31A8
 
 #define S5P_CORE_LOCAL_PWR_EN                  0x3
+#define S5P_CORE_WAKEUP_FROM_LOCAL_CFG         (0x3 << 8)
 
 /* Only for EXYNOS4210 */
 #define S5P_CMU_CLKSTOP_LCD1_LOWPWR    0x1154