modify for rga.h independ

diff --git a/drivers/video/rockchip/rga/RGA_API.c b/drivers/video/rockchip/rga/RGA_API.c
index f7e7d0b0dd6e3334354674a580b3999a82f76827..7c3b4be9d7b39059776531ecd7052c6601f0afe4 100755 (executable)
--- a/drivers/video/rockchip/rga/RGA_API.c
+++ b/drivers/video/rockchip/rga/RGA_API.c
@@ -83,10 +83,10 @@ matrix_cal(const struct rga_req *msg, TILE_INFO *tile)
 u32\r
 RGA_dst_act_addr_temp(const struct rga_req *msg)\r
 {\r
-    u32 pw;\r
-    u32 x_off, y_off;\r
-    u32 stride;\r
-    u32 p;\r
+    uint32_t pw;\r
+    uint32_t x_off, y_off;\r
+    uint32_t stride;\r
+    uint32_t p;\r
     \r
     pw = RGA_pixel_width_init(msg->dst.format);\r
     stride = (msg->dst.vir_w * pw + 3) & (~3);    \r
@@ -100,11 +100,10 @@ RGA_dst_act_addr_temp(const struct rga_req *msg)
 }\r
 \r
 void\r
-RGA_set_cmd_info(u8 cmd_mode, u32 cmd_addr)\r
+RGA_set_cmd_info(uint8_t cmd_mode, uint32_t cmd_addr)\r
 {\r
-    u32 reg = 0;\r
+    uint32_t reg = 0;\r
     \r
-    //reg = rRGA_SYS_CTRL;\r
     reg |= ((cmd_mode & 1) << 1);\r
     rRGA_SYS_CTRL = reg; \r
     rRGA_CMD_ADDR = cmd_addr;\r
@@ -113,8 +112,8 @@ RGA_set_cmd_info(u8 cmd_mode, u32 cmd_addr)
 void\r
 RGA_start(void) \r
 {\r
-    u32 reg = 0;\r
-    u8  cmd_mode;\r
+    uint32_t reg = 0;\r
+    uint8_t  cmd_mode;\r
     \r
     reg = rRGA_SYS_CTRL;\r
     cmd_mode = (reg >> 2) & 1;\r
@@ -138,7 +137,7 @@ RGA_start(void)
 void\r
 RGA_soft_reset(void)\r
 {\r
-    u32 reg = 0;\r
+    uint32_t reg = 0;\r
 \r
     reg = rRGA_SYS_CTRL;\r
     reg |= 1;\r
@@ -185,7 +184,7 @@ void rga_check_int_all_cmd_finish(RGA_INFO *p_rga_info)
 }\r
 #endif\r
 \r
-void rga_start_cmd_AXI(u8 *base, u32 num)\r
+void rga_start_cmd_AXI(uint8_t *base, uint32_t num)\r
 {\r
     rRGA_SYS_CTRL = 0x4;\r
     rRGA_INT = s_RGA_INT_ALL_CMD_DONE_INT_EN(ENABLE)| s_RGA_INT_MMU_INT_EN(ENABLE)| s_RGA_INT_ERROR_INT_EN(ENABLE);\r
@@ -196,8 +195,8 @@ void rga_start_cmd_AXI(u8 *base, u32 num)
 \r
 void rga_check_cmd_finish(void)\r
 {\r
-       u8 int_flag;\r
-    u8 error_flag;\r
+       uint8_t int_flag;\r
+    uint8_t error_flag;\r
        \r
        int_flag = 0;\r
     error_flag = 0;\r
@@ -222,9 +221,9 @@ void rga_check_cmd_finish(void)
 \r
 \r
 \r
-void rga_start_cmd_AHB(u8 *base)\r
+void rga_start_cmd_AHB(uint8_t *base)\r
 {\r
-    u32 *base_p32;\r
+    uint32_t *base_p32;\r
     \r
     base_p32 = (u32 *)base;\r
     *base_p32 = (*base_p32 | (1<<29));\r
@@ -237,7 +236,7 @@ void rga_start_cmd_AHB(u8 *base)
 \r
 void rga_check_cmd_AHB_finish(void)\r
 {\r
-       u8 int_flag;\r
+       uint8_t int_flag;\r
        \r
        int_flag = 0;\r
        while(!int_flag)\r
@@ -253,11 +252,11 @@ uint32_t RGA_gen_two_pro(struct rga_req *msg, struct rga_req *msg1)
 {\r
     \r
     struct rga_req *mp;\r
-    u32 w_ratio, h_ratio;\r
-    u32 stride;\r
+    uint32_t w_ratio, h_ratio;\r
+    uint32_t stride;\r
 \r
-    u32 daw, dah;\r
-    u32 pl;\r
+    uint32_t daw, dah;\r
+    uint32_t pl;\r
 \r
     daw = dah = 0;\r
             \r

diff --git a/drivers/video/rockchip/rga/rga.h b/drivers/video/rockchip/rga/rga.h
index 90a17bf20d36c915fcf98b939f599590a299b6eb..6a82646c11d48af53c0caa2644bbae558d068df6 100755 (executable)
--- a/drivers/video/rockchip/rga/rga.h
+++ b/drivers/video/rockchip/rga/rga.h
@@ -1,11 +1,6 @@
 #ifndef _RGA_DRIVER_H_\r
 #define _RGA_DRIVER_H_\r
 \r
-#include "rga_type.h"\r
-#include <linux/types.h>\r
-#include <linux/miscdevice.h>\r
-#include <linux/platform_device.h>\r
-\r
 \r
 #define RGA_BLIT_SYNC  0x5017\r
 #define RGA_BLIT_ASYNC  0x5018\r
@@ -118,31 +113,31 @@ enum
     \r
 typedef struct rga_img_info_t\r
 {\r
-    uint32 yrgb_addr;      /* yrgb    mem addr         */\r
-    uint32 uv_addr;        /* cb/cr   mem addr         */\r
-    uint32 v_addr;         /* cr      mem addr         */\r
-    uint32 format;         //definition by RK_FORMAT\r
+    unsigned int yrgb_addr;      /* yrgb    mem addr         */\r
+    unsigned int uv_addr;        /* cb/cr   mem addr         */\r
+    unsigned int v_addr;         /* cr      mem addr         */\r
+    unsigned int format;         //definition by RK_FORMAT\r
     \r
-    UWORD16 act_w;\r
-    UWORD16 act_h;\r
-    UWORD16 x_offset;\r
-    UWORD16 y_offset;\r
+    unsigned short act_w;\r
+    unsigned short act_h;\r
+    unsigned short x_offset;\r
+    unsigned short y_offset;\r
     \r
-    UWORD16 vir_w;\r
-    UWORD16 vir_h;\r
+    unsigned short vir_w;\r
+    unsigned short vir_h;\r
     \r
-    UWORD16 endian_mode; //for BPP\r
-    UWORD16 alpha_swap;\r
+    unsigned short endian_mode; //for BPP\r
+    unsigned short alpha_swap;\r
 }\r
 rga_img_info_t;\r
 \r
 \r
 typedef struct mdp_img_act\r
 {\r
-    UWORD16 w;         // width\r
-    UWORD16 h;         // height\r
-    WORD16 x_off;     // x offset for the vir\r
-    WORD16 y_off;     // y offset for the vir\r
+    unsigned short w;         // width\r
+    unsigned short h;         // height\r
+    short x_off;     // x offset for the vir\r
+    short y_off;     // y offset for the vir\r
 }\r
 mdp_img_act;\r
 \r
@@ -150,24 +145,24 @@ mdp_img_act;
 \r
 typedef struct RANGE\r
 {\r
-    UWORD16 min;\r
-    UWORD16 max;\r
+    unsigned short min;\r
+    unsigned short max;\r
 }\r
 RANGE;\r
 \r
 typedef struct POINT\r
 {\r
-    UWORD16 x;\r
-    UWORD16 y;\r
+    unsigned short x;\r
+    unsigned short y;\r
 }\r
 POINT;\r
 \r
 typedef struct RECT\r
 {\r
-    WORD16 xmin;\r
-    WORD16 xmax; // width - 1\r
-    WORD16 ymin; \r
-    WORD16 ymax; // height - 1 \r
+    unsigned short xmin;\r
+    unsigned short xmax; // width - 1\r
+    unsigned short ymin; \r
+    unsigned short ymax; // height - 1 \r
 } RECT;\r
 \r
 typedef struct RGB\r
@@ -182,8 +177,8 @@ typedef struct RGB
 typedef struct MMU\r
 {\r
     unsigned char mmu_en;\r
-    uint32 base_addr;\r
-    uint32 mmu_flag;     /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/\r
+    uint32_t base_addr;\r
+    uint32_t mmu_flag;     /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/\r
 } MMU;\r
 \r
 \r
@@ -206,94 +201,94 @@ COLOR_FILL;
 \r
 typedef struct FADING\r
 {\r
-    UBYTE b;\r
-    UBYTE g;\r
-    UBYTE r;\r
-    UBYTE res;\r
+    uint8_t b;\r
+    uint8_t g;\r
+    uint8_t r;\r
+    uint8_t res;\r
 }\r
 FADING;\r
 \r
 \r
 typedef struct line_draw_t\r
 {\r
-    POINT start_point;            /* LineDraw_start_point                */\r
-    POINT end_point;              /* LineDraw_end_point                  */\r
-    uint32   color;                  /* LineDraw_color                      */\r
-    uint32   flag;                   /* (enum) LineDrawing mode sel         */\r
-    uint32   line_width;             /* range 1~16 */\r
+    POINT start_point;              /* LineDraw_start_point                */\r
+    POINT end_point;                /* LineDraw_end_point                  */\r
+    uint32_t   color;               /* LineDraw_color                      */\r
+    uint32_t   flag;                /* (enum) LineDrawing mode sel         */\r
+    uint32_t   line_width;          /* range 1~16 */\r
 }\r
 line_draw_t;\r
 \r
 \r
 \r
 struct rga_req {\r
-    UBYTE render_mode;         /* (enum) process mode sel */\r
+    uint8_t render_mode;            /* (enum) process mode sel */\r
     \r
-    rga_img_info_t src;     /* src image info */\r
-    rga_img_info_t dst;     /* dst image info */\r
-    rga_img_info_t pat;     /* patten image info */\r
+    rga_img_info_t src;             /* src image info */\r
+    rga_img_info_t dst;             /* dst image info */\r
+    rga_img_info_t pat;             /* patten image info */\r
 \r
-    uint32 rop_mask_addr;      /* rop4 mask addr */\r
-    uint32 LUT_addr;           /* LUT addr */\r
+    uint32_t rop_mask_addr;         /* rop4 mask addr */\r
+    uint32_t LUT_addr;              /* LUT addr */\r
     \r
-    RECT clip;              /* dst clip window default value is dst_vir */\r
-                            /* value from [0, w-1] / [0, h-1]*/\r
+    RECT clip;                      /* dst clip window default value is dst_vir */\r
+                                    /* value from [0, w-1] / [0, h-1]*/\r
         \r
-    int32_t sina;               /* dst angle  default value 0  16.16 scan from table */\r
-    int32_t cosa;               /* dst angle  default value 0  16.16 scan from table */        \r
-\r
-    uint16_t alpha_rop_flag;     /* alpha rop process flag           */\r
-                            /* ([0] = 1 alpha_rop_enable)       */\r
-                            /* ([1] = 1 rop enable)             */                                                                                                                \r
-                            /* ([2] = 1 fading_enable)          */\r
-                            /* ([3] = 1 PD_enable)              */\r
-                            /* ([4] = 1 alpha cal_mode_sel)     */\r
-                            /* ([5] = 1 dither_enable)          */\r
-                            /* ([6] = 1 gradient fill mode sel) */\r
-                            /* ([7] = 1 AA_enable)              */\r
-\r
-    uint8_t  scale_mode;         /* 0 nearst / 1 bilnear / 2 bicubic */                             \r
+    int32_t sina;                   /* dst angle  default value 0  16.16 scan from table */\r
+    int32_t cosa;                   /* dst angle  default value 0  16.16 scan from table */        \r
+\r
+    uint16_t alpha_rop_flag;        /* alpha rop process flag           */\r
+                                    /* ([0] = 1 alpha_rop_enable)       */\r
+                                    /* ([1] = 1 rop enable)             */                                                                                                                \r
+                                    /* ([2] = 1 fading_enable)          */\r
+                                    /* ([3] = 1 PD_enable)              */\r
+                                    /* ([4] = 1 alpha cal_mode_sel)     */\r
+                                    /* ([5] = 1 dither_enable)          */\r
+                                    /* ([6] = 1 gradient fill mode sel) */\r
+                                    /* ([7] = 1 AA_enable)              */\r
+\r
+    uint8_t  scale_mode;            /* 0 nearst / 1 bilnear / 2 bicubic */                             \r
                             \r
-    uint32 color_key_max;      /* color key max */\r
-    uint32 color_key_min;      /* color key min */     \r
+    uint32_t color_key_max;         /* color key max */\r
+    uint32_t color_key_min;         /* color key min */     \r
 \r
-    uint32 fg_color;           /* foreground color */\r
-    uint32 bg_color;           /* background color */\r
+    uint32_t fg_color;              /* foreground color */\r
+    uint32_t bg_color;              /* background color */\r
 \r
-    COLOR_FILL gr_color;    /* color fill use gradient */\r
+    COLOR_FILL gr_color;            /* color fill use gradient */\r
     \r
     line_draw_t line_draw_info;\r
     \r
     FADING fading;\r
                               \r
-    uint8_t PD_mode;             /* porter duff alpha mode sel */\r
+    uint8_t PD_mode;                /* porter duff alpha mode sel */\r
     \r
-    uint8_t alpha_global_value;  /* global alpha value */\r
+    uint8_t alpha_global_value;     /* global alpha value */\r
      \r
-    uint16_t rop_code;           /* rop2/3/4 code  scan from rop code table*/\r
+    uint16_t rop_code;              /* rop2/3/4 code  scan from rop code table*/\r
     \r
-    uint8_t bsfilter_flag;       /* [2] 0 blur 1 sharp / [1:0] filter_type*/\r
+    uint8_t bsfilter_flag;          /* [2] 0 blur 1 sharp / [1:0] filter_type*/\r
     \r
-    uint8_t palette_mode;        /* (enum) color palatte  0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/\r
+    uint8_t palette_mode;           /* (enum) color palatte  0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/\r
 \r
-    uint8_t yuv2rgb_mode;        /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709  */ \r
+    uint8_t yuv2rgb_mode;           /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709  */ \r
     \r
-    uint8_t endian_mode;         /* 0/big endian 1/little endian*/\r
+    uint8_t endian_mode;            /* 0/big endian 1/little endian*/\r
 \r
-    uint8_t rotate_mode;         /* (enum) rotate mode  */\r
-                            /* 0x0,     no rotate  */\r
-                            /* 0x1,     rotate     */\r
-                            /* 0x2,     x_mirror   */\r
-                            /* 0x3,     y_mirror   */\r
+    uint8_t rotate_mode;            /* (enum) rotate mode  */\r
+                                    /* 0x0,     no rotate  */\r
+                                    /* 0x1,     rotate     */\r
+                                    /* 0x2,     x_mirror   */\r
+                                    /* 0x3,     y_mirror   */\r
 \r
-    uint8_t color_fill_mode;     /* 0 solid color / 1 patten color */\r
+    uint8_t color_fill_mode;        /* 0 solid color / 1 patten color */\r
                                     \r
-    MMU mmu_info;           /* mmu information */\r
+    MMU mmu_info;                   /* mmu information */\r
 \r
-    uint8_t  alpha_rop_mode;    /* ([0~1] alpha mode)       */\r
-                                /* ([2~3] rop   mode)       */\r
-                                /* ([4]   zero  mode en)    */\r
-                                /* ([5]   dst   alpha mode) */\r
+    uint8_t  alpha_rop_mode;        /* ([0~1] alpha mode)       */\r
+                                    /* ([2~3] rop   mode)       */\r
+                                    /* ([4]   zero  mode en)    */\r
+                                    /* ([5]   dst   alpha mode) */\r
 \r
     uint8_t  src_trans_mode;\r
 \r
@@ -388,33 +383,6 @@ typedef struct rga_service_info {
 \r
 \r
 \r
-struct rga_drvdata {\r
-       struct miscdevice miscdev;\r
-       struct device dev;\r
-       void *rga_base;\r
-       int irq0;\r
-\r
-       struct clk *pd_display;\r
-       struct clk *aclk_lcdc;\r
-       struct clk *hclk_lcdc;\r
-       struct clk *aclk_ddr_lcdc;\r
-       struct clk *hclk_cpu_display;\r
-       struct clk *aclk_disp_matrix;\r
-       struct clk *hclk_disp_matrix;\r
-       struct clk *axi_clk;\r
-       struct clk *ahb_clk;\r
-       \r
-       struct mutex    mutex;  // mutex\r
-       \r
-       struct delayed_work power_off_work;\r
-       bool enable;                                                    //clk enable or disable\r
-       void (*rga_irq_callback)(int rga_retval);   //callback function used by aync call\r
-};\r
-\r
-\r
-\r
-\r
-\r
 #define RGA_BASE                 0x10114000\r
 \r
 //General Registers\r

diff --git a/drivers/video/rockchip/rga/rga_drv.c b/drivers/video/rockchip/rga/rga_drv.c
index a58bdd54f34a808c35e71479a9a0390250b79f4b..755c6ece3c6f7c824a89a1f6a6cc53fd6010c213 100755 (executable)
--- a/drivers/video/rockchip/rga/rga_drv.c
+++ b/drivers/video/rockchip/rga/rga_drv.c
@@ -58,13 +58,33 @@
 #define RGA_POWER_OFF_DELAY    4*HZ /* 4s */\r
 #define RGA_TIMEOUT_DELAY      2*HZ /* 2s */\r
 \r
+struct rga_drvdata {\r
+       struct miscdevice miscdev;\r
+       struct device dev;\r
+       void *rga_base;\r
+       int irq0;\r
+\r
+       struct clk *pd_display;\r
+       struct clk *aclk_lcdc;\r
+       struct clk *hclk_lcdc;\r
+       struct clk *aclk_ddr_lcdc;\r
+       struct clk *hclk_cpu_display;\r
+       struct clk *aclk_disp_matrix;\r
+       struct clk *hclk_disp_matrix;\r
+       struct clk *axi_clk;\r
+       struct clk *ahb_clk;\r
+       \r
+       struct mutex    mutex;  // mutex\r
+       \r
+       struct delayed_work power_off_work;\r
+       bool enable;                                                    //clk enable or disable\r
+       void (*rga_irq_callback)(int rga_retval);   //callback function used by aync call\r
+};\r
+\r
 \r
 static struct rga_drvdata *drvdata = NULL;\r
 rga_service_info rga_service;\r
 \r
-#if 1//def RGA_TEST\r
-//uint32_t dst_buf[800*480*4];\r
-#endif\r
 \r
 \r
 static int rga_blit_async(rga_session *session, struct rga_req *req);\r