//===-- PowerPC.h - Top-level interface for PowerPC representation -*- C++ -*-//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the entry points for global functions defined in the LLVM
//===-- PPC32ISelSimple.cpp - A simple instruction selector PowerPC32 -----===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "isel"
MachineFunction *F; // The function we are compiling into
MachineBasicBlock *BB; // The current MBB we are compiling
int VarArgsFrameIndex; // FrameIndex for start of varargs area
-
- /// CollapsedGepOp - This struct is for recording the intermediate results
+
+ /// CollapsedGepOp - This struct is for recording the intermediate results
/// used to calculate the base, index, and offset of a GEP instruction.
struct CollapsedGepOp {
ConstantSInt *offset; // the current offset into the struct/array
offset(o), index(i), size(s) {}
};
- /// FoldedGEP - This struct is for recording the necessary information to
+ /// FoldedGEP - This struct is for recording the necessary information to
/// emit the GEP in a load or store instruction, used by emitGEPOperation.
struct FoldedGEP {
unsigned base;
unsigned index;
ConstantSInt *offset;
FoldedGEP() : base(0), index(0), offset(0) {}
- FoldedGEP(unsigned b, unsigned i, ConstantSInt *o) :
+ FoldedGEP(unsigned b, unsigned i, ConstantSInt *o) :
base(b), index(i), offset(o) {}
};
-
- /// RlwimiRec - This struct is for recording the arguments to a PowerPC
+
+ /// RlwimiRec - This struct is for recording the arguments to a PowerPC
/// rlwimi instruction to be output for a particular Instruction::Or when
/// we recognize the pattern for rlwimi, starting with a shift or and.
- struct RlwimiRec {
+ struct RlwimiRec {
Value *Target, *Insert;
unsigned Shift, MB, ME;
RlwimiRec() : Target(0), Insert(0), Shift(0), MB(0), ME(0) {}
RlwimiRec(Value *tgt, Value *ins, unsigned s, unsigned b, unsigned e) :
Target(tgt), Insert(ins), Shift(s), MB(b), ME(e) {}
};
-
+
// External functions we may use in compiling the Module
- Function *fmodfFn, *fmodFn, *__cmpdi2Fn, *__moddi3Fn, *__divdi3Fn,
+ Function *fmodfFn, *fmodFn, *__cmpdi2Fn, *__moddi3Fn, *__divdi3Fn,
*__umoddi3Fn, *__udivdi3Fn, *__fixsfdiFn, *__fixdfdiFn, *__fixunssfdiFn,
*__fixunsdfdiFn, *__floatdisfFn, *__floatdidfFn, *mallocFn, *freeFn;
// GEPMap - Mapping between basic blocks and GEP definitions
std::map<GetElementPtrInst*, FoldedGEP> GEPMap;
-
+
// RlwimiMap - Mapping between BinaryOperand (Or) instructions and info
// needed to properly emit a rlwimi instruction in its place.
std::map<Instruction *, RlwimiRec> InsertMap;
// flag to set whether or not we need to emit it for this function.
unsigned GlobalBaseReg;
bool GlobalBaseInitialized;
-
+
PPC32ISel(TargetMachine &tm):TM(reinterpret_cast<PPC32TargetMachine&>(tm)),
F(0), BB(0) {}
MachineBasicBlock *MBB,
MachineBasicBlock::iterator MBBI);
void visitSelectInst(SelectInst &SI);
-
-
+
+
// Memory Instructions
void visitLoadInst(LoadInst &I);
void visitStoreInst(StoreInst &I);
void visitAllocaInst(AllocaInst &I);
void visitMallocInst(MallocInst &I);
void visitFreeInst(FreeInst &I);
-
+
// Other operators
void visitShiftInst(ShiftInst &I);
void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
/// emitBitfieldInsert - return true if we were able to fold the sequence of
/// instructions into a bitfield insert (rlwimi).
bool emitBitfieldInsert(User *OpUser, unsigned DestReg);
-
+
/// emitBitfieldExtract - return true if we were able to fold the sequence
/// of instructions into a bitfield extract (rlwinm).
- bool emitBitfieldExtract(MachineBasicBlock *MBB,
+ bool emitBitfieldExtract(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
User *OpUser, unsigned DestReg);
/// arithmetic and logical operations with constants on a register rather
/// than a Value.
///
- void emitBinaryConstOperation(MachineBasicBlock *MBB,
+ void emitBinaryConstOperation(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
- unsigned Op0Reg, ConstantInt *Op1,
+ unsigned Op0Reg, ConstantInt *Op1,
unsigned Opcode, unsigned DestReg);
- /// emitSimpleBinaryOperation - Implement simple binary operators for
- /// integral types. OperatorClass is one of: 0 for Add, 1 for Sub,
+ /// emitSimpleBinaryOperation - Implement simple binary operators for
+ /// integral types. OperatorClass is one of: 0 for Add, 1 for Sub,
/// 2 for And, 3 for Or, 4 for Xor.
///
void emitSimpleBinaryOperation(MachineBasicBlock *BB,
void doMultiply(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
unsigned DestReg, Value *Op0, Value *Op1);
-
+
/// doMultiplyConst - This method will multiply the value in Op0Reg by the
/// value of the ContantInt *CI
- void doMultiplyConst(MachineBasicBlock *MBB,
+ void doMultiplyConst(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
unsigned DestReg, Value *Op0, ConstantInt *CI);
void emitShiftOperation(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
Value *Op, Value *ShiftAmount, bool isLeftShift,
- const Type *ResultTy, ShiftInst *SI,
+ const Type *ResultTy, ShiftInst *SI,
unsigned DestReg);
-
+
/// emitSelectOperation - Common code shared between visitSelectInst and the
/// constant expression support.
///
}
unsigned getReg(Value *V, MachineBasicBlock *MBB,
MachineBasicBlock::iterator IPt);
-
+
/// canUseAsImmediateForOpcode - This method returns whether a ConstantInt
/// is okay to use as an immediate argument to a certain binary operation
bool canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Opcode,
// Treat subfic like addi for the purposes of constant validation
if (Opcode == 5) Opcode = 0;
-
+
// addi, subfic, compare, and non-indexed load take SIMM
bool cond1 = (Opcode < 2)
&& ((int32_t)CI->getRawValue() <= 32767)
unsigned TySize = TM.getTargetData().getTypeSize(Ty);
TySize *= CUI->getValue(); // Get total allocated size...
unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
-
+
// Create a new stack object using the frame manager...
int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
AllocaMap.insert(I, std::make_pair(AI, FrameIdx));
abort();
}
}
-
+
assert(Class <= cInt && "Type not handled yet!");
// Handle bool
BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(C == ConstantBool::True);
return;
}
-
+
// Handle int
if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(C)) {
unsigned uval = CUI->getValue();
} else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
// GV is located at base + distance
unsigned TmpReg = makeAnotherReg(GV->getType());
-
+
// Move value at base + distance into return reg
BuildMI(*MBB, IP, PPC::LOADHiAddr, 2, TmpReg)
.addReg(getGlobalBaseReg()).addGlobalAddress(GV);
unsigned GPR_remaining = 8;
unsigned FPR_remaining = 13;
unsigned GPR_idx = 0, FPR_idx = 0;
- static const unsigned GPR[] = {
+ static const unsigned GPR[] = {
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
PPC::R7, PPC::R8, PPC::R9, PPC::R10,
};
PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
};
-
+
MachineFrameInfo *MFI = F->getFrameInfo();
-
+
for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
I != E; ++I) {
bool ArgLive = !I->use_empty();
}
// doubles require 4 additional bytes and use 2 GPRs of param space
- ArgOffset += 4;
+ ArgOffset += 4;
if (GPR_remaining > 0) {
GPR_remaining--;
GPR_idx++;
static GetElementPtrInst *canFoldGEPIntoLoadOrStore(Value *V) {
if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(V)) {
bool AllUsesAreMem = true;
- for (Value::use_iterator I = GEPI->use_begin(), E = GEPI->use_end();
+ for (Value::use_iterator I = GEPI->use_begin(), E = GEPI->use_end();
I != E; ++I) {
Instruction *User = cast<Instruction>(*I);
const Type *CompTy = Op0->getType();
unsigned Class = getClassB(CompTy);
unsigned Op0r = ExtendOrClear(MBB, IP, Op0);
-
+
// Use crand for lt, gt and crandc for le, ge
unsigned CROpcode = (OpNum == 2 || OpNum == 4) ? PPC::CRAND : PPC::CRANDC;
// ? cr1[lt] : cr1[gt]
if (Class == cByte || Class == cShort || Class == cInt) {
unsigned Op1v = CI->getRawValue() & 0xFFFF;
unsigned OpClass = (CompTy->isSigned()) ? 0 : 2;
-
+
// Treat compare like ADDI for the purposes of immediate suitability
if (canUseAsImmediateForOpcode(CI, OpClass, false)) {
BuildMI(*MBB, IP, OpcodeImm, 2, PPC::CR0).addReg(Op0r).addSImm(Op1v);
const Type *Ty = Op0->getType();
unsigned Class = getClassB(Ty);
unsigned Opcode = I.getOpcode();
- unsigned OpNum = getSetCCNumber(Opcode);
+ unsigned OpNum = getSetCCNumber(Opcode);
unsigned DestReg = getReg(I);
// If the comparison type is byte, short, or int, then we can emit a
if (CI && CI->getRawValue() == 0) {
unsigned Op0Reg = ExtendOrClear(BB, MI, Op0);
-
+
// comparisons against constant zero and negative one often have shorter
// and/or faster sequences than the set-and-branch general case, handled
// below.
BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(TempReg).addImm(27)
.addImm(5).addImm(31);
break;
- }
+ }
case 1: { // ne0
unsigned TempReg = makeAnotherReg(Type::IntTy);
BuildMI(*BB, MI, PPC::ADDIC, 2, TempReg).addReg(Op0Reg).addSImm(-1);
BuildMI(*BB, MI, PPC::SUBFE, 2, DestReg).addReg(TempReg).addReg(Op0Reg);
break;
- }
+ }
case 2: { // lt0, always false if unsigned
if (Ty->isSigned())
BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(Op0Reg).addImm(1)
break;
}
case 3: { // ge0, always true if unsigned
- if (Ty->isSigned()) {
+ if (Ty->isSigned()) {
unsigned TempReg = makeAnotherReg(Type::IntTy);
BuildMI(*BB, MI, PPC::RLWINM, 4, TempReg).addReg(Op0Reg).addImm(1)
.addImm(31).addImm(31);
case 4: { // gt0, equivalent to ne0 if unsigned
unsigned Temp1 = makeAnotherReg(Type::IntTy);
unsigned Temp2 = makeAnotherReg(Type::IntTy);
- if (Ty->isSigned()) {
+ if (Ty->isSigned()) {
BuildMI(*BB, MI, PPC::NEG, 2, Temp1).addReg(Op0Reg);
BuildMI(*BB, MI, PPC::ANDC, 2, Temp2).addReg(Temp1).addReg(Op0Reg);
BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(Temp2).addImm(1)
case 5: { // le0, equivalent to eq0 if unsigned
unsigned Temp1 = makeAnotherReg(Type::IntTy);
unsigned Temp2 = makeAnotherReg(Type::IntTy);
- if (Ty->isSigned()) {
+ if (Ty->isSigned()) {
BuildMI(*BB, MI, PPC::NEG, 2, Temp1).addReg(Op0Reg);
BuildMI(*BB, MI, PPC::ORC, 2, Temp2).addReg(Op0Reg).addReg(Temp1);
BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(Temp2).addImm(1)
const BasicBlock *LLVM_BB = BB->getBasicBlock();
ilist<MachineBasicBlock>::iterator It = BB;
++It;
-
+
// thisMBB:
// ...
// cmpTY cr0, r1, r2
emitSelectOperation(BB, MII, SI.getCondition(), SI.getTrueValue(),
SI.getFalseValue(), DestReg);
}
-
+
/// emitSelect - Common code shared between visitSelectInst and the constant
/// expression support.
void PPC32ISel::emitSelectOperation(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
- Value *Cond, Value *TrueVal,
+ Value *Cond, Value *TrueVal,
Value *FalseVal, unsigned DestReg) {
unsigned SelectClass = getClassB(TrueVal->getType());
unsigned Opcode;
BB = sinkMBB;
BuildMI(BB, PPC::PHI, 4, DestReg).addReg(FalseValue)
.addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
-
+
// For a register pair representing a long value, define the top part.
if (getClassB(TrueVal->getType()) == cLong)
BuildMI(BB, PPC::PHI, 4, DestReg+1).addReg(FalseValue+1)
BB->addSuccessor(MBBMap[BI.getSuccessor(0)]);
if (BI.isConditional())
BB->addSuccessor(MBBMap[BI.getSuccessor(1)]);
-
+
BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
if (!BI.isConditional()) { // Unconditional branch?
- if (BI.getSuccessor(0) != NextBB)
+ if (BI.getSuccessor(0) != NextBB)
BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
return;
}
-
+
// See if we can fold the setcc into the branch itself...
SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(BI.getCondition());
if (SCI == 0) {
unsigned Opcode = getPPCOpcodeForSetCCOpcode(SCI->getOpcode());
MachineBasicBlock::iterator MII = BB->end();
EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
-
+
if (BI.getSuccessor(0) != NextBB) {
BuildMI(BB, PPC::COND_BRANCH, 4).addReg(PPC::CR0).addImm(Opcode)
.addMBB(MBBMap[BI.getSuccessor(0)])
default: assert(0 && "Unknown class!");
}
- // Just to be safe, we'll always reserve the full 24 bytes of linkage area
+ // Just to be safe, we'll always reserve the full 24 bytes of linkage area
// plus 32 bytes of argument space in case any called code gets funky on us.
if (NumBytes < 56) NumBytes = 56;
// Offset to the paramater area on the stack is 24.
int GPR_remaining = 8, FPR_remaining = 13;
unsigned GPR_idx = 0, FPR_idx = 0;
- static const unsigned GPR[] = {
+ static const unsigned GPR[] = {
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
PPC::R7, PPC::R8, PPC::R9, PPC::R10,
};
static const unsigned FPR[] = {
- PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6,
- PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12,
+ PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6,
+ PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12,
PPC::F13
};
-
+
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
unsigned ArgReg;
switch (getClassB(Args[i].Ty)) {
// Promote arg to 32 bits wide into a temporary register...
ArgReg = makeAnotherReg(Type::UIntTy);
promote32(ArgReg, Args[i]);
-
+
// Reg or stack?
if (GPR_remaining > 0) {
BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
CallMI->addRegOperand(FPR[FPR_idx], MachineOperand::Use);
FPR_remaining--;
FPR_idx++;
-
+
// If this is a vararg function, and there are GPRs left, also
// pass the float in an int. Otherwise, put it on the stack.
if (isVarArg) {
if (isVarArg) {
BuildMI(BB, PPC::STFD, 3).addReg(ArgReg).addSImm(ArgOffset)
.addReg(PPC::R1);
-
+
// Doubles can be split across reg + stack for varargs
if (GPR_remaining > 0) {
BuildMI(BB, PPC::LWZ, 2, GPR[GPR_idx]).addSImm(ArgOffset)
GPR_remaining--;
GPR_idx++;
break;
-
+
default: assert(0 && "Unknown class!");
}
ArgOffset += 4;
} else {
BuildMI(BB, PPC::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
}
-
+
BuildMI(BB, PPC::IMPLICIT_DEF, 0, PPC::LR);
BB->push_back(CallMI);
-
+
// These functions are automatically eliminated by the prolog/epilog pass
BuildMI(BB, PPC::ADJCALLSTACKUP, 1).addImm(NumBytes);
unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
bool isVarArg = F ? F->getFunctionType()->isVarArg() : true;
doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args, isVarArg);
-}
+}
/// dyncastIsNan - Return the operand of an isnan operation if this is an isnan.
case Intrinsic::vastart:
// Get the address of the first vararg value...
TmpReg1 = getReg(CI);
- addFrameReference(BuildMI(BB, PPC::ADDI, 2, TmpReg1), VarArgsFrameIndex,
+ addFrameReference(BuildMI(BB, PPC::ADDI, 2, TmpReg1), VarArgsFrameIndex,
0, false);
return;
if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
MachineFrameInfo *MFI = F->getFrameInfo();
unsigned NumBytes = MFI->getStackSize();
-
+
BuildMI(BB, PPC::LWZ, 2, TmpReg1).addSImm(NumBytes+8)
.addReg(PPC::R1);
} else {
BuildMI(BB, PPC::LI, 1, TmpReg1).addSImm(0);
}
return;
-
+
#if 0
// This may be useful for supporting isunordered
case Intrinsic::isnan:
BuildMI(BB, PPC::RLWINM, 4, TmpReg3).addReg(TmpReg2).addImm(4).addImm(31).addImm(31);
return;
#endif
-
+
default: assert(0 && "Error: unknown intrinsics should have been lowered!");
}
}
.addReg(InsertReg).addImm(RR.Shift).addImm(RR.MB).addImm(RR.ME);
return;
}
-
+
unsigned Class = getClassB(B.getType());
Value *Op0 = B.getOperand(0), *Op1 = B.getOperand(1);
emitSimpleBinaryOperation(BB, MI, &B, Op0, Op1, OperatorClass, DestReg);
// not, since all 1's are not contiguous.
static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
bool isRun = true;
- MB = 0;
+ MB = 0;
ME = 0;
// look for first set bit
break;
}
}
-
+
// look for last set bit
for (; i < 32; i++) {
if ((Val & (1 << (31 - i))) == 0)
if ((Val & (1 << (31 - i))) != 0)
break;
}
-
+
// if we exhausted all the bits, we found a match at this point for 0*1*0*
if (i == 32)
return true;
if ((Val & (1 << (31 - i))) == 0)
break;
}
-
+
// if we exhausted all the bits, then we found a match for 1*0*1*, otherwise,
// the value is not a run of ones.
if (i == 32)
/// second operand is a constant int. Optionally, set OrI to the Or instruction
/// that is the sole user of OpUser, and Op1User to the other operand of the Or
/// instruction.
-static bool isInsertAndHalf(User *OpUser, Instruction **Op1User,
+static bool isInsertAndHalf(User *OpUser, Instruction **Op1User,
Instruction **OrI, unsigned &Mask) {
// If this instruction doesn't have one use, then return false.
if (!OpUser->hasOneUse())
return false;
-
+
Mask = 0xFFFFFFFF;
if (BinaryOperator *BO = dyn_cast<BinaryOperator>(OpUser))
if (BO->getOpcode() == Instruction::And) {
/// instruction that is either used directly by the or instruction, or is used
/// by an and instruction whose second operand is a constant int, and which is
/// used by the or instruction.
-static bool isInsertShiftHalf(User *OpUser, Instruction **Op1User,
- Instruction **OrI, Instruction **OptAndI,
+static bool isInsertShiftHalf(User *OpUser, Instruction **Op1User,
+ Instruction **OrI, Instruction **OptAndI,
unsigned &Shift, unsigned &Mask) {
// If this instruction doesn't have one use, then return false.
if (!OpUser->hasOneUse())
return false;
-
+
Mask = 0xFFFFFFFF;
if (ShiftInst *SI = dyn_cast<ShiftInst>(OpUser)) {
if (ConstantInt *CI = dyn_cast<ConstantInt>(SI->getOperand(1))) {
return false;
}
-/// emitBitfieldInsert - turn a shift used only by an and with immediate into
+/// emitBitfieldInsert - turn a shift used only by an and with immediate into
/// the rotate left word immediate then mask insert (rlwimi) instruction.
/// Patterns matched:
/// 1. or shl, and 5. or (shl-and), and 9. or and, and
matched = true;
else if (isInsertShiftHalf(Op1User, 0, 0, &OptAndI, Amount, InsMask))
matched = true;
-
+
// Look for cases 1, 3, 5, and 7. Force the shift argument to be the one
// inserted into the target, since rlwimi can only rotate the value inserted,
// not the value being inserted into.
std::swap(Op0User, Op1User);
matched = true;
}
-
+
// We didn't succeed in matching one of the patterns, so return false
if (matched == false)
return false;
-
+
// If the masks xor to -1, and the insert mask is a run of ones, then we have
// succeeded in matching one of the cases for generating rlwimi. Update the
// skip lists and users of the Instruction::Or.
SkipList.push_back(Op0User);
SkipList.push_back(Op1User);
SkipList.push_back(OptAndI);
- InsertMap[OrI] = RlwimiRec(Op0User->getOperand(0), Op1User->getOperand(0),
+ InsertMap[OrI] = RlwimiRec(Op0User->getOperand(0), Op1User->getOperand(0),
Amount, MB, ME);
return true;
}
/// emitBitfieldExtract - turn a shift used only by an and with immediate into the
/// rotate left word immediate then and with mask (rlwinm) instruction.
-bool PPC32ISel::emitBitfieldExtract(MachineBasicBlock *MBB,
+bool PPC32ISel::emitBitfieldExtract(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
User *OpUser, unsigned DestReg) {
return false;
if (isExtractShiftHalf)
if (isExtractAndHalf)
matched = true;
-
+
if (matched == false && isExtractAndHalf)
if (isExtractShiftHalf)
matched = true;
-
+
if (matched == false)
return false;
}
/// emitBinaryConstOperation - Implement simple binary operators for integral
-/// types with a constant operand. Opcode is one of: 0 for Add, 1 for Sub,
+/// types with a constant operand. Opcode is one of: 0 for Add, 1 for Sub,
/// 2 for And, 3 for Or, 4 for Xor, and 5 for Subtract-From.
///
-void PPC32ISel::emitBinaryConstOperation(MachineBasicBlock *MBB,
+void PPC32ISel::emitBinaryConstOperation(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
- unsigned Op0Reg, ConstantInt *Op1,
+ unsigned Op0Reg, ConstantInt *Op1,
unsigned Opcode, unsigned DestReg) {
static const unsigned OpTab[] = {
PPC::ADD, PPC::SUB, PPC::AND, PPC::OR, PPC::XOR, PPC::SUBF
Op1 = cast<ConstantInt>(ConstantExpr::getNeg(Op1));
Opcode = 0;
}
-
+
// xor X, -1 -> not X
if (Opcode == 4 && Op1->isAllOnesValue()) {
BuildMI(*MBB, IP, PPC::NOR, 2, DestReg).addReg(Op0Reg).addReg(Op0Reg);
return;
}
-
+
if (Opcode == 2 && !Op1->isNullValue()) {
unsigned MB, ME, mask = Op1->getRawValue();
if (isRunOfOnes(mask, MB, ME)) {
bool WontSignExtend = (0 == (Op1->getRawValue() & 0x8000));
// For Add, Sub, and SubF the instruction takes a signed immediate. For And,
- // Or, and Xor, the instruction takes an unsigned immediate. There is no
+ // Or, and Xor, the instruction takes an unsigned immediate. There is no
// shifted immediate form of SubF so disallow its opcode for those constants.
if (canUseAsImmediateForOpcode(Op1, Opcode, false)) {
if (Opcode < 2 || Opcode == 5)
///
void PPC32ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
- BinaryOperator *BO,
+ BinaryOperator *BO,
Value *Op0, Value *Op1,
- unsigned OperatorClass,
+ unsigned OperatorClass,
unsigned DestReg) {
// Arithmetic and Bitwise operators
static const unsigned OpcodeTab[] = {
{ PPC::ADDC, PPC::SUBFC, PPC::AND, PPC::OR, PPC::XOR },
{ PPC::ADDE, PPC::SUBFE, PPC::AND, PPC::OR, PPC::XOR }
};
-
+
unsigned Class = getClassB(Op0->getType());
if (Class == cFP32 || Class == cFP64) {
if (Class != cLong) {
if (emitBitfieldInsert(BO, DestReg))
return;
-
+
unsigned Op0r = getReg(Op0, MBB, IP);
emitBinaryConstOperation(MBB, IP, Op0r, CI, OperatorClass, DestReg);
return;
unsigned DestReg, Value *Op0, Value *Op1) {
unsigned Class0 = getClass(Op0->getType());
unsigned Class1 = getClass(Op1->getType());
-
+
unsigned Op0r = getReg(Op0, MBB, IP);
unsigned Op1r = getReg(Op1, MBB, IP);
-
+
// 64 x 64 -> 64
if (Class0 == cLong && Class1 == cLong) {
unsigned Tmp1 = makeAnotherReg(Type::IntTy);
BuildMI(*MBB, IP, PPC::ADD, 2, DestReg).addReg(Tmp3).addReg(Tmp4);
return;
}
-
+
// 64 x 32 or less, promote 32 to 64 and do a 64 x 64
if (Class0 == cLong && Class1 <= cInt) {
unsigned Tmp0 = makeAnotherReg(Type::IntTy);
BuildMI(*MBB, IP, PPC::ADD, 2, DestReg).addReg(Tmp3).addReg(Tmp4);
return;
}
-
+
// 32 x 32 -> 32
if (Class0 <= cInt && Class1 <= cInt) {
BuildMI(*MBB, IP, PPC::MULLW, 2, DestReg).addReg(Op0r).addReg(Op1r);
return;
}
-
+
assert(0 && "doMultiply cannot operate on unknown type!");
}
BuildMI(*MBB, IP, PPC::LI, 1, DestReg+1).addSImm(0);
return;
}
-
+
// Mul op0, 1 ==> op0
if (CI->equalsInt(1)) {
unsigned Op0r = getReg(Op0, MBB, IP);
emitShiftOperation(MBB, IP, Op0, ShiftCI, true, Op0->getType(), 0, DestReg);
return;
}
-
+
// If 32 bits or less and immediate is in right range, emit mul by immediate
if (Class == cByte || Class == cShort || Class == cInt) {
if (canUseAsImmediateForOpcode(CI, 0, false)) {
return;
}
}
-
+
doMultiply(MBB, IP, DestReg, Op0, CI);
}
// Floating point divide...
emitBinaryFPOperation(MBB, IP, Op0, Op1, 3, ResultReg);
return;
- } else {
+ } else {
// Floating point remainder via fmod(double x, double y);
unsigned Op0Reg = getReg(Op0, MBB, IP);
unsigned Op1Reg = getReg(Op1, MBB, IP);
if (log2V != 0 && Ty->isSigned()) {
unsigned Op0Reg = getReg(Op0, MBB, IP);
unsigned TmpReg = makeAnotherReg(Op0->getType());
-
+
BuildMI(*MBB, IP, PPC::SRAWI, 2, TmpReg).addReg(Op0Reg).addImm(log2V);
BuildMI(*MBB, IP, PPC::ADDZE, 1, ResultReg).addReg(TmpReg);
return;
///
void PPC32ISel::emitShiftOperation(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
- Value *Op, Value *ShiftAmount,
+ Value *Op, Value *ShiftAmount,
bool isLeftShift, const Type *ResultTy,
ShiftInst *SI, unsigned DestReg) {
bool isSigned = ResultTy->isSigned ();
unsigned Class = getClass (ResultTy);
-
+
// Longs, as usual, are handled specially...
if (Class == cLong) {
unsigned SrcReg = getReg (Op, MBB, IP);
unsigned TmpReg5 = makeAnotherReg(Type::IntTy);
unsigned TmpReg6 = makeAnotherReg(Type::IntTy);
unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
-
+
if (isLeftShift) {
BuildMI(*MBB, IP, PPC::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
.addSImm(32);
BuildMI(*MBB, IP, PPC::SLW, 2, DestReg+1).addReg(SrcReg+1)
.addReg(ShiftAmountReg);
} else {
- if (isSigned) { // shift right algebraic
+ if (isSigned) { // shift right algebraic
MachineBasicBlock *TmpMBB =new MachineBasicBlock(BB->getBasicBlock());
MachineBasicBlock *PhiMBB =new MachineBasicBlock(BB->getBasicBlock());
MachineBasicBlock *OldMBB = BB;
BuildMI(*MBB, IP, PPC::SRAW, 2, DestReg).addReg(SrcReg)
.addReg(ShiftAmountReg);
BuildMI(*MBB, IP, PPC::BLE, 2).addReg(PPC::CR0).addMBB(PhiMBB);
-
+
// OrMBB:
// Select correct least significant half if the shift amount > 32
BB = TmpMBB;
unsigned OrReg = makeAnotherReg(Type::IntTy);
BuildMI(BB, PPC::OR, 2, OrReg).addReg(TmpReg6).addReg(TmpReg6);
TmpMBB->addSuccessor(PhiMBB);
-
+
BB = PhiMBB;
BuildMI(BB, PPC::PHI, 4, DestReg+1).addReg(TmpReg4).addMBB(OldMBB)
.addReg(OrReg).addMBB(TmpMBB);
// The shift amount is constant, guaranteed to be a ubyte. Get its value.
assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
unsigned Amount = CUI->getValue();
-
+
// If this is a shift with one use, and that use is an And instruction,
// then attempt to emit a bitfield operation.
if (SI && emitBitfieldInsert(SI, DestReg))
return;
-
+
unsigned SrcReg = getReg (Op, MBB, IP);
if (Amount == 0) {
BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
///
void PPC32ISel::visitLoadInst(LoadInst &I) {
// Immediate opcodes, for reg+imm addressing
- static const unsigned ImmOpcodes[] = {
- PPC::LBZ, PPC::LHZ, PPC::LWZ,
+ static const unsigned ImmOpcodes[] = {
+ PPC::LBZ, PPC::LHZ, PPC::LWZ,
PPC::LFS, PPC::LFD, PPC::LWZ
};
// Indexed opcodes, for reg+reg addressing
unsigned IdxOpcode = IdxOpcodes[Class];
unsigned DestReg = getReg(I);
Value *SourceAddr = I.getOperand(0);
-
+
if (Class == cShort && I.getType()->isSigned()) ImmOpcode = PPC::LHA;
if (Class == cShort && I.getType()->isSigned()) IdxOpcode = PPC::LHAX;
}
return;
}
-
+
// If the offset fits in 16 bits, we can emit a reg+imm load, otherwise, we
// use the index from the FoldedGEP struct and use reg+reg addressing.
if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {
}
return;
}
-
+
// The fallback case, where the load was from a source that could not be
- // folded into the load instruction.
+ // folded into the load instruction.
unsigned SrcAddrReg = getReg(SourceAddr);
-
+
if (Class == cLong) {
BuildMI(BB, ImmOpcode, 2, DestReg).addSImm(0).addReg(SrcAddrReg);
BuildMI(BB, ImmOpcode, 2, DestReg+1).addSImm(4).addReg(SrcAddrReg);
void PPC32ISel::visitStoreInst(StoreInst &I) {
// Immediate opcodes, for reg+imm addressing
static const unsigned ImmOpcodes[] = {
- PPC::STB, PPC::STH, PPC::STW,
+ PPC::STB, PPC::STH, PPC::STW,
PPC::STFS, PPC::STFD, PPC::STW
};
// Indexed opcodes, for reg+reg addressing
static const unsigned IdxOpcodes[] = {
- PPC::STBX, PPC::STHX, PPC::STWX,
+ PPC::STBX, PPC::STHX, PPC::STWX,
PPC::STFSX, PPC::STFDX, PPC::STWX
};
-
+
Value *SourceAddr = I.getOperand(1);
const Type *ValTy = I.getOperand(0)->getType();
unsigned Class = getClassB(ValTy);
addFrameReference(BuildMI(BB, ImmOpcode, 3).addReg(ValReg+1), FI, 4);
return;
}
-
+
// If the offset fits in 16 bits, we can emit a reg+imm store, otherwise, we
// use the index from the FoldedGEP struct and use reg+reg addressing.
if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {
unsigned baseReg = GEPMap[GEPI].base;
unsigned indexReg = GEPMap[GEPI].index;
ConstantSInt *offset = GEPMap[GEPI].offset;
-
+
if (Class != cLong) {
if (indexReg == 0)
BuildMI(BB, ImmOpcode, 3).addReg(ValReg).addSImm(offset->getValue())
}
return;
}
-
+
// If the store address wasn't the only use of a GEP, we fall back to the
// standard path: store the ValReg at the value in AddressReg.
unsigned AddressReg = getReg(I.getOperand(1));
if (!isa<GetElementPtrInst>(*I)) {
AllUsesAreGEPs = false;
break;
- }
+ }
if (AllUsesAreGEPs) return;
}
-
+
unsigned DestReg = getReg(CI);
MachineBasicBlock::iterator MI = BB->end();
if (SI && (SI->getOperand(1) == &CI)) {
unsigned SrcReg = getReg(Op, BB, MI);
BuildMI(*BB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
- return;
+ return;
}
}
if (!isa<StoreInst>(*I)) {
AllUsesAreStores = false;
break;
- }
+ }
// Turn this cast directly into a move instruction, which the register
// allocator will deal with.
- if (AllUsesAreStores) {
+ if (AllUsesAreStores) {
unsigned SrcReg = getReg(Op, BB, MI);
BuildMI(*BB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
- return;
+ return;
}
}
emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
BuildMI(*MBB, IP, PPC::FMR, 1, DestReg).addReg(SrcReg);
return;
}
-
+
// Handle cast of Double -> Float
if (SrcClass == cFP64 && DestClass == cFP32) {
BuildMI(*MBB, IP, PPC::FRSP, 1, DestReg).addReg(SrcReg);
return;
}
-
+
// Handle casts from integer to floating point now...
if (DestClass == cFP32 || DestClass == cFP64) {
doCall(ValueRecord(ClrReg, DestTy), TheCall, ClrArgs, false);
BuildMI(BB, PPC::B, 1).addMBB(PhiMBB);
BB->addSuccessor(PhiMBB);
-
+
// SetMBB
BB = SetMBB;
unsigned SetReg = makeAnotherReg(DestTy);
unsigned CallReg = makeAnotherReg(DestTy);
unsigned ShiftedReg = makeAnotherReg(SrcTy);
ConstantSInt *Const1 = ConstantSInt::get(Type::IntTy, 1);
- emitShiftOperation(BB, BB->end(), Src, Const1, false, SrcTy, 0,
+ emitShiftOperation(BB, BB->end(), Src, Const1, false, SrcTy, 0,
ShiftedReg);
SetArgs.push_back(ValueRecord(ShiftedReg, SrcTy));
TheCall = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
unsigned SetOpcode = (DestClass == cFP32) ? PPC::FADDS : PPC::FADD;
BuildMI(BB, SetOpcode, 2, SetReg).addReg(CallReg).addReg(CallReg);
BB->addSuccessor(PhiMBB);
-
+
// PhiMBB
BB = PhiMBB;
BuildMI(BB, PPC::PHI, 4, DestReg).addReg(ClrReg).addMBB(ClrMBB)
}
return;
}
-
+
// Make sure we're dealing with a full 32 bits
if (SrcClass < cInt) {
unsigned TmpReg = makeAnotherReg(Type::IntTy);
promote32(TmpReg, ValueRecord(SrcReg, SrcTy));
SrcReg = TmpReg;
}
-
+
// Spill the integer to memory and reload it from there.
// Also spill room for a special conversion constant
int ValueFrameIdx =
unsigned constantHi = makeAnotherReg(Type::IntTy);
unsigned TempF = makeAnotherReg(Type::DoubleTy);
-
+
if (!SrcTy->isSigned()) {
ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, 0x1.000000p52);
unsigned ConstF = getReg(CFP, BB, IP);
BuildMI(*MBB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330);
- addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(constantHi),
+ addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(constantHi),
ValueFrameIdx);
- addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(SrcReg),
+ addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(SrcReg),
ValueFrameIdx, 4);
addFrameReference(BuildMI(*MBB, IP, PPC::LFD, 2, TempF), ValueFrameIdx);
BuildMI(*MBB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
unsigned ConstF = getReg(CFP, BB, IP);
unsigned TempLo = makeAnotherReg(Type::IntTy);
BuildMI(*MBB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330);
- addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(constantHi),
+ addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(constantHi),
ValueFrameIdx);
BuildMI(*MBB, IP, PPC::XORIS, 2, TempLo).addReg(SrcReg).addImm(0x8000);
- addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(TempLo),
+ addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(TempLo),
ValueFrameIdx, 4);
addFrameReference(BuildMI(*MBB, IP, PPC::LFD, 2, TempF), ValueFrameIdx);
BuildMI(*MBB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
if (DestTy->isSigned()) {
unsigned TempReg = makeAnotherReg(Type::DoubleTy);
-
+
// Convert to integer in the FP reg and store it to a stack slot
BuildMI(*MBB, IP, PPC::FCTIWZ, 1, TempReg).addReg(SrcReg);
addFrameReference(BuildMI(*MBB, IP, PPC::STFD, 3)
.addReg(TempReg), ValueFrameIdx);
// There is no load signed byte opcode, so we must emit a sign extend for
- // that particular size. Make sure to source the new integer from the
+ // that particular size. Make sure to source the new integer from the
// correct offset.
if (DestClass == cByte) {
unsigned TempReg2 = makeAnotherReg(DestTy);
- addFrameReference(BuildMI(*MBB, IP, PPC::LBZ, 2, TempReg2),
+ addFrameReference(BuildMI(*MBB, IP, PPC::LBZ, 2, TempReg2),
ValueFrameIdx, 7);
BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(TempReg2);
} else {
int offset = (DestClass == cShort) ? 6 : 4;
unsigned LoadOp = (DestClass == cShort) ? PPC::LHA : PPC::LWZ;
- addFrameReference(BuildMI(*MBB, IP, LoadOp, 2, DestReg),
+ addFrameReference(BuildMI(*MBB, IP, LoadOp, 2, DestReg),
ValueFrameIdx, offset);
}
} else {
unsigned ConvReg = makeAnotherReg(Type::DoubleTy);
unsigned IntTmp = makeAnotherReg(Type::IntTy);
unsigned XorReg = makeAnotherReg(Type::IntTy);
- int FrameIdx =
+ int FrameIdx =
F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
// Update machine-CFG edges
MachineBasicBlock *XorMBB = new MachineBasicBlock(BB->getBasicBlock());
}
// Check our invariants
- assert((SrcClass <= cInt || SrcClass == cLong) &&
+ assert((SrcClass <= cInt || SrcClass == cLong) &&
"Unhandled source class for cast operation!");
- assert((DestClass <= cInt || DestClass == cLong) &&
+ assert((DestClass <= cInt || DestClass == cLong) &&
"Unhandled destination class for cast operation!");
bool sourceUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
bool destUnsigned = DestTy->isUnsigned();
- // Unsigned -> Unsigned, clear if larger,
+ // Unsigned -> Unsigned, clear if larger,
if (sourceUnsigned && destUnsigned) {
// handle long dest class now to keep switch clean
if (DestClass == cLong) {
// multiple definitions of the base register.
if (GEPIsFolded && (GEPMap[GEPI].base != 0))
return;
-
+
Value *Src = GEPI->getOperand(0);
User::op_iterator IdxBegin = GEPI->op_begin()+1;
User::op_iterator IdxEnd = GEPI->op_end();
const TargetData &TD = TM.getTargetData();
const Type *Ty = Src->getType();
int32_t constValue = 0;
-
+
// Record the operations to emit the GEP in a vector so that we can emit them
// after having analyzed the entire instruction.
std::vector<CollapsedGepOp> ops;
-
+
// GEPs have zero or more indices; we must perform a struct access
// or array access for each one.
for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
// type is the type of the elements in the array).
Ty = SqTy->getElementType();
unsigned elementSize = TD.getTypeSize(Ty);
-
+
if (ConstantInt *C = dyn_cast<ConstantInt>(idx)) {
if (ConstantSInt *CS = dyn_cast<ConstantSInt>(C))
constValue += CS->getValue() * elementSize;
TmpReg1 = makeAnotherReg(Type::IntTy);
doMultiplyConst(MBB, IP, TmpReg1, cgo.index, cgo.size);
}
-
+
unsigned TmpReg2;
- if (cgo.offset->isNullValue()) {
+ if (cgo.offset->isNullValue()) {
TmpReg2 = TmpReg1;
} else {
TmpReg2 = makeAnotherReg(Type::IntTy);
emitBinaryConstOperation(MBB, IP, TmpReg1, cgo.offset, 0, TmpReg2);
}
-
+
if (indexReg == 0)
indexReg = TmpReg2;
else {
indexReg = TmpReg3;
}
}
-
+
// We now have a base register, an index register, and possibly a constant
// remainder. If the GEP is going to be folded, we try to generate the
// optimal addressing mode.
ConstantSInt *remainder = ConstantSInt::get(Type::IntTy, constValue);
-
+
// If we are emitting this during a fold, copy the current base register to
// the target, and save the current constant offset so the folding load or
// store can try and use it as an immediate.
// statically stack allocate the space, so we don't need to do anything here.
//
if (dyn_castFixedAlloca(&I)) return;
-
+
// Find the data size of the alloca inst's getAllocatedType.
const Type *Ty = I.getAllocatedType();
unsigned TySize = TM.getTargetData().getTypeSize(Ty);
// Create a register to hold the temporary result of multiplying the type size
// constant by the variable amount.
unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
-
+
// TotalSizeReg = mul <numelements>, <TypeSize>
MachineBasicBlock::iterator MBBI = BB->end();
ConstantUInt *CUI = ConstantUInt::get(Type::UIntTy, TySize);
unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
BuildMI(BB, PPC::RLWINM, 4, AlignedSize).addReg(AddedSizeReg).addImm(0)
.addImm(0).addImm(27);
-
+
// Subtract size from stack pointer, thereby allocating some space.
BuildMI(BB, PPC::SUBF, 2, PPC::R1).addReg(AlignedSize).addReg(PPC::R1);
std::vector<ValueRecord> Args;
Args.push_back(ValueRecord(Arg, Type::UIntTy));
- MachineInstr *TheCall =
+ MachineInstr *TheCall =
BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(mallocFn, true);
doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args, false);
}
void PPC32ISel::visitFreeInst(FreeInst &I) {
std::vector<ValueRecord> Args;
Args.push_back(ValueRecord(I.getOperand(0)));
- MachineInstr *TheCall =
+ MachineInstr *TheCall =
BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(freeFn, true);
doCall(ValueRecord(0, Type::VoidTy), TheCall, Args, false);
}
-
+
/// createPPC32ISelSimple - This pass converts an LLVM function into a machine
/// code representation is a very simple peep-hole fashion.
///
//===- PPC32JITInfo.h - PowerPC/Darwin JIT interface --------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the PowerPC implementation of the TargetJITInfo class.
//===-- PPC64CodeEmitter.cpp - JIT Code Emitter for PPC64 -----*- C++ -*-=//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
//
//===----------------------------------------------------------------------===//
//
// This file was developed by Nate Begeman and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file defines a pattern matching instruction selector for 64 bit PowerPC.
addRegisterClass(MVT::i64, PPC64::GPRCRegisterClass);
addRegisterClass(MVT::f32, PPC64::FPRCRegisterClass);
addRegisterClass(MVT::f64, PPC64::FPRCRegisterClass);
-
+
// PowerPC has no intrinsics for these particular operations
setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
setShiftAmountFlavor(Extend); // shl X, 32 == 0
addLegalFPImmediate(+0.0); // Necessary for FSEL
- addLegalFPImmediate(-0.0); //
+ addLegalFPImmediate(-0.0); //
computeRegisterProperties();
}
/// lower the arguments for the specified function, into the specified DAG.
virtual std::vector<SDOperand>
LowerArguments(Function &F, SelectionDAG &DAG);
-
+
/// LowerCallTo - This hook lowers an abstract call to a function into an
/// actual call.
virtual std::pair<SDOperand, SDOperand>
LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
-
+
virtual std::pair<SDOperand, SDOperand>
LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
-
+
virtual std::pair<SDOperand,SDOperand>
LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
const Type *ArgTy, SelectionDAG &DAG);
MachineFrameInfo *MFI = MF.getFrameInfo();
MachineBasicBlock& BB = MF.front();
std::vector<SDOperand> ArgValues;
-
- // Due to the rather complicated nature of the PowerPC ABI, rather than a
+
+ // Due to the rather complicated nature of the PowerPC ABI, rather than a
// fixed size array of physical args, for the sake of simplicity let the STL
// handle tracking them for us.
std::vector<unsigned> argVR, argPR, argOp;
unsigned GPR_remaining = 8;
unsigned FPR_remaining = 13;
unsigned GPR_idx = 0, FPR_idx = 0;
- static const unsigned GPR[] = {
+ static const unsigned GPR[] = {
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
PPC::R7, PPC::R8, PPC::R9, PPC::R10,
};
SDOperand newroot, argt;
bool needsLoad = false;
MVT::ValueType ObjectVT = getValueType(I->getType());
-
+
switch (ObjectVT) {
default: assert(0 && "Unhandled argument type!");
case MVT::i1:
case MVT::i8:
case MVT::i16:
- case MVT::i32:
+ case MVT::i32:
case MVT::i64:
if (GPR_remaining > 0) {
BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
case MVT::f64:
if (FPR_remaining > 0) {
BuildMI(&BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
- argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
+ argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
DAG.getRoot());
--FPR_remaining;
++FPR_idx;
}
break;
}
-
+
// We need to load the argument to a virtual register if we determined above
- // that we ran out of physical registers of the appropriate type
+ // that we ran out of physical registers of the appropriate type
if (needsLoad) {
unsigned SubregOffset = 0;
switch (ObjectVT) {
case MVT::i1:
case MVT::i8: SubregOffset = 7; break;
case MVT::i16: SubregOffset = 6; break;
- case MVT::i32:
+ case MVT::i32:
case MVT::f32: SubregOffset = 4; break;
- case MVT::i64:
+ case MVT::i64:
case MVT::f64: SubregOffset = 0; break;
}
int FI = MFI->CreateFixedObject(8, ArgOffset);
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
- FIN = DAG.getNode(ISD::ADD, MVT::i64, FIN,
+ FIN = DAG.getNode(ISD::ADD, MVT::i64, FIN,
DAG.getConstant(SubregOffset, MVT::i64));
argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
}
-
+
// Every 4 bytes of argument space consumes one of the GPRs available for
// argument passing.
if (GPR_remaining > 0) {
++GPR_idx;
}
ArgOffset += 8;
-
+
DAG.setRoot(newroot.getValue(1));
ArgValues.push_back(argt);
}
for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i64, DAG.getRoot());
- SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
+ SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
Val, FIN);
MemOps.push_back(Store);
// Increment the address by eight for the next argument to store
DAG.getConstant(NumBytes, getPointerTy()));
} else {
NumBytes = 8 * Args.size(); // All arguments are rounded up to 8 bytes
-
- // Just to be safe, we'll always reserve the full 48 bytes of linkage area
+
+ // Just to be safe, we'll always reserve the full 48 bytes of linkage area
// plus 64 bytes of argument space in case any called code gets funky on us.
if (NumBytes < 112) NumBytes = 112;
// passing.
SDOperand StackPtr = DAG.getCopyFromReg(PPC::R1, MVT::i32,
DAG.getEntryNode());
-
+
// Figure out which arguments are going to go in registers, and which in
// memory. Also, if this is a vararg function, floating point operations
// must be stored to our stack, and loaded into integer regs as well, if
unsigned ArgOffset = 48;
unsigned GPR_remaining = 8;
unsigned FPR_remaining = 13;
-
+
std::vector<SDOperand> MemOps;
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
// PtrOff will be used to store the current argument to the stack if a
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
MVT::ValueType ArgVT = getValueType(Args[i].second);
-
+
switch (ArgVT) {
default: assert(0 && "Unexpected ValueType for argument!");
case MVT::i1:
if (!MemOps.empty())
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
}
-
+
std::vector<MVT::ValueType> RetVals;
MVT::ValueType RetTyVT = getValueType(RetTy);
if (RetTyVT != MVT::isVoid)
RetVals.push_back(RetTyVT);
RetVals.push_back(MVT::Other);
- SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
+ SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
Chain, Callee, args_to_use), 0);
Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
Chain = DAG.getNode(ISD::ADJCALLSTACKUP, MVT::Other, Chain,
}
return std::make_pair(Result, Chain);
}
-
+
std::pair<SDOperand, SDOperand> PPC64TargetLowering::
LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
/// SelectionDAG operations.
//===--------------------------------------------------------------------===//
class ISel : public SelectionDAGISel {
-
+
/// Comment Here.
PPC64TargetLowering PPC64Lowering;
-
+
/// ExprMap - As shared expressions are codegen'd, we keep track of which
/// vreg the value is produced in, so we only emit one copy of each compiled
/// tree.
unsigned GlobalBaseReg;
bool GlobalBaseInitialized;
-
+
public:
- ISel(TargetMachine &TM) : SelectionDAGISel(PPC64Lowering), PPC64Lowering(TM)
+ ISel(TargetMachine &TM) : SelectionDAGISel(PPC64Lowering), PPC64Lowering(TM)
{}
-
+
/// runOnFunction - Override this function in order to reset our per-function
/// variables.
virtual bool runOnFunction(Function &Fn) {
// Make sure we re-emit a set of the global base reg if necessary
GlobalBaseInitialized = false;
return SelectionDAGISel::runOnFunction(Fn);
- }
-
+ }
+
/// InstructionSelectBasicBlock - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
DEBUG(BB->dump());
// Codegen the basic block.
Select(DAG.getRoot());
-
+
// Clear state used for selection.
ExprMap.clear();
}
-
+
unsigned getGlobalBaseReg();
unsigned getConstDouble(double floatVal, unsigned Result);
unsigned SelectSetCR0(SDOperand CC);
unsigned SelectExpr(SDOperand N);
unsigned SelectExprFP(SDOperand N, unsigned Result);
void Select(SDOperand N);
-
+
bool SelectAddr(SDOperand N, unsigned& Reg, int& offset);
void SelectBranchCC(SDOperand N);
};
/// getImmediateForOpcode - This method returns a value indicating whether
/// the ConstantSDNode N can be used as an immediate to Opcode. The return
/// values are either 0, 1 or 2. 0 indicates that either N is not a
-/// ConstantSDNode, or is not suitable for use by that opcode. A return value
+/// ConstantSDNode, or is not suitable for use by that opcode. A return value
/// of 1 indicates that the constant may be used in normal immediate form. A
/// return value of 2 indicates that the constant may be used in shifted
/// immediate form. A return value of 3 indicates that log base 2 of the
if (N.getOpcode() != ISD::Constant) return 0;
int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
-
+
switch(Opcode) {
default: return 0;
case ISD::ADD:
return GlobalBaseReg;
}
-/// getConstDouble - Loads a floating point value into a register, via the
+/// getConstDouble - Loads a floating point value into a register, via the
/// Constant Pool. Optionally takes a register in which to load the value.
unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
unsigned Tmp1 = MakeReg(MVT::i64);
unsigned ISel::SelectSetCR0(SDOperand CC) {
unsigned Opc, Tmp1, Tmp2;
- static const unsigned CompareOpcodes[] =
+ static const unsigned CompareOpcodes[] =
{ PPC::FCMPU, PPC::FCMPU, PPC::CMPW, PPC::CMPLW };
-
+
// If the first operand to the select is a SETCC node, then we can fold it
// into the branch that selects which value to return.
SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val);
// Pass the optional argument U to getImmediateForOpcode for SETCC,
// so that it knows whether the SETCC immediate range is signed or not.
- if (1 == getImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC,
+ if (1 == getImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC,
Tmp2, U)) {
if (U)
BuildMI(BB, PPC::CMPLWI, 2, PPC::CR0).addReg(Tmp1).addImm(Tmp2);
if (1 == getImmediateForOpcode(N.getOperand(1), opcode, imm)) {
offset = imm;
return false;
- }
+ }
offset = SelectExpr(N.getOperand(1));
return true;
}
void ISel::SelectBranchCC(SDOperand N)
{
assert(N.getOpcode() == ISD::BRCOND && "Not a BranchCC???");
- MachineBasicBlock *Dest =
+ MachineBasicBlock *Dest =
cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
// Get the MBB we will fall through to so that we can hand it off to the
// branch selection pass as an argument to the PPC::COND_BRANCH pseudo op.
//ilist<MachineBasicBlock>::iterator It = BB;
//MachineBasicBlock *Fallthrough = ++It;
-
+
Select(N.getOperand(0)); //chain
unsigned Opc = SelectSetCR0(N.getOperand(1));
// FIXME: Use this once we have something approximating two-way branches
Tmp1 = SelectExpr(SetCC->getOperand(0)); // Val to compare against
unsigned TV = SelectExpr(N.getOperand(1)); // Use if TRUE
unsigned FV = SelectExpr(N.getOperand(2)); // Use if FALSE
-
+
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1));
if (CN && (CN->isExactlyValue(-0.0) || CN->isExactlyValue(0.0))) {
switch(SetCC->getCondition()) {
assert(0 && "Should never get here");
return 0;
}
-
+
unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
Opc = SelectSetCR0(N.getOperand(0));
- // Create an iterator with which to insert the MBB for copying the false
+ // Create an iterator with which to insert the MBB for copying the false
// value and the MBB to hold the PHI instruction for this SetCC.
MachineBasicBlock *thisMBB = BB;
const BasicBlock *LLVM_BB = BB->getBasicBlock();
}
case ISD::FNEG:
- if (!NoExcessFPPrecision &&
+ if (!NoExcessFPPrecision &&
ISD::ADD == N.getOperand(0).getOpcode() &&
N.getOperand(0).Val->hasOneUse() &&
ISD::MUL == N.getOperand(0).getOperand(0).getOpcode() &&
Tmp3 = SelectExpr(N.getOperand(0).getOperand(1));
Opc = DestType == MVT::f64 ? PPC::FNMADD : PPC::FNMADDS;
BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
- } else if (!NoExcessFPPrecision &&
+ } else if (!NoExcessFPPrecision &&
ISD::SUB == N.getOperand(0).getOpcode() &&
N.getOperand(0).Val->hasOneUse() &&
ISD::MUL == N.getOperand(0).getOperand(0).getOpcode() &&
BuildMI(BB, PPC::FNEG, 1, Result).addReg(Tmp1);
}
return Result;
-
+
case ISD::FABS:
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, PPC::FABS, 1, Result).addReg(Tmp1);
return Result;
case ISD::FP_ROUND:
- assert (DestType == MVT::f32 &&
- N.getOperand(0).getValueType() == MVT::f64 &&
+ assert (DestType == MVT::f32 &&
+ N.getOperand(0).getValueType() == MVT::f64 &&
"only f64 to f32 conversion supported here");
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, PPC::FRSP, 1, Result).addReg(Tmp1);
return Result;
case ISD::FP_EXTEND:
- assert (DestType == MVT::f64 &&
- N.getOperand(0).getValueType() == MVT::f32 &&
+ assert (DestType == MVT::f64 &&
+ N.getOperand(0).getValueType() == MVT::f32 &&
"only f32 to f64 conversion supported here");
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
return Result;
-
+
case ISD::ConstantFP: {
ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
Result = getConstDouble(CN->getValue(), Result);
return Result;
}
-
+
case ISD::ADD:
if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::MUL &&
N.getOperand(0).Val->hasOneUse()) {
Tmp2 = MakeReg(MVT::f64); // temp reg to load the integer value into
Tmp3 = MakeReg(MVT::i64); // temp reg to hold the conversion constant
unsigned ConstF = MakeReg(MVT::f64); // temp reg to hold the fp constant
-
+
int FrameIdx = BB->getParent()->getFrameInfo()->CreateStackObject(8, 8);
MachineConstantPool *CP = BB->getParent()->getConstantPool();
-
+
// FIXME: pull this FP constant generation stuff out into something like
// the simple ISel's getReg.
if (IsUnsigned) {
if (ISD::CopyFromReg == opcode)
DestType = N.getValue(0).getValueType();
-
+
if (DestType == MVT::f64 || DestType == MVT::f32)
if (ISD::LOAD != opcode && ISD::EXTLOAD != opcode && ISD::UNDEF != opcode)
return SelectExprFP(N, Result);
Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
addFrameReference(BuildMI(BB, PPC::ADDI, 2, Result), (int)Tmp1, 0, false);
return Result;
-
+
case ISD::GlobalAddress: {
GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
Tmp1 = MakeReg(MVT::i64);
MVT::ValueType TypeBeingLoaded = (ISD::LOAD == opcode) ?
Node->getValueType(0) : cast<MVTSDNode>(Node)->getExtraValueType();
bool sext = (ISD::SEXTLOAD == opcode);
-
+
// Make sure we generate both values.
if (Result != 1)
ExprMap[N.getValue(1)] = 1; // Generate the token
case MVT::f32: Opc = PPC::LFS; break;
case MVT::f64: Opc = PPC::LFD; break;
}
-
+
if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
Tmp1 = MakeReg(MVT::i64);
int CPI = CP->getIndex();
}
return Result;
}
-
+
case ISD::CALL: {
unsigned GPR_idx = 0, FPR_idx = 0;
- static const unsigned GPR[] = {
+ static const unsigned GPR[] = {
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
PPC::R7, PPC::R8, PPC::R9, PPC::R10,
};
MachineInstr *CallMI;
// Emit the correct call instruction based on the type of symbol called.
- if (GlobalAddressSDNode *GASD =
+ if (GlobalAddressSDNode *GASD =
dyn_cast<GlobalAddressSDNode>(N.getOperand(1))) {
- CallMI = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(GASD->getGlobal(),
+ CallMI = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(GASD->getGlobal(),
true);
- } else if (ExternalSymbolSDNode *ESSDN =
+ } else if (ExternalSymbolSDNode *ESSDN =
dyn_cast<ExternalSymbolSDNode>(N.getOperand(1))) {
- CallMI = BuildMI(PPC::CALLpcrel, 1).addExternalSymbol(ESSDN->getSymbol(),
+ CallMI = BuildMI(PPC::CALLpcrel, 1).addExternalSymbol(ESSDN->getSymbol(),
true);
} else {
Tmp1 = SelectExpr(N.getOperand(1));
CallMI = BuildMI(PPC::CALLindirect, 3).addImm(20).addImm(0)
.addReg(PPC::R12);
}
-
+
// Load the register args to virtual regs
std::vector<unsigned> ArgVR;
for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
break;
}
}
-
+
// Put the call instruction in the correct place in the MachineBasicBlock
BB->push_back(CallMI);
switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
default: Node->dump(); assert(0 && "Unhandled SIGN_EXTEND type"); break;
case MVT::i32:
- BuildMI(BB, PPC::EXTSW, 1, Result).addReg(Tmp1);
+ BuildMI(BB, PPC::EXTSW, 1, Result).addReg(Tmp1);
break;
case MVT::i16:
- BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1);
+ BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1);
break;
case MVT::i8:
- BuildMI(BB, PPC::EXTSB, 1, Result).addReg(Tmp1);
+ BuildMI(BB, PPC::EXTSB, 1, Result).addReg(Tmp1);
break;
case MVT::i1:
BuildMI(BB, PPC::SUBFIC, 2, Result).addReg(Tmp1).addSImm(0);
break;
}
return Result;
-
+
case ISD::CopyFromReg:
if (Result == 1)
Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
BuildMI(BB, PPC::SLD, 2, Result).addReg(Tmp1).addReg(Tmp2);
}
return Result;
-
+
case ISD::SRL:
Tmp1 = SelectExpr(N.getOperand(0));
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
BuildMI(BB, PPC::SRD, 2, Result).addReg(Tmp1).addReg(Tmp2);
}
return Result;
-
+
case ISD::SRA:
Tmp1 = SelectExpr(N.getOperand(0));
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
BuildMI(BB, PPC::SRAD, 2, Result).addReg(Tmp1).addReg(Tmp2);
}
return Result;
-
+
case ISD::ADD:
Tmp1 = SelectExpr(N.getOperand(0));
switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
BuildMI(BB, PPC::SUBF, 2, Result).addReg(Tmp2).addReg(Tmp1);
}
return Result;
-
+
case ISD::MUL:
Tmp1 = SelectExpr(N.getOperand(0));
if (1 == getImmediateForOpcode(N.getOperand(1), opcode, Tmp2))
addFrameReference(BuildMI(BB, PPC::LD, 2, Result), FrameIdx);
return Result;
}
-
+
case ISD::SETCC:
if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node)) {
Opc = SelectSetCR0(N);
-
+
unsigned TrueValue = MakeReg(MVT::i32);
BuildMI(BB, PPC::LI, 1, TrueValue).addSImm(1);
unsigned FalseValue = MakeReg(MVT::i32);
BuildMI(BB, PPC::LI, 1, FalseValue).addSImm(0);
- // Create an iterator with which to insert the MBB for copying the false
+ // Create an iterator with which to insert the MBB for copying the false
// value and the MBB to hold the PHI instruction for this SetCC.
MachineBasicBlock *thisMBB = BB;
const BasicBlock *LLVM_BB = BB->getBasicBlock();
ilist<MachineBasicBlock>::iterator It = BB;
++It;
-
+
// thisMBB:
// ...
// cmpTY cr0, r1, r2
}
assert(0 && "Is this legal?");
return 0;
-
+
case ISD::SELECT: {
unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
Opc = SelectSetCR0(N.getOperand(0));
- // Create an iterator with which to insert the MBB for copying the false
+ // Create an iterator with which to insert the MBB for copying the false
// value and the MBB to hold the PHI instruction for this SetCC.
MachineBasicBlock *thisMBB = BB;
const BasicBlock *LLVM_BB = BB->getBasicBlock();
return; // Already selected.
SDNode *Node = N.Val;
-
+
switch (Node->getOpcode()) {
default:
Node->dump(); std::cerr << "\n";
BuildMI(BB, PPC::B, 1).addMBB(Dest);
return;
}
- case ISD::BRCOND:
+ case ISD::BRCOND:
SelectBranchCC(N);
return;
case ISD::CopyToReg:
Select(N.getOperand(0));
Tmp1 = SelectExpr(N.getOperand(1));
Tmp2 = cast<RegSDNode>(N)->getReg();
-
+
if (Tmp1 != Tmp2) {
- if (N.getOperand(1).getValueType() == MVT::f64 ||
+ if (N.getOperand(1).getValueType() == MVT::f64 ||
N.getOperand(1).getValueType() == MVT::f32)
BuildMI(BB, PPC::FMR, 1, Tmp2).addReg(Tmp1);
else
}
BuildMI(BB, PPC::BLR, 0); // Just emit a 'ret' instruction
return;
- case ISD::TRUNCSTORE:
- case ISD::STORE:
+ case ISD::TRUNCSTORE:
+ case ISD::STORE:
{
SDOperand Chain = N.getOperand(0);
SDOperand Value = N.getOperand(1);
{
int offset;
bool idx = SelectAddr(Address, Tmp2, offset);
- if (idx) {
+ if (idx) {
Opc = IndexedOpForOp(Opc);
BuildMI(BB, Opc, 3).addReg(Tmp1).addReg(Tmp2).addReg(offset);
} else {
/// description file.
///
FunctionPass *llvm::createPPC64ISelPattern(TargetMachine &TM) {
- return new ISel(TM);
+ return new ISel(TM);
}
//===- PPC64InstrInfo.cpp - PowerPC64 Instruction Information ---*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the PowerPC implementation of the TargetInstrInfo class.
//===- PPC64InstrInfo.h - PowerPC64 Instruction Information -----*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the PowerPC64 implementation of the TargetInstrInfo class.
case PPC::BGE: return PPC::BLT;
case PPC::BGT: return PPC::BLE;
case PPC::BLE: return PPC::BGT;
- }
+ }
}
};
//===- PPC64JITInfo.h - PowerPC/AIX impl. of the JIT interface -*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the PowerPC/AIX implementation of the TargetJITInfo class.
//===- PPC64RegisterInfo.cpp - PowerPC64 Register Information ---*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the PowerPC64 implementation of the MRegisterInfo class.
PPC64RegisterInfo::PPC64RegisterInfo()
: PPC64GenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
- ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
+ ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
case 1: return 0;
case 2: return 1;
case 4: return 2;
- case 8: return 3;
+ case 8: return 3;
}
} else if (RC == PPC64::FPRCRegisterClass) {
switch (RC->getSize()) {
abort();
}
-void
+void
PPC64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, int FrameIdx) const {
- static const unsigned Opcode[] = {
- PPC::STB, PPC::STH, PPC::STW, PPC::STD, PPC::STFS, PPC::STFD
+ static const unsigned Opcode[] = {
+ PPC::STB, PPC::STH, PPC::STW, PPC::STD, PPC::STFS, PPC::STFD
};
unsigned OC = Opcode[getIdx(getClass(SrcReg))];
if (SrcReg == PPC::LR) {
PPC64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIdx) const{
- static const unsigned Opcode[] = {
- PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LD, PPC::LFS, PPC::LFD
+ static const unsigned Opcode[] = {
+ PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LD, PPC::LFS, PPC::LFD
};
unsigned OC = Opcode[getIdx(getClass(DestReg))];
if (DestReg == PPC::LR) {
BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
} else if (RC == PPC64::FPRCRegisterClass) {
BuildMI(MBB, MI, PPC::FMR, 1, DestReg).addReg(SrcReg);
- } else {
+ } else {
std::cerr << "Attempt to copy register that is not GPR or FPR";
abort();
}
// alignment boundary.
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
Amount = (Amount+Align-1)/Align*Align;
-
+
// Replace the pseudo instruction with a new instruction...
if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
-
+
while (!MI.getOperand(i).isFrameIndex()) {
++i;
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
// SP before having the stack size subtracted from it, then add the stack size
// to Offset to get the correct offset.
Offset += MF.getFrameInfo()->getStackSize();
-
+
if (Offset > 32767 || Offset < -32768) {
// Insert a set of r0 with the full offset value before the ld, st, or add
MachineBasicBlock *MBB = MI.getParent();
// convert into indexed form of the instruction
// sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
// addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
- unsigned NewOpcode =
+ unsigned NewOpcode =
const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
assert(NewOpcode && "No indexed form of load or store available!");
MI.setOpcode(NewOpcode);
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
MachineInstr *MI;
-
+
// Get the number of bytes to allocate from the FrameInfo
unsigned NumBytes = MFI->getStackSize();
// If we have calls, we cannot use the red zone to store callee save registers
// and we must set up a stack frame, so calculate the necessary size here.
if (MFI->hasCalls()) {
- // We reserve argument space for call sites in the function immediately on
- // entry to the current function. This eliminates the need for add/sub
+ // We reserve argument space for call sites in the function immediately on
+ // entry to the current function. This eliminates the need for add/sub
// brackets around call sites.
NumBytes += MFI->getMaxCallFrameSize();
}
// Do we need to allocate space on the stack?
if (NumBytes == 0) return;
- // Add the size of R1 to NumBytes size for the store of R1 to the bottom
+ // Add the size of R1 to NumBytes size for the store of R1 to the bottom
// of the stack and round the size to a multiple of the alignment.
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
unsigned GPRSize = getSpillSize(PPC::R1)/8;
MI = BuildMI(PPC::STDUX, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
MBB.insert(MBBI, MI);
}
-
+
if (hasFP(MF)) {
MI = BuildMI(PPC::STD, 3).addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
MBB.insert(MBBI, MI);
MachineInstr *MI;
assert(MBBI->getOpcode() == PPC::BLR &&
"Can only insert epilog into returning blocks");
-
+
// Get the number of bytes allocated from the FrameInfo...
unsigned NumBytes = MFI->getStackSize();
case Type::PointerTyID:
case Type::LongTyID:
case Type::ULongTyID: return &GPRCInstance;
-
+
case Type::FloatTyID:
case Type::DoubleTyID: return &FPRCInstance;
}
//===- PPC64RegisterInfo.h - PowerPC64 Register Information Impl -*- C++ -*-==//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the PowerPC implementation of the MRegisterInfo class.
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex) const;
-
+
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
//===-- PPC64TargetMachine.h - Define TargetMachine for PowerPC64 -*- C++ -*-=//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file declares the PowerPC specific subclass of TargetMachine.
//
//===----------------------------------------------------------------------===//
//===-- PowerPCAsmPrinter.cpp - Print machine instrs to PowerPC assembly --===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains a printer that converts from our internal representation
struct PowerPCAsmPrinter : public AsmPrinter {
std::set<std::string> FnStubs, GVStubs, LinkOnceStubs;
std::set<std::string> Strings;
-
+
PowerPCAsmPrinter(std::ostream &O, TargetMachine &TM)
: AsmPrinter(O, TM), LabelNumber(0) {}
/// Unique incrementer for label values for referencing Global values.
///
unsigned LabelNumber;
-
+
virtual const char *getPassName() const {
return "PowerPC Assembly Printer";
}
if (MI->getOperand(OpNo).isImmediate()) {
O << "$+" << MI->getOperand(OpNo).getImmedValue();
} else {
- printOp(MI->getOperand(OpNo),
+ printOp(MI->getOperand(OpNo),
TM.getInstrInfo()->isCall(MI->getOpcode()));
}
}
}
O << 4 * RegNo + value;
}
-
+
virtual void printConstantPool(MachineConstantPool *MCP) = 0;
- virtual bool runOnMachineFunction(MachineFunction &F) = 0;
+ virtual bool runOnMachineFunction(MachineFunction &F) = 0;
virtual bool doFinalization(Module &M) = 0;
};
-
+
/// DarwinAsmPrinter - PowerPC assembly printer, customized for Darwin/Mac OS
/// X
///
}
void printConstantPool(MachineConstantPool *MCP);
- bool runOnMachineFunction(MachineFunction &F);
+ bool runOnMachineFunction(MachineFunction &F);
bool doFinalization(Module &M);
};
-
+
/// AIXAsmPrinter - PowerPC assembly printer, customized for AIX
///
struct AIXAsmPrinter : public PowerPCAsmPrinter {
Data64bitsDirective = 0; // we can't emit a 64-bit unit
AlignmentIsInBytes = false; // Alignment is by power of 2.
}
-
+
virtual const char *getPassName() const {
return "AIX PPC Assembly Printer";
}
void printConstantPool(MachineConstantPool *MCP);
- bool runOnMachineFunction(MachineFunction &F);
+ bool runOnMachineFunction(MachineFunction &F);
bool doInitialization(Module &M);
bool doFinalization(Module &M);
};
/// SwitchStringSection - manage the changes required to output bytes as
/// characters in a string vs. numeric decimal values
-///
+///
static inline void SwitchStringSection(std::ostream &O, StringSection NewSect,
StringSection &Current) {
if (Current == None) {
} else if (Current == Alpha) {
if (NewSect == None)
O << "\"";
- else if (NewSect == Numeric)
+ else if (NewSect == Numeric)
O << "\"\n"
<< "\t.byte ";
} else if (Current == Numeric) {
O << '\n';
}
-/// createDarwinAsmPrinterPass - Returns a pass that prints the PPC assembly
-/// code for a MachineFunction to the given output stream, in a format that the
+/// createDarwinAsmPrinterPass - Returns a pass that prints the PPC assembly
+/// code for a MachineFunction to the given output stream, in a format that the
/// Darwin assembler can deal with.
///
FunctionPass *llvm::createDarwinAsmPrinter(std::ostream &o, TargetMachine &tm) {
}
/// createAIXAsmPrinterPass - Returns a pass that prints the PPC assembly code
-/// for a MachineFunction to the given output stream, in a format that the
+/// for a MachineFunction to the given output stream, in a format that the
/// AIX 5L assembler can deal with.
///
FunctionPass *llvm::createAIXAsmPrinter(std::ostream &o, TargetMachine &tm) {
void PowerPCAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
const MRegisterInfo &RI = *TM.getRegisterInfo();
int new_symbol;
-
+
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
if (Value *V = MO.getVRegValueOrNull()) {
std::cerr << "Shouldn't use addPCDisp() when building PPC MachineInstrs";
abort();
return;
-
+
case MachineOperand::MO_MachineBasicBlock: {
MachineBasicBlock *MBBOp = MO.getMachineBasicBlock();
O << ".LBB" << Mang->getValueName(MBBOp->getParent()->getFunction())
O << "L" << Name << "$stub";
return;
}
-
+
// External or weakly linked global variables need non-lazily-resolved stubs
if ((GV->isExternal() || GV->hasWeakLinkage() || GV->hasLinkOnceLinkage())){
if (GV->hasLinkOnceLinkage())
O << Mang->getValueName(GV);
return;
}
-
+
default:
O << "<unknown operand type: " << MO.getType() << ">";
return;
SH = 32-SH;
}
if (FoundMnemonic) {
- printOperand(MI, 0, MVT::i64);
- O << ", ";
- printOperand(MI, 1, MVT::i64);
+ printOperand(MI, 0, MVT::i64);
+ O << ", ";
+ printOperand(MI, 1, MVT::i64);
O << ", " << (unsigned int)SH << "\n";
return;
}
}
-
+
if (printInstruction(MI))
return; // Printer was automatically generated
-
+
assert(0 && "Unhandled instruction in asm writer!");
abort();
return;
void DarwinAsmPrinter::printConstantPool(MachineConstantPool *MCP) {
const std::vector<Constant*> &CP = MCP->getConstants();
const TargetData &TD = TM.getTargetData();
-
+
if (CP.empty()) return;
for (unsigned i = 0, e = CP.size(); i != e; ++i) {
unsigned Align = TD.getTypeAlignmentShift(C->getType());
if (C->isNullValue() && /* FIXME: Verify correct */
- (I->hasInternalLinkage() || I->hasWeakLinkage() ||
+ (I->hasInternalLinkage() || I->hasWeakLinkage() ||
I->hasLinkOnceLinkage())) {
SwitchSection(O, CurSection, ".data");
if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
if (I->hasInternalLinkage())
O << ".lcomm " << name << "," << Size << "," << Align;
- else
+ else
O << ".comm " << name << "," << Size;
O << "\t\t; ";
WriteAsOperand(O, I, true, true, &M);
<< ".private_extern " << name << '\n'
<< ".section __DATA,__datacoal_nt,coalesced,no_toc\n";
LinkOnceStubs.insert(name);
- break;
+ break;
case GlobalValue::WeakLinkage: // FIXME: Verify correct for weak.
// Nonnull linkonce -> weak
O << "\t.weak " << name << "\n";
}
// Output stubs for dynamically-linked functions
- for (std::set<std::string>::iterator i = FnStubs.begin(), e = FnStubs.end();
+ for (std::set<std::string>::iterator i = FnStubs.begin(), e = FnStubs.end();
i != e; ++i)
{
O << ".data\n";
// Output stubs for external global variables
if (GVStubs.begin() != GVStubs.end())
O << ".data\n.non_lazy_symbol_pointer\n";
- for (std::set<std::string>::iterator i = GVStubs.begin(), e = GVStubs.end();
+ for (std::set<std::string>::iterator i = GVStubs.begin(), e = GVStubs.end();
i != e; ++i) {
O << "L" << *i << "$non_lazy_ptr:\n";
O << "\t.indirect_symbol " << *i << "\n";
O << "\t.long\t0\n";
}
-
+
// Output stubs for link-once variables
if (LinkOnceStubs.begin() != LinkOnceStubs.end())
O << ".data\n.align 2\n";
- for (std::set<std::string>::iterator i = LinkOnceStubs.begin(),
+ for (std::set<std::string>::iterator i = LinkOnceStubs.begin(),
e = LinkOnceStubs.end(); i != e; ++i) {
O << "L" << *i << "$non_lazy_ptr:\n"
<< "\t.long\t" << *i << '\n';
}
-
+
AsmPrinter::doFinalization(M);
return false; // success
}
void AIXAsmPrinter::printConstantPool(MachineConstantPool *MCP) {
const std::vector<Constant*> &CP = MCP->getConstants();
const TargetData &TD = TM.getTargetData();
-
+
if (CP.empty()) return;
for (unsigned i = 0, e = CP.size(); i != e; ++i) {
const TargetData &TD = TM.getTargetData();
std::string CurSection;
- O << "\t.machine \"ppc64\"\n"
+ O << "\t.machine \"ppc64\"\n"
<< "\t.toc\n"
<< "\t.csect .text[PR]\n";
for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); I != E; ++I) {
if (!I->hasInitializer())
continue;
-
+
std::string Name = I->getName();
Constant *C = I->getInitializer();
// N.B.: We are defaulting to writable strings
- if (I->hasExternalLinkage()) {
+ if (I->hasExternalLinkage()) {
O << "\t.globl " << Name << '\n'
<< "\t.csect .data[RW],3\n";
} else {
//===-- PowerPCBranchSelector.cpp - Emit long conditional branches-*- C++ -*-=//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by Nate Baegeman and is distributed under the
// University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
-// This file contains a pass that scans a machine function to determine which
+// This file contains a pass that scans a machine function to determine which
// conditional branches need more than 16 bits of displacement to reach their
// target basic block. It does this in two passes; a calculation of basic block
// positions pass, and a branch psuedo op to machine branch opcode pass. This
// OffsetMap - Mapping between BB and byte offset from start of function
std::map<MachineBasicBlock*, unsigned> OffsetMap;
- /// bytesForOpcode - A convenience function for totalling up the number of
+ /// bytesForOpcode - A convenience function for totalling up the number of
/// bytes in a basic block.
///
static unsigned bytesForOpcode(unsigned opcode) {
switch (opcode) {
case PPC::COND_BRANCH:
// while this will be 4 most of the time, if we emit 12 it is just a
- // minor pessimization that saves us from having to worry about
+ // minor pessimization that saves us from having to worry about
// keeping the offsets up to date later when we emit long branch glue.
return 12;
case PPC::IMPLICIT_DEF: // no asm emitted
return 0;
break;
- default:
+ default:
return 4; // PowerPC instructions are all 4 bytes
break;
}
}
-
+
virtual bool runOnMachineFunction(MachineFunction &Fn) {
// Running total of instructions encountered since beginning of function
unsigned ByteCount = 0;
// For each MBB, add its offset to the offset map, and count up its
// instructions
- for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
+ for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
++MFI) {
MachineBasicBlock *MBB = MFI;
OffsetMap[MBB] = ByteCount;
// b .L_TARGET_MBB
// b .L_FALLTHROUGH_MBB
- for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
+ for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
++MFI) {
MachineBasicBlock *MBB = MFI;
-
+
for (MachineBasicBlock::iterator MBBI = MBB->begin(), EE = MBB->end();
MBBI != EE; ++MBBI) {
if (MBBI->getOpcode() == PPC::COND_BRANCH) {
// 1. bc opcode
// 2. target MBB
// 3. fallthrough MBB
- MachineBasicBlock *trueMBB =
+ MachineBasicBlock *trueMBB =
MBBI->getOperand(2).getMachineBasicBlock();
- MachineBasicBlock *falseMBB =
+ MachineBasicBlock *falseMBB =
MBBI->getOperand(3).getMachineBasicBlock();
-
+
int Displacement = OffsetMap[trueMBB] - ByteCount;
unsigned Opcode = MBBI->getOperand(1).getImmedValue();
unsigned Inverted = PPC32InstrInfo::invertPPCBranchOpcode(Opcode);
//===-- PPC32CodeEmitter.cpp - JIT Code Emitter for PowerPC32 -----*- C++ -*-=//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file defines the PowerPC 32-bit CodeEmitter and associated machinery to
// JIT-compile bytecode to native PowerPC.
//
int getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
public:
- PPC32CodeEmitter(TargetMachine &T, MachineCodeEmitter &M)
+ PPC32CodeEmitter(TargetMachine &T, MachineCodeEmitter &M)
: TM(T), MCE(M) {}
const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
/// emitWord - write a 32-bit word to memory at the current PC
///
void emitWord(unsigned w) { MCE.emitWord(w); }
-
+
/// getValueBit - return the particular bit of Val
///
unsigned getValueBit(int64_t Val, unsigned bit) { return (Val >> bit) & 1; }
bool PPC32TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
MachineCodeEmitter &MCE) {
// Machine code emitter pass for PowerPC
- PM.add(new PPC32CodeEmitter(*this, MCE));
+ PM.add(new PPC32CodeEmitter(*this, MCE));
// Delete machine code for this function after emitting it
PM.add(createMachineCodeDeleter());
return false;
<< "\n");
unsigned Instr = *Ref;
intptr_t BranchTargetDisp = (Location - (intptr_t)Ref) >> 2;
-
+
switch (Instr >> 26) {
default: assert(0 && "Unknown branch user!");
case 18: // This is B or BL
static unsigned enumRegToMachineReg(unsigned enumReg) {
switch (enumReg) {
- case PPC::R0 : case PPC::F0 : case PPC::CR0: return 0;
- case PPC::R1 : case PPC::F1 : case PPC::CR1: return 1;
+ case PPC::R0 : case PPC::F0 : case PPC::CR0: return 0;
+ case PPC::R1 : case PPC::F1 : case PPC::CR1: return 1;
case PPC::R2 : case PPC::F2 : case PPC::CR2: return 2;
- case PPC::R3 : case PPC::F3 : case PPC::CR3: return 3;
- case PPC::R4 : case PPC::F4 : case PPC::CR4: return 4;
+ case PPC::R3 : case PPC::F3 : case PPC::CR3: return 3;
+ case PPC::R4 : case PPC::F4 : case PPC::CR4: return 4;
case PPC::R5 : case PPC::F5 : case PPC::CR5: return 5;
- case PPC::R6 : case PPC::F6 : case PPC::CR6: return 6;
- case PPC::R7 : case PPC::F7 : case PPC::CR7: return 7;
+ case PPC::R6 : case PPC::F6 : case PPC::CR6: return 6;
+ case PPC::R7 : case PPC::F7 : case PPC::CR7: return 7;
case PPC::R8 : case PPC::F8 : return 8;
- case PPC::R9 : case PPC::F9 : return 9;
- case PPC::R10: case PPC::F10: return 10;
+ case PPC::R9 : case PPC::F9 : return 9;
+ case PPC::R10: case PPC::F10: return 10;
case PPC::R11: case PPC::F11: return 11;
- case PPC::R12: case PPC::F12: return 12;
- case PPC::R13: case PPC::F13: return 13;
+ case PPC::R12: case PPC::F12: return 12;
+ case PPC::R13: case PPC::F13: return 13;
case PPC::R14: case PPC::F14: return 14;
- case PPC::R15: case PPC::F15: return 15;
- case PPC::R16: case PPC::F16: return 16;
+ case PPC::R15: case PPC::F15: return 15;
+ case PPC::R16: case PPC::F16: return 16;
case PPC::R17: case PPC::F17: return 17;
- case PPC::R18: case PPC::F18: return 18;
- case PPC::R19: case PPC::F19: return 19;
+ case PPC::R18: case PPC::F18: return 18;
+ case PPC::R19: case PPC::F19: return 19;
case PPC::R20: case PPC::F20: return 20;
case PPC::R21: case PPC::F21: return 21;
- case PPC::R22: case PPC::F22: return 22;
- case PPC::R23: case PPC::F23: return 23;
+ case PPC::R22: case PPC::F22: return 22;
+ case PPC::R23: case PPC::F23: return 23;
case PPC::R24: case PPC::F24: return 24;
- case PPC::R25: case PPC::F25: return 25;
- case PPC::R26: case PPC::F26: return 26;
+ case PPC::R25: case PPC::F25: return 25;
+ case PPC::R26: case PPC::F26: return 26;
case PPC::R27: case PPC::F27: return 27;
- case PPC::R28: case PPC::F28: return 28;
- case PPC::R29: case PPC::F29: return 29;
+ case PPC::R28: case PPC::F28: return 28;
+ case PPC::R29: case PPC::F29: return 29;
case PPC::R30: case PPC::F30: return 30;
case PPC::R31: case PPC::F31: return 31;
default:
}
int PPC32CodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
-
+
int rv = 0; // Return value; defaults to 0 for unhandled cases
// or things that get fixed up later by the JIT.
if (MO.isRegister()) {
//===-- PowerPCFrameInfo.h - Define TargetFrameInfo for PowerPC -*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
//
class PowerPCFrameInfo: public TargetFrameInfo {
const TargetMachine &TM;
std::pair<unsigned, int> LR[1];
-
+
public:
PowerPCFrameInfo(const TargetMachine &tm, bool LP64)
: TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0), TM(tm) {
//
// This file was developed by Nate Begeman and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file defines a pattern matching instruction selector for 32 bit PowerPC.
addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
-
+
// PowerPC has no intrinsics for these particular operations
setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
setOperationAction(ISD::MEMSET, MVT::Other, Expand);
// PowerPC has an i16 but no i8 (or i1) SEXTLOAD
setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
-
+
// PowerPC has no SREM/UREM instructions
setOperationAction(ISD::SREM, MVT::i32, Expand);
setOperationAction(ISD::UREM, MVT::i32, Expand);
setSetCCResultContents(ZeroOrOneSetCCResult);
addLegalFPImmediate(+0.0); // Necessary for FSEL
- addLegalFPImmediate(-0.0); //
+ addLegalFPImmediate(-0.0); //
computeRegisterProperties();
}
/// lower the arguments for the specified function, into the specified DAG.
virtual std::vector<SDOperand>
LowerArguments(Function &F, SelectionDAG &DAG);
-
+
/// LowerCallTo - This hook lowers an abstract call to a function into an
/// actual call.
virtual std::pair<SDOperand, SDOperand>
LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
-
+
virtual std::pair<SDOperand, SDOperand>
LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
-
+
virtual std::pair<SDOperand,SDOperand>
LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
const Type *ArgTy, SelectionDAG &DAG);
MachineFrameInfo *MFI = MF.getFrameInfo();
MachineBasicBlock& BB = MF.front();
std::vector<SDOperand> ArgValues;
-
- // Due to the rather complicated nature of the PowerPC ABI, rather than a
+
+ // Due to the rather complicated nature of the PowerPC ABI, rather than a
// fixed size array of physical args, for the sake of simplicity let the STL
// handle tracking them for us.
std::vector<unsigned> argVR, argPR, argOp;
unsigned GPR_remaining = 8;
unsigned FPR_remaining = 13;
unsigned GPR_idx = 0, FPR_idx = 0;
- static const unsigned GPR[] = {
+ static const unsigned GPR[] = {
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
PPC::R7, PPC::R8, PPC::R9, PPC::R10,
};
bool needsLoad = false;
bool ArgLive = !I->use_empty();
MVT::ValueType ObjectVT = getValueType(I->getType());
-
+
switch (ObjectVT) {
default: assert(0 && "Unhandled argument type!");
case MVT::i1:
case MVT::i8:
case MVT::i16:
- case MVT::i32:
+ case MVT::i32:
ObjSize = 4;
if (!ArgLive) break;
if (GPR_remaining > 0) {
argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
newroot = argLo;
} else {
- needsLoad = true;
+ needsLoad = true;
}
break;
case MVT::f32:
if (!ArgLive) break;
if (FPR_remaining > 0) {
MF.addLiveIn(FPR[FPR_idx]);
- argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
+ argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
DAG.getRoot());
--FPR_remaining;
++FPR_idx;
}
break;
}
-
+
// We need to load the argument to a virtual register if we determined above
- // that we ran out of physical registers of the appropriate type
+ // that we ran out of physical registers of the appropriate type
if (needsLoad) {
unsigned SubregOffset = 0;
if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
if (ObjectVT == MVT::i16) SubregOffset = 2;
int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
- FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
+ FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
DAG.getConstant(SubregOffset, MVT::i32));
argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
}
-
+
// Every 4 bytes of argument space consumes one of the GPRs available for
// argument passing.
if (GPR_remaining > 0) {
ArgOffset += ObjSize;
if (newroot.Val)
DAG.setRoot(newroot.getValue(1));
-
+
ArgValues.push_back(argt);
}
for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
MF.addLiveIn(GPR[GPR_idx]);
SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
- SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
+ SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
Val, FIN);
MemOps.push_back(Store);
// Increment the address by four for the next argument to store
NumBytes += 8;
break;
}
-
- // Just to be safe, we'll always reserve the full 24 bytes of linkage area
+
+ // Just to be safe, we'll always reserve the full 24 bytes of linkage area
// plus 32 bytes of argument space in case any called code gets funky on us.
if (NumBytes < 56) NumBytes = 56;
// passing.
SDOperand StackPtr = DAG.getCopyFromReg(PPC::R1, MVT::i32,
DAG.getEntryNode());
-
+
// Figure out which arguments are going to go in registers, and which in
// memory. Also, if this is a vararg function, floating point operations
// must be stored to our stack, and loaded into integer regs as well, if
unsigned ArgOffset = 24;
unsigned GPR_remaining = 8;
unsigned FPR_remaining = 13;
-
+
std::vector<SDOperand> MemOps;
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
// PtrOff will be used to store the current argument to the stack if a
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
MVT::ValueType ArgVT = getValueType(Args[i].second);
-
+
switch (ArgVT) {
default: assert(0 && "Unexpected ValueType for argument!");
case MVT::i1:
// in it, and store the other half to the stack. If we have two or more
// free GPRs, then we can pass both halves of the i64 in registers.
if (GPR_remaining > 0) {
- SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
+ SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
Args[i].first, DAG.getConstant(1, MVT::i32));
- SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
+ SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
Args[i].first, DAG.getConstant(0, MVT::i32));
args_to_use.push_back(Hi);
--GPR_remaining;
if (!MemOps.empty())
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
}
-
+
std::vector<MVT::ValueType> RetVals;
MVT::ValueType RetTyVT = getValueType(RetTy);
if (RetTyVT != MVT::isVoid)
RetVals.push_back(RetTyVT);
RetVals.push_back(MVT::Other);
- SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
+ SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
Chain, Callee, args_to_use), 0);
Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
Chain = DAG.getNode(ISD::ADJCALLSTACKUP, MVT::Other, Chain,
}
return std::make_pair(Result, Chain);
}
-
+
std::pair<SDOperand, SDOperand> PPC32TargetLowering::
LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
SelectionDAG *ISelDAG; // Hack to support us having a dag->dag transform
// for sdiv and udiv until it is put into the future
// dag combiner.
-
+
/// ExprMap - As shared expressions are codegen'd, we keep track of which
/// vreg the value is produced in, so we only emit one copy of each compiled
/// tree.
public:
ISel(TargetMachine &TM) : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM),
ISelDAG(0) {}
-
+
/// runOnFunction - Override this function in order to reset our per-function
/// variables.
virtual bool runOnFunction(Function &Fn) {
// Make sure we re-emit a set of the global base reg if necessary
GlobalBaseInitialized = false;
return SelectionDAGISel::runOnFunction(Fn);
- }
-
+ }
+
/// InstructionSelectBasicBlock - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
// Codegen the basic block.
ISelDAG = &DAG;
Select(DAG.getRoot());
-
+
// Clear state used for selection.
ExprMap.clear();
ISelDAG = 0;
// dag -> dag expanders for integer divide by constant
SDOperand BuildSDIVSequence(SDOperand N);
SDOperand BuildUDIVSequence(SDOperand N);
-
+
unsigned getGlobalBaseReg();
unsigned getConstDouble(double floatVal, unsigned Result);
void MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result);
unsigned SelectExpr(SDOperand N, bool Recording=false);
unsigned SelectExprFP(SDOperand N, unsigned Result);
void Select(SDOperand N);
-
+
bool SelectAddr(SDOperand N, unsigned& Reg, int& offset);
void SelectBranchCC(SDOperand N);
};
// not, since all 1's are not contiguous.
static bool IsRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
bool isRun = true;
- MB = 0;
+ MB = 0;
ME = 0;
// look for first set bit
break;
}
}
-
+
// look for last set bit
for (; i < 32; i++) {
if ((Val & (1 << (31 - i))) == 0)
if ((Val & (1 << (31 - i))) != 0)
break;
}
-
+
// if we exhausted all the bits, we found a match at this point for 0*1*0*
if (i == 32)
return true;
if ((Val & (1 << (31 - i))) == 0)
break;
}
-
+
// if we exhausted all the bits, then we found a match for 1*0*1*, otherwise,
// the value is not a run of ones.
if (i == 32)
if (N.getOpcode() != ISD::Constant) return 0;
int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
-
+
switch(Opcode) {
default: return 0;
case ISD::ADD:
switch(NodeOpcode) {
default: return false;
case ISD::AND:
- case ISD::OR:
+ case ISD::OR:
return true;
}
}
static unsigned getCRIdxForSetCC(unsigned Condition, bool& Inv) {
switch (Condition) {
default: assert(0 && "Unknown condition!"); abort();
- case ISD::SETULT:
+ case ISD::SETULT:
case ISD::SETLT: Inv = false; return 0;
case ISD::SETUGE:
case ISD::SETGE: Inv = true; return 0;
return 0;
}
-// Structure used to return the necessary information to codegen an SDIV as
+// Structure used to return the necessary information to codegen an SDIV as
// a multiply.
struct ms {
int m; // magic number
};
/// magic - calculate the magic numbers required to codegen an integer sdiv as
-/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
+/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
/// or -1.
static struct ms magic(int d) {
int p;
unsigned int ad, anc, delta, q1, r1, q2, r2, t;
const unsigned int two31 = 2147483648U; // 2^31
struct ms mag;
-
+
ad = abs(d);
t = two31 + ((unsigned int)d >> 31);
anc = t - 1 - t%ad; // absolute value of nc
int d = (int)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
ms magics = magic(d);
// Multiply the numerator (operand 0) by the magic value
- SDOperand Q = ISelDAG->getNode(ISD::MULHS, MVT::i32, N.getOperand(0),
+ SDOperand Q = ISelDAG->getNode(ISD::MULHS, MVT::i32, N.getOperand(0),
ISelDAG->getConstant(magics.m, MVT::i32));
// If d > 0 and m < 0, add the numerator
if (d > 0 && magics.m < 0)
Q = ISelDAG->getNode(ISD::SUB, MVT::i32, Q, N.getOperand(0));
// Shift right algebraic if shift value is nonzero
if (magics.s > 0)
- Q = ISelDAG->getNode(ISD::SRA, MVT::i32, Q,
+ Q = ISelDAG->getNode(ISD::SRA, MVT::i32, Q,
ISelDAG->getConstant(magics.s, MVT::i32));
// Extract the sign bit and add it to the quotient
- SDOperand T =
+ SDOperand T =
ISelDAG->getNode(ISD::SRL, MVT::i32, Q, ISelDAG->getConstant(31, MVT::i32));
return ISelDAG->getNode(ISD::ADD, MVT::i32, Q, T);
}
/// multiplying by a magic number. See:
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
SDOperand ISel::BuildUDIVSequence(SDOperand N) {
- unsigned d =
+ unsigned d =
(unsigned)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
mu magics = magicu(d);
// Multiply the numerator (operand 0) by the magic value
- SDOperand Q = ISelDAG->getNode(ISD::MULHU, MVT::i32, N.getOperand(0),
+ SDOperand Q = ISelDAG->getNode(ISD::MULHU, MVT::i32, N.getOperand(0),
ISelDAG->getConstant(magics.m, MVT::i32));
if (magics.a == 0) {
- Q = ISelDAG->getNode(ISD::SRL, MVT::i32, Q,
+ Q = ISelDAG->getNode(ISD::SRL, MVT::i32, Q,
ISelDAG->getConstant(magics.s, MVT::i32));
} else {
SDOperand NPQ = ISelDAG->getNode(ISD::SUB, MVT::i32, N.getOperand(0), Q);
- NPQ = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ,
+ NPQ = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ,
ISelDAG->getConstant(1, MVT::i32));
NPQ = ISelDAG->getNode(ISD::ADD, MVT::i32, NPQ, Q);
- Q = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ,
+ Q = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ,
ISelDAG->getConstant(magics.s-1, MVT::i32));
}
return Q;
return GlobalBaseReg;
}
-/// getConstDouble - Loads a floating point value into a register, via the
+/// getConstDouble - Loads a floating point value into a register, via the
/// Constant Pool. Optionally takes a register in which to load the value.
unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
unsigned Tmp1 = MakeReg(MVT::i32);
return Result;
}
-/// MoveCRtoGPR - Move CCReg[Idx] to the least significant bit of Result. If
+/// MoveCRtoGPR - Move CCReg[Idx] to the least significant bit of Result. If
/// Inv is true, then invert the result.
void ISel::MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result){
unsigned IntCR = MakeReg(MVT::i32);
}
}
-/// SelectBitfieldInsert - turn an or of two masked values into
+/// SelectBitfieldInsert - turn an or of two masked values into
/// the rotate left word immediate then mask insert (rlwimi) instruction.
/// Returns true on success, false if the caller still needs to select OR.
///
unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, Amount = 0;
unsigned Op0Opc = OR.getOperand(0).getOpcode();
unsigned Op1Opc = OR.getOperand(1).getOpcode();
-
+
// Verify that we have the correct opcodes
if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc)
return false;
if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc)
return false;
-
+
// Generate Mask value for Target
- if (ConstantSDNode *CN =
+ if (ConstantSDNode *CN =
dyn_cast<ConstantSDNode>(OR.getOperand(0).getOperand(1).Val)) {
switch(Op0Opc) {
case ISD::SHL: TgtMask <<= (unsigned)CN->getValue(); break;
} else {
return false;
}
-
+
// Generate Mask value for Insert
- if (ConstantSDNode *CN =
+ if (ConstantSDNode *CN =
dyn_cast<ConstantSDNode>(OR.getOperand(1).getOperand(1).Val)) {
switch(Op1Opc) {
- case ISD::SHL:
- Amount = CN->getValue();
+ case ISD::SHL:
+ Amount = CN->getValue();
InsMask <<= Amount;
if (Op0Opc == ISD::SRL) IsRotate = true;
break;
- case ISD::SRL:
- Amount = CN->getValue();
- InsMask >>= Amount;
+ case ISD::SRL:
+ Amount = CN->getValue();
+ InsMask >>= Amount;
Amount = 32-Amount;
if (Op0Opc == ISD::SHL) IsRotate = true;
break;
- case ISD::AND:
+ case ISD::AND:
InsMask &= (unsigned)CN->getValue();
break;
}
} else {
return false;
}
-
+
// Verify that the Target mask and Insert mask together form a full word mask
// and that the Insert mask is a run of set bits (which implies both are runs
// of set bits). Given that, Select the arguments and generate the rlwimi
unsigned Tmp1, Tmp2;
// Check for rotlwi / rotrwi here, a special case of bitfield insert
// where both bitfield halves are sourced from the same value.
- if (IsRotate &&
+ if (IsRotate &&
OR.getOperand(0).getOperand(0) == OR.getOperand(1).getOperand(0)) {
Tmp1 = SelectExpr(OR.getOperand(0).getOperand(0));
BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(Amount)
unsigned ISel::SelectCC(SDOperand CC, unsigned& Opc, bool &Inv, unsigned& Idx) {
unsigned Result, Tmp1, Tmp2;
bool AlreadySelected = false;
- static const unsigned CompareOpcodes[] =
+ static const unsigned CompareOpcodes[] =
{ PPC::FCMPU, PPC::FCMPU, PPC::CMPW, PPC::CMPLW };
-
+
// Allocate a condition register for this expression
Result = RegMap->createVirtualRegister(PPC32::CRRCRegisterClass);
-
+
// If the first operand to the select is a SETCC node, then we can fold it
// into the branch that selects which value to return.
if (SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val)) {
// Pass the optional argument U to getImmediateForOpcode for SETCC,
// so that it knows whether the SETCC immediate range is signed or not.
- if (1 == getImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC,
+ if (1 == getImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC,
Tmp2, U)) {
- // For comparisons against zero, we can implicity set CR0 if a recording
+ // For comparisons against zero, we can implicity set CR0 if a recording
// variant (e.g. 'or.' instead of 'or') of the instruction that defines
// operand zero of the SetCC node is available.
- if (0 == Tmp2 &&
+ if (0 == Tmp2 &&
NodeHasRecordingVariant(SetCC->getOperand(0).getOpcode()) &&
SetCC->getOperand(0).Val->hasOneUse()) {
RecordSuccess = false;
return Result;
}
-unsigned ISel::SelectCCExpr(SDOperand N, unsigned& Opc, bool &Inv,
+unsigned ISel::SelectCCExpr(SDOperand N, unsigned& Opc, bool &Inv,
unsigned &Idx) {
bool Inv0, Inv1;
unsigned Idx0, Idx1, CROpc, Opc1, Tmp1, Tmp2;
if (1 == getImmediateForOpcode(N.getOperand(1), opcode, imm)) {
offset = imm;
return false;
- }
+ }
offset = SelectExpr(N.getOperand(1));
return true;
}
void ISel::SelectBranchCC(SDOperand N)
{
- MachineBasicBlock *Dest =
+ MachineBasicBlock *Dest =
cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
bool Inv;
unsigned Opc, CCReg, Idx;
Select(N.getOperand(0)); //chain
CCReg = SelectCC(N.getOperand(1), Opc, Inv, Idx);
-
+
// Iterate to the next basic block, unless we're already at the end of the
ilist<MachineBasicBlock>::iterator It = BB, E = BB->getParent()->end();
if (++It == E) It = BB;
// if necessary by the branch selection pass. Otherwise, emit a standard
// conditional branch.
if (N.getOpcode() == ISD::BRCONDTWOWAY) {
- MachineBasicBlock *Fallthrough =
+ MachineBasicBlock *Fallthrough =
cast<BasicBlockSDNode>(N.getOperand(3))->getBasicBlock();
if (Dest != It) {
BuildMI(BB, PPC::COND_BRANCH, 4).addReg(CCReg).addImm(Opc)
MVT::ValueType VT = SetCC->getOperand(0).getValueType();
unsigned TV = SelectExpr(N.getOperand(1)); // Use if TRUE
unsigned FV = SelectExpr(N.getOperand(2)); // Use if FALSE
-
+
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1));
if (CN && (CN->isExactlyValue(-0.0) || CN->isExactlyValue(0.0))) {
switch(SetCC->getCondition()) {
assert(0 && "Should never get here");
return 0;
}
-
+
bool Inv;
unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
unsigned CCReg = SelectCC(N.getOperand(0), Opc, Inv, Tmp3);
- // Create an iterator with which to insert the MBB for copying the false
+ // Create an iterator with which to insert the MBB for copying the false
// value and the MBB to hold the PHI instruction for this SetCC.
MachineBasicBlock *thisMBB = BB;
const BasicBlock *LLVM_BB = BB->getBasicBlock();
}
case ISD::FNEG:
- if (!NoExcessFPPrecision &&
+ if (!NoExcessFPPrecision &&
ISD::ADD == N.getOperand(0).getOpcode() &&
N.getOperand(0).Val->hasOneUse() &&
ISD::MUL == N.getOperand(0).getOperand(0).getOpcode() &&
Tmp3 = SelectExpr(N.getOperand(0).getOperand(1));
Opc = DestType == MVT::f64 ? PPC::FNMADD : PPC::FNMADDS;
BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
- } else if (!NoExcessFPPrecision &&
+ } else if (!NoExcessFPPrecision &&
ISD::ADD == N.getOperand(0).getOpcode() &&
N.getOperand(0).Val->hasOneUse() &&
ISD::MUL == N.getOperand(0).getOperand(1).getOpcode() &&
BuildMI(BB, PPC::FNEG, 1, Result).addReg(Tmp1);
}
return Result;
-
+
case ISD::FABS:
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, PPC::FABS, 1, Result).addReg(Tmp1);
return Result;
case ISD::FP_ROUND:
- assert (DestType == MVT::f32 &&
- N.getOperand(0).getValueType() == MVT::f64 &&
+ assert (DestType == MVT::f32 &&
+ N.getOperand(0).getValueType() == MVT::f64 &&
"only f64 to f32 conversion supported here");
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, PPC::FRSP, 1, Result).addReg(Tmp1);
return Result;
case ISD::FP_EXTEND:
- assert (DestType == MVT::f64 &&
- N.getOperand(0).getValueType() == MVT::f32 &&
+ assert (DestType == MVT::f64 &&
+ N.getOperand(0).getValueType() == MVT::f32 &&
"only f32 to f64 conversion supported here");
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
return Result;
-
+
case ISD::ConstantFP: {
ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
Result = getConstDouble(CN->getValue(), Result);
return Result;
}
-
+
case ISD::ADD:
if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::MUL &&
N.getOperand(0).Val->hasOneUse()) {
case ISD::UINT_TO_FP:
case ISD::SINT_TO_FP: {
- assert (N.getOperand(0).getValueType() == MVT::i32
+ assert (N.getOperand(0).getValueType() == MVT::i32
&& "int to float must operate on i32");
bool IsUnsigned = (ISD::UINT_TO_FP == opcode);
Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
Tmp2 = MakeReg(MVT::f64); // temp reg to load the integer value into
Tmp3 = MakeReg(MVT::i32); // temp reg to hold the conversion constant
-
+
int FrameIdx = BB->getParent()->getFrameInfo()->CreateStackObject(8, 8);
MachineConstantPool *CP = BB->getParent()->getConstantPool();
-
+
if (IsUnsigned) {
unsigned ConstF = getConstDouble(0x1.000000p52);
// Store the hi & low halves of the fp value, currently in int regs
if (ISD::CopyFromReg == opcode)
DestType = N.getValue(0).getValueType();
-
+
if (DestType == MVT::f64 || DestType == MVT::f32)
- if (ISD::LOAD != opcode && ISD::EXTLOAD != opcode &&
+ if (ISD::LOAD != opcode && ISD::EXTLOAD != opcode &&
ISD::UNDEF != opcode && ISD::CALL != opcode)
return SelectExprFP(N, Result);
Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
addFrameReference(BuildMI(BB, PPC::ADDI, 2, Result), (int)Tmp1, 0, false);
return Result;
-
+
case ISD::GlobalAddress: {
GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
Tmp1 = MakeReg(MVT::i32);
MVT::ValueType TypeBeingLoaded = (ISD::LOAD == opcode) ?
Node->getValueType(0) : cast<MVTSDNode>(Node)->getExtraValueType();
bool sext = (ISD::SEXTLOAD == opcode);
-
+
// Make sure we generate both values.
if (Result != 1)
ExprMap[N.getValue(1)] = 1; // Generate the token
case MVT::f32: Opc = PPC::LFS; break;
case MVT::f64: Opc = PPC::LFD; break;
}
-
+
if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
Tmp1 = MakeReg(MVT::i32);
int CPI = CP->getIndex();
}
return Result;
}
-
+
case ISD::CALL: {
unsigned GPR_idx = 0, FPR_idx = 0;
- static const unsigned GPR[] = {
+ static const unsigned GPR[] = {
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
PPC::R7, PPC::R8, PPC::R9, PPC::R10,
};
MachineInstr *CallMI;
// Emit the correct call instruction based on the type of symbol called.
- if (GlobalAddressSDNode *GASD =
+ if (GlobalAddressSDNode *GASD =
dyn_cast<GlobalAddressSDNode>(N.getOperand(1))) {
- CallMI = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(GASD->getGlobal(),
+ CallMI = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(GASD->getGlobal(),
true);
- } else if (ExternalSymbolSDNode *ESSDN =
+ } else if (ExternalSymbolSDNode *ESSDN =
dyn_cast<ExternalSymbolSDNode>(N.getOperand(1))) {
- CallMI = BuildMI(PPC::CALLpcrel, 1).addExternalSymbol(ESSDN->getSymbol(),
+ CallMI = BuildMI(PPC::CALLpcrel, 1).addExternalSymbol(ESSDN->getSymbol(),
true);
} else {
Tmp1 = SelectExpr(N.getOperand(1));
CallMI = BuildMI(PPC::CALLindirect, 3).addImm(20).addImm(0)
.addReg(PPC::R12);
}
-
+
// Load the register args to virtual regs
std::vector<unsigned> ArgVR;
for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
break;
}
}
-
+
// Put the call instruction in the correct place in the MachineBasicBlock
BB->push_back(CallMI);
switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
default: Node->dump(); assert(0 && "Unhandled SIGN_EXTEND type"); break;
case MVT::i16:
- BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1);
+ BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1);
break;
case MVT::i8:
- BuildMI(BB, PPC::EXTSB, 1, Result).addReg(Tmp1);
+ BuildMI(BB, PPC::EXTSB, 1, Result).addReg(Tmp1);
break;
case MVT::i1:
BuildMI(BB, PPC::SUBFIC, 2, Result).addReg(Tmp1).addSImm(0);
break;
}
return Result;
-
+
case ISD::CopyFromReg:
if (Result == 1)
Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
BuildMI(BB, PPC::SLW, 2, Result).addReg(Tmp1).addReg(Tmp2);
}
return Result;
-
+
case ISD::SRL:
Tmp1 = SelectExpr(N.getOperand(0));
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
BuildMI(BB, PPC::SRW, 2, Result).addReg(Tmp1).addReg(Tmp2);
}
return Result;
-
+
case ISD::SRA:
Tmp1 = SelectExpr(N.getOperand(0));
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
BuildMI(BB, PPC::SRAW, 2, Result).addReg(Tmp1).addReg(Tmp2);
}
return Result;
-
+
case ISD::ADD:
assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
Tmp1 = SelectExpr(N.getOperand(0));
case ISD::AND:
if (PPCCRopts) {
- if (N.getOperand(0).getOpcode() == ISD::SETCC ||
+ if (N.getOperand(0).getOpcode() == ISD::SETCC ||
N.getOperand(1).getOpcode() == ISD::SETCC) {
bool Inv;
Tmp1 = SelectCCExpr(N, Opc, Inv, Tmp2);
}
RecordSuccess = true;
return Result;
-
+
case ISD::OR:
if (SelectBitfieldInsert(N, Result))
return Result;
if (PPCCRopts) {
- if (N.getOperand(0).getOpcode() == ISD::SETCC ||
+ if (N.getOperand(0).getOpcode() == ISD::SETCC ||
N.getOperand(1).getOpcode() == ISD::SETCC) {
bool Inv;
Tmp1 = SelectCCExpr(N, Opc, Inv, Tmp2);
BuildMI(BB, PPC::SUBF, 2, Result).addReg(Tmp2).addReg(Tmp1);
}
return Result;
-
+
case ISD::MUL:
Tmp1 = SelectExpr(N.getOperand(0));
if (1 == getImmediateForOpcode(N.getOperand(1), opcode, Tmp2))
// constants to implement it as a multiply instead.
case 4:
ExprMap.erase(N);
- if (opcode == ISD::SDIV)
+ if (opcode == ISD::SDIV)
return SelectExpr(BuildSDIVSequence(N));
else
return SelectExpr(BuildUDIVSequence(N));
}
return Result+N.ResNo;
}
-
+
case ISD::FP_TO_UINT:
case ISD::FP_TO_SINT: {
bool U = (ISD::FP_TO_UINT == opcode);
assert(0 && "Should never get here");
return 0;
}
-
+
case ISD::SETCC:
if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node)) {
- if (ConstantSDNode *CN =
+ if (ConstantSDNode *CN =
dyn_cast<ConstantSDNode>(SetCC->getOperand(1).Val)) {
// We can codegen setcc op, imm very efficiently compared to a brcond.
// Check for those cases here.
return Result;
}
}
-
+
bool Inv;
unsigned CCReg = SelectCC(N, Opc, Inv, Tmp2);
MoveCRtoGPR(CCReg, Inv, Tmp2, Result);
}
assert(0 && "Is this legal?");
return 0;
-
+
case ISD::SELECT: {
bool Inv;
unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
unsigned CCReg = SelectCC(N.getOperand(0), Opc, Inv, Tmp3);
- // Create an iterator with which to insert the MBB for copying the false
+ // Create an iterator with which to insert the MBB for copying the false
// value and the MBB to hold the PHI instruction for this SetCC.
MachineBasicBlock *thisMBB = BB;
const BasicBlock *LLVM_BB = BB->getBasicBlock();
return; // Already selected.
SDNode *Node = N.Val;
-
+
switch (Node->getOpcode()) {
default:
Node->dump(); std::cerr << "\n";
BuildMI(BB, PPC::B, 1).addMBB(Dest);
return;
}
- case ISD::BRCOND:
+ case ISD::BRCOND:
case ISD::BRCONDTWOWAY:
SelectBranchCC(N);
return;
Select(N.getOperand(0));
Tmp1 = SelectExpr(N.getOperand(1));
Tmp2 = cast<RegSDNode>(N)->getReg();
-
+
if (Tmp1 != Tmp2) {
- if (N.getOperand(1).getValueType() == MVT::f64 ||
+ if (N.getOperand(1).getValueType() == MVT::f64 ||
N.getOperand(1).getValueType() == MVT::f32)
BuildMI(BB, PPC::FMR, 1, Tmp2).addReg(Tmp1);
else
}
BuildMI(BB, PPC::BLR, 0); // Just emit a 'ret' instruction
return;
- case ISD::TRUNCSTORE:
- case ISD::STORE:
+ case ISD::TRUNCSTORE:
+ case ISD::STORE:
{
SDOperand Chain = N.getOperand(0);
SDOperand Value = N.getOperand(1);
{
int offset;
bool idx = SelectAddr(Address, Tmp2, offset);
- if (idx) {
+ if (idx) {
Opc = IndexedOpForOp(Opc);
BuildMI(BB, Opc, 3).addReg(Tmp1).addReg(Tmp2).addReg(offset);
} else {
/// description file.
///
FunctionPass *llvm::createPPC32ISelPattern(TargetMachine &TM) {
- return new ISel(TM);
+ return new ISel(TM);
}
//===-- PowerPCInstrBuilder.h - Aides for building PPC insts ----*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file exposes functions that may be used with BuildMI from the
/// This allows a constant offset to be specified as well...
///
inline const MachineInstrBuilder&
-addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
+addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
bool mem = true) {
if (mem)
return MIB.addSImm(Offset).addFrameIndex(FI);
//===- PPC32InstrInfo.cpp - PowerPC32 Instruction Information ---*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the PowerPC implementation of the TargetInstrInfo class.
//===- PPC32InstrInfo.h - PowerPC32 Instruction Information -----*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the PowerPC implementation of the TargetInstrInfo class.
case PPC::BGE: return PPC::BLT;
case PPC::BGT: return PPC::BLE;
case PPC::BLE: return PPC::BGT;
- }
+ }
}
};
//===-- PPC32JITInfo.cpp - Implement the JIT interfaces for the PowerPC ---===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file implements the JIT interfaces for the 32-bit PowerPC target.
"stw r11, 280(r1)\n" // Set up a proper stack frame
"stmw r3, 156(r1)\n" // Save all of the integer registers
// Save all call-clobbered FP regs.
- "stfd f1, 44(r1)\n" "stfd f2, 52(r1)\n" "stfd f3, 60(r1)\n"
- "stfd f4, 68(r1)\n" "stfd f5, 76(r1)\n" "stfd f6, 84(r1)\n"
- "stfd f7, 92(r1)\n" "stfd f8, 100(r1)\n" "stfd f9, 108(r1)\n"
+ "stfd f1, 44(r1)\n" "stfd f2, 52(r1)\n" "stfd f3, 60(r1)\n"
+ "stfd f4, 68(r1)\n" "stfd f5, 76(r1)\n" "stfd f6, 84(r1)\n"
+ "stfd f7, 92(r1)\n" "stfd f8, 100(r1)\n" "stfd f9, 108(r1)\n"
"stfd f10, 116(r1)\n" "stfd f11, 124(r1)\n" "stfd f12, 132(r1)\n"
"stfd f13, 140(r1)\n"
CameFromOrig[-1] = CameFromOrigInst;
}
}
-
+
// Locate the start of the stub. If this is a short call, adjust backwards
// the short amount, otherwise the full amount.
bool isShortStub = (*CameFromStub >> 26) == 18;
register unsigned *IRR asm ("r2") = IntRegs;
register double *FRR asm ("r3") = FPRegs;
__asm__ __volatile__ (
- "lfd f1, 0(%0)\n" "lfd f2, 8(%0)\n" "lfd f3, 16(%0)\n"
- "lfd f4, 24(%0)\n" "lfd f5, 32(%0)\n" "lfd f6, 40(%0)\n"
- "lfd f7, 48(%0)\n" "lfd f8, 56(%0)\n" "lfd f9, 64(%0)\n"
+ "lfd f1, 0(%0)\n" "lfd f2, 8(%0)\n" "lfd f3, 16(%0)\n"
+ "lfd f4, 24(%0)\n" "lfd f5, 32(%0)\n" "lfd f6, 40(%0)\n"
+ "lfd f7, 48(%0)\n" "lfd f8, 56(%0)\n" "lfd f9, 64(%0)\n"
"lfd f10, 72(%0)\n" "lfd f11, 80(%0)\n" "lfd f12, 88(%0)\n"
"lfd f13, 96(%0)\n"
"lmw r3, 0(%1)\n" // Load all integer regs
"mtctr r0\n" // Put it into the CTR register
"lwz r1,0(r1)\n" // Pop two frames off
"bctr\n" :: // Return to stub!
- "b" (FRR), "b" (IRR));
+ "b" (FRR), "b" (IRR));
#endif
}
-TargetJITInfo::LazyResolverFn
+TargetJITInfo::LazyResolverFn
PPC32JITInfo::getLazyResolverFunction(JITCompilerFn Fn) {
JITCompilerFunction = Fn;
return PPC32CompilationCallback;
//===- PowerPCJITInfo.h - PowerPC impl. of the JIT interface ----*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the PowerPC implementation of the TargetJITInfo class.
//===- PPC32RegisterInfo.cpp - PowerPC32 Register Information ---*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the PowerPC32 implementation of the MRegisterInfo class.
PPC32RegisterInfo::PPC32RegisterInfo()
: PPC32GenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
- ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
+ ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
abort();
}
-void
+void
PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, int FrameIdx) const {
- static const unsigned Opcode[] = {
- PPC::STB, PPC::STH, PPC::STW, PPC::STFS, PPC::STFD
+ static const unsigned Opcode[] = {
+ PPC::STB, PPC::STH, PPC::STW, PPC::STFS, PPC::STFD
};
unsigned OC = Opcode[getIdx(getClass(SrcReg))];
if (SrcReg == PPC::LR) {
PPC32RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIdx) const{
- static const unsigned Opcode[] = {
- PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD
+ static const unsigned Opcode[] = {
+ PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD
};
unsigned OC = Opcode[getIdx(getClass(DestReg))];
if (DestReg == PPC::LR) {
// alignment boundary.
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
Amount = (Amount+Align-1)/Align*Align;
-
+
// Replace the pseudo instruction with a new instruction...
if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
-
+
while (!MI.getOperand(i).isFrameIndex()) {
++i;
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
// SP before having the stack size subtracted from it, then add the stack size
// to Offset to get the correct offset.
Offset += MF.getFrameInfo()->getStackSize();
-
+
if (Offset > 32767 || Offset < -32768) {
// Insert a set of r0 with the full offset value before the ld, st, or add
MachineBasicBlock *MBB = MI.getParent();
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
MachineInstr *MI;
-
+
// Get the number of bytes to allocate from the FrameInfo
unsigned NumBytes = MFI->getStackSize();
// If we have calls, we cannot use the red zone to store callee save registers
// and we must set up a stack frame, so calculate the necessary size here.
if (MFI->hasCalls()) {
- // We reserve argument space for call sites in the function immediately on
- // entry to the current function. This eliminates the need for add/sub
+ // We reserve argument space for call sites in the function immediately on
+ // entry to the current function. This eliminates the need for add/sub
// brackets around call sites.
NumBytes += MFI->getMaxCallFrameSize();
}
// Do we need to allocate space on the stack?
if (NumBytes == 0) return;
- // Add the size of R1 to NumBytes size for the store of R1 to the bottom
+ // Add the size of R1 to NumBytes size for the store of R1 to the bottom
// of the stack and round the size to a multiple of the alignment.
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
unsigned GPRSize = getSpillSize(PPC::R1)/8;
MI = BuildMI(PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
MBB.insert(MBBI, MI);
}
-
+
if (hasFP(MF)) {
MI = BuildMI(PPC::STW, 3).addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
MBB.insert(MBBI, MI);
MachineInstr *MI;
assert(MBBI->getOpcode() == PPC::BLR &&
"Can only insert epilog into returning blocks");
-
+
// Get the number of bytes allocated from the FrameInfo...
unsigned NumBytes = MFI->getStackSize();
unsigned GPRSize = getSpillSize(PPC::R31)/8;
case Type::IntTyID:
case Type::UIntTyID:
case Type::PointerTyID: return &GPRCInstance;
-
+
case Type::FloatTyID:
case Type::DoubleTyID: return &FPRCInstance;
}
//===- PPC32RegisterInfo.h - PowerPC32 Register Information Impl -*- C++ -*-==//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the PowerPC implementation of the MRegisterInfo class.
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex) const;
-
+
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
//===- PPC32Relocations.h - PPC32 Code Relocations --------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file defines the PowerPC 32-bit target-specific relocation types.
//===-- PowerPCTargetMachine.cpp - Define TargetMachine for PowerPC -------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
//
//===----------------------------------------------------------------------===//
namespace llvm {
bool PPCCRopts;
- cl::opt<bool> AIX("aix",
- cl::desc("Generate AIX/xcoff instead of Darwin/MachO"),
+ cl::opt<bool> AIX("aix",
+ cl::desc("Generate AIX/xcoff instead of Darwin/MachO"),
cl::Hidden);
- cl::opt<bool> EnablePPCLSR("enable-lsr-for-ppc",
- cl::desc("Enable LSR for PPC (beta)"),
+ cl::opt<bool> EnablePPCLSR("enable-lsr-for-ppc",
+ cl::desc("Enable LSR for PPC (beta)"),
cl::Hidden);
- cl::opt<bool, true> EnablePPCCRopts("enable-cc-opts",
+ cl::opt<bool, true> EnablePPCCRopts("enable-cc-opts",
cl::desc("Enable opts using condition regs (beta)"),
cl::location(PPCCRopts),
cl::init(false),
namespace {
const std::string PPC32ID = "PowerPC/32bit";
const std::string PPC64ID = "PowerPC/64bit";
-
+
// Register the targets
- RegisterTarget<PPC32TargetMachine>
+ RegisterTarget<PPC32TargetMachine>
X("ppc32", " PowerPC 32-bit");
#if 0
- RegisterTarget<PPC64TargetMachine>
+ RegisterTarget<PPC64TargetMachine>
Y("ppc64", " PowerPC 64-bit (unimplemented)");
#endif
}
PM.add(createLoopStrengthReducePass());
PM.add(createCFGSimplificationPass());
}
-
+
// FIXME: Implement efficient support for garbage collection intrinsics.
PM.add(createLowerGCPass());
PM.add(createMachineFunctionPrinterPass(&std::cerr));
PM.add(createPrologEpilogCodeInserter());
-
+
// Must run branch selection immediately preceding the asm printer
PM.add(createPPCBranchSelectionPass());
-
+
if (AIX)
PM.add(createAIXAsmPrinter(Out, *this));
else
PM.add(createDarwinAsmPrinter(Out, *this));
-
+
PM.add(createMachineCodeDeleter());
return false;
}
/// PowerPCTargetMachine ctor - Create an ILP32 architecture model
///
PPC32TargetMachine::PPC32TargetMachine(const Module &M, IntrinsicLowering *IL)
- : PowerPCTargetMachine(PPC32ID, IL,
+ : PowerPCTargetMachine(PPC32ID, IL,
TargetData(PPC32ID,false,4,4,4,4,4,4,2,1,1),
PowerPCFrameInfo(*this, false)), JITInfo(*this) {}
//===-- PPC32TargetMachine.h - Define TargetMachine for PowerPC -*- C++ -*-=//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file declares the PowerPC specific subclass of TargetMachine.
//
//===----------------------------------------------------------------------===//
//===- PowerPCInstrInfo.h - PowerPC Instruction Information -----*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the PowerPC implementation of the TargetInstrInfo class.
VMX = 1 << 0,
PPC64 = 1 << 1,
};
-
+
enum {
None = 0,
Gpr = 1,
//===-- PowerPCTargetMachine.h - Define TargetMachine for PowerPC -*- C++ -*-=//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file declares the PowerPC-specific subclass of TargetMachine.
//
//===----------------------------------------------------------------------===//
//===-- Skeleton.h - Target private header file -----------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the definitions shared among the various components of the
//===- SkeletonInstrInfo.cpp - Instruction Information ----------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This is where you implement methods for the TargetInstrInfo class.
//===- SkeletonInstrInfo.h - Instruction Information ------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file is where the target-specific implementation of the TargetInstrInfo
const SkeletonRegisterInfo RI;
public:
SkeletonInstrInfo();
-
+
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
//===-- SkeletonCodeEmitter.cpp - JIT Code Emitter --------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This is a stub for a JIT code generator, which is obviously not implemented.
//
//===----------------------------------------------------------------------===//
//===- SkeletonJITInfo.h - Skeleton impl of JIT interface -------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the skeleton implementation of the TargetJITInfo class.
/// is not supported for this target.
///
virtual void addPassesToJITCompile(FunctionPassManager &PM);
-
+
/// replaceMachineCodeForFunction - Make it so that calling the function
/// whose machine code is at OLD turns into a call to NEW, perhaps by
/// overwriting OLD with a branch to NEW. This is used for self-modifying
//===- SkeletonRegisterInfo.cpp - Skeleton Register Information -*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the Skeleton implementation of the MRegisterInfo class.
abort();
}
-void SkeletonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II)
+void SkeletonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II)
const {
abort();
}
case Type::IntTyID:
case Type::UIntTyID:
case Type::PointerTyID: return &GPRCInstance;
-
+
case Type::FloatTyID:
case Type::DoubleTyID: return &FPRCInstance;
}
//===- SkeletonRegisterInfo.h - Skeleton Register Information Impl -*- C++ -*-==//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the Skeleton implementation of the MRegisterInfo class.
struct SkeletonRegisterInfo : public SkeletonGenRegisterInfo {
SkeletonRegisterInfo();
const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
-
+
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, int FrameIndex) const;
-
+
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex) const;
-
+
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
-
+
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const;
-
+
void eliminateFrameIndex(MachineBasicBlock::iterator II) const;
-
+
void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
-
+
void emitPrologue(MachineFunction &MF) const;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
};
//===-- SkeletonTargetMachine.cpp - Define TargetMachine for Skeleton -----===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
//
//===----------------------------------------------------------------------===//
//===-- SkeletonTargetMachine.h - TargetMachine for Skeleton ----*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file declares the Skeleton specific subclass of TargetMachine.
//
//===----------------------------------------------------------------------===//
virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
MachineCodeEmitter &MCE);
-
+
virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
};
//===-- DelaySlotFiller.cpp - SparcV8 delay slot filler -------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This is a simple local pass that fills delay slots with NOPs.
//===-- FPMover.cpp - SparcV8 double-precision floating point move fixer --===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Turns FpMOVD instructions into FMOVS pairs after regalloc.
//===-- SparcV8.h - Top-level interface for SparcV8 representation -*- C++ -*-//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the entry points for global functions defined in the LLVM
//===-- SparcV8AsmPrinter.cpp - SparcV8 LLVM assembly writer --------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains a printer that converts from our internal representation
void printOperand(const MachineInstr *MI, int opNum);
void printBaseOffsetPair (const MachineInstr *MI, int i, bool brackets=true);
void printMachineInstruction(const MachineInstr *MI);
- bool runOnMachineFunction(MachineFunction &F);
+ bool runOnMachineFunction(MachineFunction &F);
bool doInitialization(Module &M);
bool doFinalization(Module &M);
};
// Print a constant value or values, with the appropriate storage class as a
// prefix.
-void V8Printer::emitGlobalConstant(const Constant *CV) {
+void V8Printer::emitGlobalConstant(const Constant *CV) {
const TargetData &TD = TM.getTargetData();
if (const ConstantArray *CVA = dyn_cast<ConstantArray>(CV)) {
// Insert the field padding unless it's zero bytes...
if (padSize)
- O << "\t.skip\t " << padSize << "\n";
+ O << "\t.skip\t " << padSize << "\n";
}
assert(sizeSoFar == cvsLayout->StructSize &&
"Layout of constant struct may be incorrect!");
}
} else if (isa<UndefValue> (CV)) {
unsigned size = TD.getTypeSize (CV->getType ());
- O << "\t.skip\t " << size << "\n";
+ O << "\t.skip\t " << size << "\n";
return;
} else if (isa<ConstantAggregateZero> (CV)) {
unsigned size = TD.getTypeSize (CV->getType ());
void V8Printer::printConstantPool(MachineConstantPool *MCP) {
const std::vector<Constant*> &CP = MCP->getConstants();
const TargetData &TD = TM.getTargetData();
-
+
if (CP.empty()) return;
for (unsigned i = 0, e = CP.size(); i != e; ++i) {
O << ".CPI" << CurrentFnName << "_" << MO.getConstantPoolIndex();
break;
default:
- O << "<unknown operand type>"; abort (); break;
+ O << "<unknown operand type>"; abort (); break;
}
if (CloseParen) O << ")";
}
O << "! ";
O << Desc.Name << " ";
-
+
// Printing memory instructions is a special case.
// for loads: %dest = op %base, offset --> op [%base + offset], %dest
// for stores: op %base, offset, %src --> op %src, [%base + offset]
for (unsigned i = 0; i < MI->getNumOperands (); ++i)
if (MI->getOperand (i).isRegister () && MI->getOperand (i).isDef ())
print_order.push_back (i);
- for (unsigned i = 0, e = print_order.size (); i != e; ++i) {
+ for (unsigned i = 0, e = print_order.size (); i != e; ++i) {
printOperand (MI, print_order[i]);
if (i != (print_order.size () - 1))
O << ", ";
unsigned Size = TD.getTypeSize(C->getType());
unsigned Align = TD.getTypeAlignment(C->getType());
- if (C->isNullValue() &&
+ if (C->isNullValue() &&
(I->hasLinkOnceLinkage() || I->hasInternalLinkage() ||
I->hasWeakLinkage() /* FIXME: Verify correct */)) {
SwitchSection(O, CurSection, ".data");
if (I->hasInternalLinkage())
O << "\t.local " << name << "\n";
-
+
O << "\t.comm " << name << "," << TD.getTypeSize(C->getType())
<< "," << (unsigned)TD.getTypeAlignment(C->getType());
O << "\t\t! ";
SwitchSection(O, CurSection, "");
O << "\t.section\t\".llvm.linkonce.d." << name << "\",\"aw\",@progbits\n";
break;
-
+
case GlobalValue::AppendingLinkage:
// FIXME: appending linkage variables should go into a section of
// their name or something. For now, just emit them as external.
//===- SparcV8InstrInfo.cpp - SparcV8 Instruction Information ---*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV8 implementation of the TargetInstrInfo class.
//===- SparcV8InstrInfo.h - SparcV8 Instruction Information -----*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV8 implementation of the TargetInstrInfo class.
//===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV8 implementation of the MRegisterInfo class.
const TargetRegisterClass *RC = getClass(SrcReg);
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
- if (RC == SparcV8::IntRegsRegisterClass)
+ if (RC == SparcV8::IntRegsRegisterClass)
BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0)
.addReg (SrcReg);
else if (RC == SparcV8::FPRegsRegisterClass)
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, int FrameIdx) const {
const TargetRegisterClass *RC = getClass(DestReg);
- if (RC == SparcV8::IntRegsRegisterClass)
+ if (RC == SparcV8::IntRegsRegisterClass)
BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
else if (RC == SparcV8::FPRegsRegisterClass)
BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx)
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const {
- if (RC == SparcV8::IntRegsRegisterClass)
+ if (RC == SparcV8::IntRegsRegisterClass)
BuildMI (MBB, I, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
else if (RC == SparcV8::FPRegsRegisterClass)
BuildMI (MBB, I, V8::FMOVS, 1, DestReg).addReg (SrcReg);
//===- SparcV8RegisterInfo.h - SparcV8 Register Information Impl -*- C++ -*-==//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV8 implementation of the MRegisterInfo class.
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex) const;
-
+
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
//===-- SparcV8TargetMachine.cpp - Define TargetMachine for SparcV8 -------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
//
//===----------------------------------------------------------------------===//
// Print LLVM code input to instruction selector:
if (PrintMachineCode)
PM.add(new PrintFunctionPass());
-
+
PM.add(createSparcV8SimpleInstructionSelector(*this));
// Print machine instructions as they were initially generated.
// Replace malloc and free instructions with library calls.
PM.add(createLowerAllocationsPass());
-
+
// FIXME: implement the switch instruction in the instruction selector.
PM.add(createLowerSwitchPass());
PM.add(createLowerInvokePass());
PM.add(createLowerConstantExpressionsPass());
-
+
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
// FIXME: implement the select instruction in the instruction selector.
PM.add(createLowerSelectPass());
-
+
// Print LLVM code input to instruction selector:
if (PrintMachineCode)
PM.add(new PrintFunctionPass());
-
+
PM.add(createSparcV8SimpleInstructionSelector(TM));
// Print machine instructions as they were initially generated.
//===-- SparcV8TargetMachine.h - Define TargetMachine for SparcV8 -*- C++ -*-=//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file declares the SparcV8 specific subclass of TargetMachine.
//
//===----------------------------------------------------------------------===//
///
virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
MachineCodeEmitter &MCE);
-
+
virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
};
//===-- SparcV8CodeEmitter.cpp - JIT Code Emitter for SparcV8 -----*- C++ -*-=//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
//
//===----------------------------------------------------------------------===//
MachineCodeEmitter &MCE) {
// Keep as `true' until this is a functional JIT to allow llvm-gcc to build
return true;
-
+
// Machine code emitter pass for SparcV8
PM.add(new SparcV8CodeEmitter(*this, MCE));
// Delete machine code for this function after emitting it
//===-- InstSelectSimple.cpp - A simple instruction selector for SparcV8 --===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file defines a simple peephole instruction selector for the V8 target
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm (0);
} else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
// Copy it with a SETHI/OR pair; the JIT + asmwriter should recognize
- // that SETHI %reg,global == SETHI %reg,%hi(global) and
+ // that SETHI %reg,global == SETHI %reg,%hi(global) and
// OR %reg,global,%reg == OR %reg,%lo(global),%reg.
unsigned TmpReg = makeAnotherReg (C->getType ());
BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addGlobalAddress(GV);
const unsigned *IAR = &IncomingArgRegs[0];
unsigned ArgOffset = 68;
- // Store registers onto stack if this is a varargs function.
+ // Store registers onto stack if this is a varargs function.
// FIXME: This doesn't really pertain to "loading arguments into
// virtual registers", so it's not clear that it really belongs here.
- // FIXME: We could avoid storing any args onto the stack that don't
+ // FIXME: We could avoid storing any args onto the stack that don't
// need to be in memory, because they come before the ellipsis in the
// parameter list (and thus could never be accessed through va_arg).
if (LF->getFunctionType ()->isVarArg ()) {
break;
}
assert (PredMBB && "Couldn't find incoming machine-cfg edge for phi");
-
+
unsigned ValReg;
std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
PHIValues.lower_bound(PredMBB);
// predecessor. Recycle it.
ValReg = EntryIt->second;
- } else {
+ } else {
// Get the incoming value into a virtual register.
//
Value *Val = PN->getIncomingValue(i);
// might be arbitrarily complex if it is a constant expression),
// just insert the computation at the top of the basic block.
MachineBasicBlock::iterator PI = PredMBB->begin();
-
+
// Skip over any PHI nodes though!
while (PI != PredMBB->end() && PI->getOpcode() == V8::PHI)
++PI;
-
+
ValReg = getReg(Val, PredMBB, PI);
}
// First pass over the function, lower any unknown intrinsic functions
// with the IntrinsicLowering class.
LowerUnknownIntrinsicFunctionCalls(Fn);
-
+
F = &MachineFunction::construct(&Fn, TM);
-
+
// Create all of the machine basic blocks for the function...
for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
-
+
BB = &F->front();
-
+
// Set up a frame object for the return address. This is used by the
// llvm.returnaddress & llvm.frameaddress intrinisics.
//ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
-
+
// Copy incoming arguments off of the stack and out of fixed registers.
LoadArgumentsToVirtualRegs(&Fn);
-
+
// Instruction select everything except PHI nodes
visit(Fn);
-
+
// Select the PHI nodes
SelectPHINodes();
-
+
RegMap.clear();
MBBMap.clear();
F = 0;
const Type *newTy, unsigned DestReg) {
unsigned FPCastOpcode, FPStoreOpcode, FPSize, FPAlign;
unsigned oldTyClass = getClassB(oldTy);
- if (oldTyClass == cFloat) {
- FPCastOpcode = V8::FSTOI; FPStoreOpcode = V8::STFri; FPSize = 4;
+ if (oldTyClass == cFloat) {
+ FPCastOpcode = V8::FSTOI; FPStoreOpcode = V8::STFri; FPSize = 4;
FPAlign = TM.getTargetData().getFloatAlignment();
} else { // it's a double
- FPCastOpcode = V8::FDTOI; FPStoreOpcode = V8::STDFri; FPSize = 8;
+ FPCastOpcode = V8::FDTOI; FPStoreOpcode = V8::STDFri; FPSize = 8;
FPAlign = TM.getTargetData().getDoubleAlignment();
}
unsigned TempReg = makeAnotherReg (oldTy);
case cShort:
case cInt:
switch (oldTyClass) {
- case cLong:
+ case cLong:
// Treat it like a cast from the lower half of the value.
emitIntegerCast (BB, IP, Type::IntTy, SrcReg+1, newTy, DestReg);
break;
- case cFloat:
+ case cFloat:
case cDouble:
emitFPToIntegerCast (BB, IP, oldTy, SrcReg, newTy, DestReg);
break;
unsigned TempReg = emitIntegerCast (BB, IP, OldHalfTy, SrcReg,
NewHalfTy, DestReg+1, true);
if (newTy->isSigned ()) {
- BuildMI (*BB, IP, V8::SRAri, 2, DestReg).addReg (TempReg)
+ BuildMI (*BB, IP, V8::SRAri, 2, DestReg).addReg (TempReg)
.addZImm (31);
} else {
- BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0)
+ BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0)
.addReg (V8::G0);
}
break;
if (isa<ConstantIntegral> (idx)) {
// If idx is a constant, we don't have to emit the multiply.
int64_t Val = cast<ConstantIntegral> (idx)->getRawValue ();
- if ((Val * elementSize) + 4096 < 8191) {
+ if ((Val * elementSize) + 4096 < 8191) {
// (Val * elementSize) is constant and fits in an immediate field.
// emit: nextBasePtrReg = ADDri basePtrReg, (Val * elementSize)
addImmed = true;
OffsetReg = makeAnotherReg (Type::IntTy);
unsigned idxReg = getReg (idx, MBB, IP);
switch (elementSize) {
- case 1:
+ case 1:
BuildMI (*MBB, IP, V8::ORrr, 2, OffsetReg).addReg (V8::G0).addReg (idxReg);
break;
- case 2:
+ case 2:
BuildMI (*MBB, IP, V8::SLLri, 2, OffsetReg).addReg (idxReg).addZImm (1);
break;
- case 4:
+ case 4:
BuildMI (*MBB, IP, V8::SLLri, 2, OffsetReg).addReg (idxReg).addZImm (2);
break;
- case 8:
+ case 8:
BuildMI (*MBB, IP, V8::SLLri, 2, OffsetReg).addReg (idxReg).addZImm (3);
break;
default: {
// ba .lshr_continue
BB = oneShiftMBB;
-
+
if (isSigned)
BuildMI (BB, V8::SRAri, 2, OneShiftOutReg).addReg (SrcReg).addZImm (31);
else
}
switch (getClassB (I.getType ())) {
- case cByte:
+ case cByte:
if (I.getType ()->isSigned ()) { // add byte
BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
} else { // add ubyte
unsigned Op1Reg = getReg (I.getOperand (1));
unsigned DestReg = getReg (I);
const Type *Ty = I.getOperand (0)->getType ();
-
+
// Compare the two values.
if (getClass (Ty) < cLong) {
BuildMI(BB, V8::SUBCCrr, 2, V8::G0).addReg(Op0Reg).addReg(Op1Reg);
//===- SparcV8JITInfo.h - SparcV8 impl. of the JIT interface ----*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV8 implementation of the TargetJITInfo class.
/// is not supported for this target.
///
virtual void addPassesToJITCompile(FunctionPassManager &PM);
-
+
/// replaceMachineCodeForFunction - Make it so that calling the function
/// whose machine code is at OLD turns into a call to NEW, perhaps by
/// overwriting OLD with a branch to NEW. This is used for self-modifying
/// code.
///
virtual void replaceMachineCodeForFunction(void *Old, void *New);
-
+
/// getJITStubForFunction - Create or return a stub for the specified
/// function. This stub acts just like the specified function, except that
/// it allows the "address" of the function to be taken without having to
//===-- DelaySlotFiller.cpp - SparcV8 delay slot filler -------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This is a simple local pass that fills delay slots with NOPs.
//===-- FPMover.cpp - SparcV8 double-precision floating point move fixer --===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Turns FpMOVD instructions into FMOVS pairs after regalloc.
//===-- SparcV8.h - Top-level interface for SparcV8 representation -*- C++ -*-//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the entry points for global functions defined in the LLVM
//===-- SparcV8AsmPrinter.cpp - SparcV8 LLVM assembly writer --------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains a printer that converts from our internal representation
void printOperand(const MachineInstr *MI, int opNum);
void printBaseOffsetPair (const MachineInstr *MI, int i, bool brackets=true);
void printMachineInstruction(const MachineInstr *MI);
- bool runOnMachineFunction(MachineFunction &F);
+ bool runOnMachineFunction(MachineFunction &F);
bool doInitialization(Module &M);
bool doFinalization(Module &M);
};
// Print a constant value or values, with the appropriate storage class as a
// prefix.
-void V8Printer::emitGlobalConstant(const Constant *CV) {
+void V8Printer::emitGlobalConstant(const Constant *CV) {
const TargetData &TD = TM.getTargetData();
if (const ConstantArray *CVA = dyn_cast<ConstantArray>(CV)) {
// Insert the field padding unless it's zero bytes...
if (padSize)
- O << "\t.skip\t " << padSize << "\n";
+ O << "\t.skip\t " << padSize << "\n";
}
assert(sizeSoFar == cvsLayout->StructSize &&
"Layout of constant struct may be incorrect!");
}
} else if (isa<UndefValue> (CV)) {
unsigned size = TD.getTypeSize (CV->getType ());
- O << "\t.skip\t " << size << "\n";
+ O << "\t.skip\t " << size << "\n";
return;
} else if (isa<ConstantAggregateZero> (CV)) {
unsigned size = TD.getTypeSize (CV->getType ());
void V8Printer::printConstantPool(MachineConstantPool *MCP) {
const std::vector<Constant*> &CP = MCP->getConstants();
const TargetData &TD = TM.getTargetData();
-
+
if (CP.empty()) return;
for (unsigned i = 0, e = CP.size(); i != e; ++i) {
O << ".CPI" << CurrentFnName << "_" << MO.getConstantPoolIndex();
break;
default:
- O << "<unknown operand type>"; abort (); break;
+ O << "<unknown operand type>"; abort (); break;
}
if (CloseParen) O << ")";
}
O << "! ";
O << Desc.Name << " ";
-
+
// Printing memory instructions is a special case.
// for loads: %dest = op %base, offset --> op [%base + offset], %dest
// for stores: op %base, offset, %src --> op %src, [%base + offset]
for (unsigned i = 0; i < MI->getNumOperands (); ++i)
if (MI->getOperand (i).isRegister () && MI->getOperand (i).isDef ())
print_order.push_back (i);
- for (unsigned i = 0, e = print_order.size (); i != e; ++i) {
+ for (unsigned i = 0, e = print_order.size (); i != e; ++i) {
printOperand (MI, print_order[i]);
if (i != (print_order.size () - 1))
O << ", ";
unsigned Size = TD.getTypeSize(C->getType());
unsigned Align = TD.getTypeAlignment(C->getType());
- if (C->isNullValue() &&
+ if (C->isNullValue() &&
(I->hasLinkOnceLinkage() || I->hasInternalLinkage() ||
I->hasWeakLinkage() /* FIXME: Verify correct */)) {
SwitchSection(O, CurSection, ".data");
if (I->hasInternalLinkage())
O << "\t.local " << name << "\n";
-
+
O << "\t.comm " << name << "," << TD.getTypeSize(C->getType())
<< "," << (unsigned)TD.getTypeAlignment(C->getType());
O << "\t\t! ";
SwitchSection(O, CurSection, "");
O << "\t.section\t\".llvm.linkonce.d." << name << "\",\"aw\",@progbits\n";
break;
-
+
case GlobalValue::AppendingLinkage:
// FIXME: appending linkage variables should go into a section of
// their name or something. For now, just emit them as external.
//===-- SparcV8CodeEmitter.cpp - JIT Code Emitter for SparcV8 -----*- C++ -*-=//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
//
//===----------------------------------------------------------------------===//
MachineCodeEmitter &MCE) {
// Keep as `true' until this is a functional JIT to allow llvm-gcc to build
return true;
-
+
// Machine code emitter pass for SparcV8
PM.add(new SparcV8CodeEmitter(*this, MCE));
// Delete machine code for this function after emitting it
//===-- InstSelectSimple.cpp - A simple instruction selector for SparcV8 --===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file defines a simple peephole instruction selector for the V8 target
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm (0);
} else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
// Copy it with a SETHI/OR pair; the JIT + asmwriter should recognize
- // that SETHI %reg,global == SETHI %reg,%hi(global) and
+ // that SETHI %reg,global == SETHI %reg,%hi(global) and
// OR %reg,global,%reg == OR %reg,%lo(global),%reg.
unsigned TmpReg = makeAnotherReg (C->getType ());
BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addGlobalAddress(GV);
const unsigned *IAR = &IncomingArgRegs[0];
unsigned ArgOffset = 68;
- // Store registers onto stack if this is a varargs function.
+ // Store registers onto stack if this is a varargs function.
// FIXME: This doesn't really pertain to "loading arguments into
// virtual registers", so it's not clear that it really belongs here.
- // FIXME: We could avoid storing any args onto the stack that don't
+ // FIXME: We could avoid storing any args onto the stack that don't
// need to be in memory, because they come before the ellipsis in the
// parameter list (and thus could never be accessed through va_arg).
if (LF->getFunctionType ()->isVarArg ()) {
break;
}
assert (PredMBB && "Couldn't find incoming machine-cfg edge for phi");
-
+
unsigned ValReg;
std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
PHIValues.lower_bound(PredMBB);
// predecessor. Recycle it.
ValReg = EntryIt->second;
- } else {
+ } else {
// Get the incoming value into a virtual register.
//
Value *Val = PN->getIncomingValue(i);
// might be arbitrarily complex if it is a constant expression),
// just insert the computation at the top of the basic block.
MachineBasicBlock::iterator PI = PredMBB->begin();
-
+
// Skip over any PHI nodes though!
while (PI != PredMBB->end() && PI->getOpcode() == V8::PHI)
++PI;
-
+
ValReg = getReg(Val, PredMBB, PI);
}
// First pass over the function, lower any unknown intrinsic functions
// with the IntrinsicLowering class.
LowerUnknownIntrinsicFunctionCalls(Fn);
-
+
F = &MachineFunction::construct(&Fn, TM);
-
+
// Create all of the machine basic blocks for the function...
for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
-
+
BB = &F->front();
-
+
// Set up a frame object for the return address. This is used by the
// llvm.returnaddress & llvm.frameaddress intrinisics.
//ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
-
+
// Copy incoming arguments off of the stack and out of fixed registers.
LoadArgumentsToVirtualRegs(&Fn);
-
+
// Instruction select everything except PHI nodes
visit(Fn);
-
+
// Select the PHI nodes
SelectPHINodes();
-
+
RegMap.clear();
MBBMap.clear();
F = 0;
const Type *newTy, unsigned DestReg) {
unsigned FPCastOpcode, FPStoreOpcode, FPSize, FPAlign;
unsigned oldTyClass = getClassB(oldTy);
- if (oldTyClass == cFloat) {
- FPCastOpcode = V8::FSTOI; FPStoreOpcode = V8::STFri; FPSize = 4;
+ if (oldTyClass == cFloat) {
+ FPCastOpcode = V8::FSTOI; FPStoreOpcode = V8::STFri; FPSize = 4;
FPAlign = TM.getTargetData().getFloatAlignment();
} else { // it's a double
- FPCastOpcode = V8::FDTOI; FPStoreOpcode = V8::STDFri; FPSize = 8;
+ FPCastOpcode = V8::FDTOI; FPStoreOpcode = V8::STDFri; FPSize = 8;
FPAlign = TM.getTargetData().getDoubleAlignment();
}
unsigned TempReg = makeAnotherReg (oldTy);
case cShort:
case cInt:
switch (oldTyClass) {
- case cLong:
+ case cLong:
// Treat it like a cast from the lower half of the value.
emitIntegerCast (BB, IP, Type::IntTy, SrcReg+1, newTy, DestReg);
break;
- case cFloat:
+ case cFloat:
case cDouble:
emitFPToIntegerCast (BB, IP, oldTy, SrcReg, newTy, DestReg);
break;
unsigned TempReg = emitIntegerCast (BB, IP, OldHalfTy, SrcReg,
NewHalfTy, DestReg+1, true);
if (newTy->isSigned ()) {
- BuildMI (*BB, IP, V8::SRAri, 2, DestReg).addReg (TempReg)
+ BuildMI (*BB, IP, V8::SRAri, 2, DestReg).addReg (TempReg)
.addZImm (31);
} else {
- BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0)
+ BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0)
.addReg (V8::G0);
}
break;
if (isa<ConstantIntegral> (idx)) {
// If idx is a constant, we don't have to emit the multiply.
int64_t Val = cast<ConstantIntegral> (idx)->getRawValue ();
- if ((Val * elementSize) + 4096 < 8191) {
+ if ((Val * elementSize) + 4096 < 8191) {
// (Val * elementSize) is constant and fits in an immediate field.
// emit: nextBasePtrReg = ADDri basePtrReg, (Val * elementSize)
addImmed = true;
OffsetReg = makeAnotherReg (Type::IntTy);
unsigned idxReg = getReg (idx, MBB, IP);
switch (elementSize) {
- case 1:
+ case 1:
BuildMI (*MBB, IP, V8::ORrr, 2, OffsetReg).addReg (V8::G0).addReg (idxReg);
break;
- case 2:
+ case 2:
BuildMI (*MBB, IP, V8::SLLri, 2, OffsetReg).addReg (idxReg).addZImm (1);
break;
- case 4:
+ case 4:
BuildMI (*MBB, IP, V8::SLLri, 2, OffsetReg).addReg (idxReg).addZImm (2);
break;
- case 8:
+ case 8:
BuildMI (*MBB, IP, V8::SLLri, 2, OffsetReg).addReg (idxReg).addZImm (3);
break;
default: {
// ba .lshr_continue
BB = oneShiftMBB;
-
+
if (isSigned)
BuildMI (BB, V8::SRAri, 2, OneShiftOutReg).addReg (SrcReg).addZImm (31);
else
}
switch (getClassB (I.getType ())) {
- case cByte:
+ case cByte:
if (I.getType ()->isSigned ()) { // add byte
BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
} else { // add ubyte
unsigned Op1Reg = getReg (I.getOperand (1));
unsigned DestReg = getReg (I);
const Type *Ty = I.getOperand (0)->getType ();
-
+
// Compare the two values.
if (getClass (Ty) < cLong) {
BuildMI(BB, V8::SUBCCrr, 2, V8::G0).addReg(Op0Reg).addReg(Op1Reg);
//===- SparcV8InstrInfo.cpp - SparcV8 Instruction Information ---*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV8 implementation of the TargetInstrInfo class.
//===- SparcV8InstrInfo.h - SparcV8 Instruction Information -----*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV8 implementation of the TargetInstrInfo class.
//===- SparcV8JITInfo.h - SparcV8 impl. of the JIT interface ----*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV8 implementation of the TargetJITInfo class.
/// is not supported for this target.
///
virtual void addPassesToJITCompile(FunctionPassManager &PM);
-
+
/// replaceMachineCodeForFunction - Make it so that calling the function
/// whose machine code is at OLD turns into a call to NEW, perhaps by
/// overwriting OLD with a branch to NEW. This is used for self-modifying
/// code.
///
virtual void replaceMachineCodeForFunction(void *Old, void *New);
-
+
/// getJITStubForFunction - Create or return a stub for the specified
/// function. This stub acts just like the specified function, except that
/// it allows the "address" of the function to be taken without having to
//===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV8 implementation of the MRegisterInfo class.
const TargetRegisterClass *RC = getClass(SrcReg);
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
- if (RC == SparcV8::IntRegsRegisterClass)
+ if (RC == SparcV8::IntRegsRegisterClass)
BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0)
.addReg (SrcReg);
else if (RC == SparcV8::FPRegsRegisterClass)
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, int FrameIdx) const {
const TargetRegisterClass *RC = getClass(DestReg);
- if (RC == SparcV8::IntRegsRegisterClass)
+ if (RC == SparcV8::IntRegsRegisterClass)
BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
else if (RC == SparcV8::FPRegsRegisterClass)
BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx)
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const {
- if (RC == SparcV8::IntRegsRegisterClass)
+ if (RC == SparcV8::IntRegsRegisterClass)
BuildMI (MBB, I, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
else if (RC == SparcV8::FPRegsRegisterClass)
BuildMI (MBB, I, V8::FMOVS, 1, DestReg).addReg (SrcReg);
//===- SparcV8RegisterInfo.h - SparcV8 Register Information Impl -*- C++ -*-==//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV8 implementation of the MRegisterInfo class.
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex) const;
-
+
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
//===-- SparcV8TargetMachine.cpp - Define TargetMachine for SparcV8 -------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
//
//===----------------------------------------------------------------------===//
// Print LLVM code input to instruction selector:
if (PrintMachineCode)
PM.add(new PrintFunctionPass());
-
+
PM.add(createSparcV8SimpleInstructionSelector(*this));
// Print machine instructions as they were initially generated.
// Replace malloc and free instructions with library calls.
PM.add(createLowerAllocationsPass());
-
+
// FIXME: implement the switch instruction in the instruction selector.
PM.add(createLowerSwitchPass());
PM.add(createLowerInvokePass());
PM.add(createLowerConstantExpressionsPass());
-
+
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
// FIXME: implement the select instruction in the instruction selector.
PM.add(createLowerSelectPass());
-
+
// Print LLVM code input to instruction selector:
if (PrintMachineCode)
PM.add(new PrintFunctionPass());
-
+
PM.add(createSparcV8SimpleInstructionSelector(TM));
// Print machine instructions as they were initially generated.
//===-- SparcV8TargetMachine.h - Define TargetMachine for SparcV8 -*- C++ -*-=//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file declares the SparcV8 specific subclass of TargetMachine.
//
//===----------------------------------------------------------------------===//
///
virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
MachineCodeEmitter &MCE);
-
+
virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
};
//===- llvm/Transforms/DecomposeMultiDimRefs.cpp - Lower array refs to 1D -===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// DecomposeMultiDimRefs - Convert multi-dimensional references consisting of
}
// Function: DecomposeArrayRef()
-//
+//
// For any GetElementPtrInst with 2 or more array and structure indices:
-//
+//
// opCode CompositeType* P, [uint|ubyte] idx1, ..., [uint|ubyte] idxN
-//
+//
// this function generates the following sequence:
-//
+//
// ptr1 = getElementPtr P, idx1
// ptr2 = getElementPtr ptr1, 0, idx2
// ...
// ptrN-1 = getElementPtr ptrN-2, 0, idxN-1
// opCode ptrN-1, 0, idxN // New-MAI
-//
+//
// Then it replaces the original instruction with this sequence,
// and replaces all uses of the original instruction with New-MAI.
// If idx1 is 0, we simply omit the first getElementPtr instruction.
-//
+//
// On return: BBI points to the instruction after the current one
// (whether or not *BBI was replaced).
-//
+//
// Return value: true if the instruction was replaced; false otherwise.
-//
+//
bool llvm::DecomposeArrayRef(GetElementPtrInst* GEP) {
if (GEP->getNumIndices() < 2
|| (GEP->getNumIndices() == 2
User::const_op_iterator OI = GEP->idx_begin(), OE = GEP->idx_end();
for (; OI+1 != OE; ++OI) {
std::vector<Value*> Indices;
-
+
// If this is the first index and is 0, skip it and move on!
if (OI == GEP->idx_begin()) {
if (isZeroConst (*OI))
//===-- EmitBytecodeToAssembly.cpp - Emit bytecode to SparcV9 .s File ------==//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file implements the pass that writes LLVM bytecode as data to a sparc
typedef int int_type;
typedef std::streampos pos_type;
typedef std::streamoff off_type;
-
+
sparcasmbuf(std::ostream &On) : BaseStr(On) {}
virtual int_type overflow(int_type C) {
const std::string &symName) {
// Prologue:
// Output a comment describing the object.
- Out << "!" << comment << "\n";
+ Out << "!" << comment << "\n";
// Switch the current section to .rodata in the assembly output:
- Out << "\t.section \".rodata\"\n\t.align 8\n";
+ Out << "\t.section \".rodata\"\n\t.align 8\n";
// Output a global symbol naming the object:
- Out << "\t.global " << symName << "\n";
- Out << "\t.type " << symName << ",#object\n";
- Out << symName << ":\n";
+ Out << "\t.global " << symName << "\n";
+ Out << "\t.type " << symName << ",#object\n";
+ Out << symName << ":\n";
}
static void writeEpilogue (std::ostream &Out, const std::string &symName) {
// Epilogue:
// Output a local symbol marking the end of the object:
- Out << ".end_" << symName << ":\n";
+ Out << ".end_" << symName << ":\n";
// Output size directive giving the size of the object:
Out << "\t.size " << symName << ", .end_" << symName << "-" << symName
<< "\n";
SparcV9BytecodeWriter(std::ostream &out) : Out(out) {}
const char *getPassName() const { return "Emit Bytecode to SparcV9 Assembly";}
-
+
virtual bool runOnModule(Module &M) {
// Write an object containing the bytecode to the SPARC assembly stream
writePrologue (Out, "LLVM BYTECODE OUTPUT", "LLVMBytecode");
// Write an object containing its length as an integer to the
// SPARC assembly stream
writePrologue (Out, "LLVM BYTECODE LENGTH", "llvm_length");
- Out <<"\t.word\t.end_LLVMBytecode-LLVMBytecode\n";
+ Out <<"\t.word\t.end_LLVMBytecode-LLVMBytecode\n";
writeEpilogue (Out, "llvm_length");
return false;
//===- InstrScheduling.cpp - Generic Instruction Scheduling support -------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file implements the llvm/CodeGen/InstrScheduling.h interface, along with
//----------------------------------------------------------------------
// class InstrGroup:
-//
+//
// Represents a group of instructions scheduled to be issued
// in a single cycle.
//----------------------------------------------------------------------
class InstrGroup {
InstrGroup(const InstrGroup&); // DO NOT IMPLEMENT
void operator=(const InstrGroup&); // DO NOT IMPLEMENT
-
+
public:
inline const SchedGraphNode* operator[](unsigned int slotNum) const {
assert(slotNum < group.size());
return group[slotNum];
}
-
+
private:
friend class InstrSchedule;
-
+
inline void addInstr(const SchedGraphNode* node, unsigned int slotNum) {
assert(slotNum < group.size());
group[slotNum] = node;
}
-
+
/*ctor*/ InstrGroup(unsigned int nslots)
: group(nslots, NULL) {}
-
+
/*ctor*/ InstrGroup(); // disable: DO NOT IMPLEMENT
-
+
private:
std::vector<const SchedGraphNode*> group;
};
//----------------------------------------------------------------------
// class ScheduleIterator:
-//
+//
// Iterates over the machine instructions in the for a single basic block.
// The schedule is represented by an InstrSchedule object.
//----------------------------------------------------------------------
const InstrSchedule& S;
public:
typedef ScheduleIterator<_NodeType> _Self;
-
+
/*ctor*/ inline ScheduleIterator(const InstrSchedule& _schedule,
unsigned _cycleNum,
unsigned _slotNum)
: cycleNum(_cycleNum), slotNum(_slotNum), S(_schedule) {
- skipToNextInstr();
+ skipToNextInstr();
}
-
+
/*ctor*/ inline ScheduleIterator(const _Self& x)
: cycleNum(x.cycleNum), slotNum(x.slotNum), S(x.S) {}
-
+
inline bool operator==(const _Self& x) const {
return (slotNum == x.slotNum && cycleNum== x.cycleNum && &S==&x.S);
}
-
+
inline bool operator!=(const _Self& x) const { return !operator==(x); }
-
+
inline _NodeType* operator*() const;
inline _NodeType* operator->() const { return operator*(); }
-
+
_Self& operator++(); // Preincrement
inline _Self operator++(int) { // Postincrement
- _Self tmp(*this); ++*this; return tmp;
+ _Self tmp(*this); ++*this; return tmp;
}
-
+
static _Self begin(const InstrSchedule& _schedule);
static _Self end( const InstrSchedule& _schedule);
-
+
private:
inline _Self& operator=(const _Self& x); // DISABLE -- DO NOT IMPLEMENT
void skipToNextInstr();
//----------------------------------------------------------------------
// class InstrSchedule:
-//
+//
// Represents the schedule of machine instructions for a single basic block.
//----------------------------------------------------------------------
InstrSchedule(InstrSchedule&); // DO NOT IMPLEMENT
void operator=(InstrSchedule&); // DO NOT IMPLEMENT
-
+
public: // iterators
typedef ScheduleIterator<SchedGraphNode> iterator;
typedef ScheduleIterator<const SchedGraphNode> const_iterator;
-
+
iterator begin() { return iterator::begin(*this); }
const_iterator begin() const { return const_iterator::begin(*this); }
iterator end() { return iterator::end(*this); }
const_iterator end() const { return const_iterator::end(*this); }
-
+
public: // constructors and destructor
/*ctor*/ InstrSchedule (unsigned int _nslots,
unsigned int _numNodes);
/*dtor*/ ~InstrSchedule ();
-
+
public: // accessor functions to query chosen schedule
const SchedGraphNode* getInstr (unsigned int slotNum,
CycleCount_t c) {
const InstrGroup* igroup = this->getIGroup(c);
return (igroup == NULL)? NULL : (*igroup)[slotNum];
}
-
+
inline InstrGroup* getIGroup (CycleCount_t c) {
if ((unsigned)c >= groups.size())
groups.resize(c+1);
groups[c] = new InstrGroup(nslots);
return groups[c];
}
-
+
inline const InstrGroup* getIGroup (CycleCount_t c) const {
assert((unsigned)c < groups.size());
return groups[c];
}
-
+
inline CycleCount_t getStartTime (unsigned int nodeId) const {
assert(nodeId < startTime.size());
return startTime[nodeId];
}
-
+
unsigned int getNumInstructions() const {
return numInstr;
}
-
+
inline void scheduleInstr (const SchedGraphNode* node,
unsigned int slotNum,
CycleCount_t cycle) {
startTime[node->getNodeId()] = cycle;
++numInstr;
}
-
+
private:
friend class ScheduleIterator<SchedGraphNode>;
friend class ScheduleIterator<const SchedGraphNode>;
template<class _NodeType>
-inline
+inline
void
ScheduleIterator<_NodeType>::skipToNextInstr()
{
while(cycleNum < S.groups.size() && S.groups[cycleNum] == NULL)
++cycleNum; // skip cycles with no instructions
-
+
while (cycleNum < S.groups.size() &&
(*S.groups[cycleNum])[slotNum] == NULL)
{
}
template<class _NodeType>
-inline
+inline
ScheduleIterator<_NodeType>&
ScheduleIterator<_NodeType>::operator++() // Preincrement
{
++cycleNum;
slotNum = 0;
}
- skipToNextInstr();
+ skipToNextInstr();
return *this;
}
//----------------------------------------------------------------------
// class DelaySlotInfo:
-//
+//
// Record information about delay slots for a single branch instruction.
// Delay slots are simply indexed by slot number 1 ... numDelaySlots
//----------------------------------------------------------------------
std::vector<const SchedGraphNode*> delayNodeVec;
CycleCount_t delayedNodeCycle;
unsigned delayedNodeSlotNum;
-
+
DelaySlotInfo(const DelaySlotInfo &); // DO NOT IMPLEMENT
void operator=(const DelaySlotInfo&); // DO NOT IMPLEMENT
public:
unsigned _ndelays)
: brNode(_brNode), ndelays(_ndelays),
delayedNodeCycle(0), delayedNodeSlotNum(0) {}
-
+
inline unsigned getNumDelays () {
return ndelays;
}
-
+
inline const std::vector<const SchedGraphNode*>& getDelayNodeVec() {
return delayNodeVec;
}
-
+
inline void addDelayNode (const SchedGraphNode* node) {
delayNodeVec.push_back(node);
assert(delayNodeVec.size() <= ndelays && "Too many delay slot instrs!");
}
-
+
inline void recordChosenSlot (CycleCount_t cycle, unsigned slotNum) {
delayedNodeCycle = cycle;
delayedNodeSlotNum = slotNum;
}
-
+
unsigned scheduleDelayedNode (SchedulingManager& S);
};
//----------------------------------------------------------------------
// class SchedulingManager:
-//
+//
// Represents the schedule of machine instructions for a single basic block.
//----------------------------------------------------------------------
const TargetSchedInfo& schedInfo;
SchedPriorities& schedPrio;
InstrSchedule isched;
-
+
private:
unsigned totalInstrCount;
CycleCount_t curTime;
std::vector<int> numInClass; // indexed by sched class
std::vector<CycleCount_t> nextEarliestStartTime; // indexed by opCode
hash_map<const SchedGraphNode*, DelaySlotInfo*> delaySlotInfoForBranches;
- // indexed by branch node ptr
-
+ // indexed by branch node ptr
+
public:
SchedulingManager(const TargetMachine& _target, const SchedGraph* graph,
SchedPriorities& schedPrio);
E = delaySlotInfoForBranches.end(); I != E; ++I)
delete I->second;
}
-
+
//----------------------------------------------------------------------
// Simplify access to the machine instruction info
//----------------------------------------------------------------------
-
+
inline const TargetInstrInfo& getInstrInfo () const {
return schedInfo.getInstrInfo();
}
-
+
//----------------------------------------------------------------------
// Interface for checking and updating the current time
//----------------------------------------------------------------------
-
+
inline CycleCount_t getTime () const {
return curTime;
}
-
+
inline CycleCount_t getEarliestIssueTime() const {
return nextEarliestIssueTime;
}
-
+
inline CycleCount_t getEarliestStartTimeForOp(MachineOpCode opCode) const {
assert(opCode < (int) nextEarliestStartTime.size());
return nextEarliestStartTime[opCode];
}
-
+
// Update current time to specified cycle
inline void updateTime (CycleCount_t c) {
curTime = c;
schedPrio.updateTime(c);
}
-
+
//----------------------------------------------------------------------
// Functions to manage the choices for the current cycle including:
// -- a vector of choices by priority (choiceVec)
// -- number of choices in each sched class, used to check issue conflicts
// between choices for a single cycle
//----------------------------------------------------------------------
-
+
inline unsigned int getNumChoices () const {
return choiceVec.size();
}
-
+
inline unsigned getNumChoicesInClass (const InstrSchedClass& sc) const {
assert(sc < numInClass.size() && "Invalid op code or sched class!");
return numInClass[sc];
}
-
+
inline const SchedGraphNode* getChoice(unsigned int i) const {
// assert(i < choiceVec.size()); don't check here.
return choiceVec[i];
}
-
+
inline hash_set<const SchedGraphNode*>& getChoicesForSlot(unsigned slotNum) {
assert(slotNum < nslots);
return choicesForSlot[slotNum];
}
-
+
inline void addChoice (const SchedGraphNode* node) {
// Append the instruction to the vector of choices for current cycle.
// Increment numInClass[c] for the sched class to which the instr belongs.
assert(sc < numInClass.size());
numInClass[sc]++;
}
-
+
inline void addChoiceToSlot (unsigned int slotNum,
const SchedGraphNode* node) {
// Add the instruction to the choice set for the specified slot
assert(slotNum < nslots);
choicesForSlot[slotNum].insert(node);
}
-
+
inline void resetChoices () {
choiceVec.clear();
for (unsigned int s=0; s < nslots; s++)
for (unsigned int c=0; c < numInClass.size(); c++)
numInClass[c] = 0;
}
-
+
//----------------------------------------------------------------------
// Code to query and manage the partial instruction schedule so far
//----------------------------------------------------------------------
-
+
inline unsigned int getNumScheduled () const {
return isched.getNumInstructions();
}
-
+
inline unsigned int getNumUnscheduled() const {
return totalInstrCount - isched.getNumInstructions();
}
-
+
inline bool isScheduled (const SchedGraphNode* node) const {
return (isched.getStartTime(node->getNodeId()) >= 0);
}
-
+
inline void scheduleInstr (const SchedGraphNode* node,
unsigned int slotNum,
CycleCount_t cycle)
{
assert(! isScheduled(node) && "Instruction already scheduled?");
-
+
// add the instruction to the schedule
isched.scheduleInstr(node, slotNum, cycle);
-
+
// update the earliest start times of all nodes that conflict with `node'
// and the next-earliest time anything can issue if `node' causes bubbles
updateEarliestStartTimes(node, cycle);
-
+
// remove the instruction from the choice sets for all slots
for (unsigned s=0; s < nslots; s++)
choicesForSlot[s].erase(node);
-
+
// and decrement the instr count for the sched class to which it belongs
const InstrSchedClass& sc = schedInfo.getSchedClass(node->getOpcode());
assert(sc < numInClass.size());
//----------------------------------------------------------------------
// Create and retrieve delay slot info for delayed instructions
//----------------------------------------------------------------------
-
+
inline DelaySlotInfo* getDelaySlotInfoForInstr(const SchedGraphNode* bn,
bool createIfMissing=false)
{
new DelaySlotInfo(bn, getInstrInfo().getNumDelaySlots(bn->getOpcode()));
return delaySlotInfoForBranches[bn] = dinfo;
}
-
+
private:
SchedulingManager(); // DISABLED: DO NOT IMPLEMENT
void updateEarliestStartTimes(const SchedGraphNode* node, CycleCount_t schedTime);
(CycleCount_t) 0) // set all to 0
{
updateTime(0);
-
+
// Note that an upper bound on #choices for each slot is = nslots since
// we use this vector to hold a feasible set of instructions, and more
// would be infeasible. Reserve that much memory since it is probably small.
nextEarliestIssueTime = std::max(nextEarliestIssueTime,
curTime + 1 + schedInfo.numBubblesAfter(node->getOpcode()));
}
-
+
const std::vector<MachineOpCode>&
conflictVec = schedInfo.getConflictList(node->getOpcode());
-
+
for (unsigned i=0; i < conflictVec.size(); i++)
{
MachineOpCode toOp = conflictVec[i];
// find the slot to start from, in the current cycle
unsigned int startSlot = 0;
CycleCount_t curTime = S.getTime();
-
+
assert(maxIssue > 0 && maxIssue <= S.nslots - startSlot);
-
+
// If only one instruction can be issued, do so.
if (maxIssue == 1)
for (unsigned s=startSlot; s < S.nslots; s++)
S.scheduleInstr(*S.getChoicesForSlot(s).begin(), s, curTime);
return;
}
-
+
// Otherwise, choose from the choices for each slot
- //
+ //
InstrGroup* igroup = S.isched.getIGroup(S.getTime());
assert(igroup != NULL && "Group creation failed?");
-
+
// Find a slot that has only a single choice, and take it.
// If all slots have 0 or multiple choices, pick the first slot with
// choices and use its last instruction (just to avoid shifting the vector).
chosenSlot = (int) s;
break;
}
-
+
if (chosenSlot == -1)
for (unsigned s=startSlot; s < S.nslots; s++)
if ((*igroup)[s] == NULL && S.getChoicesForSlot(s).size() > 0) {
chosenSlot = (int) s;
break;
}
-
+
if (chosenSlot != -1) {
// Insert the chosen instr in the chosen slot and
// erase it from all slots.
S.scheduleInstr(node, chosenSlot, curTime);
}
}
-
+
assert(numIssued > 0 && "Should not happen when maxIssue > 0!");
}
-//
+//
// For now, just assume we are scheduling within a single basic block.
// Get the machine instruction vector for the basic block and clear it,
// then append instructions in scheduled order.
// Also, re-insert the dummy PHI instructions that were at the beginning
// of the basic block, since they are not part of the schedule.
-//
+//
static void
RecordSchedule(MachineBasicBlock &MBB, const SchedulingManager& S)
{
const TargetInstrInfo& mii = S.schedInfo.getInstrInfo();
-
+
// Lets make sure we didn't lose any instructions, except possibly
// some NOPs from delay slots. Also, PHIs are not included in the schedule.
unsigned numInstr = 0;
++numInstr;
assert(S.isched.getNumInstructions() >= numInstr &&
"Lost some non-NOP instructions during scheduling!");
-
+
if (S.isched.getNumInstructions() == 0)
return; // empty basic block!
-
+
// First find the dummy instructions at the start of the basic block
MachineBasicBlock::iterator I = MBB.begin();
for ( ; I != MBB.end(); ++I)
if (I->getOpcode() != V9::PHI)
break;
-
+
// Remove all except the dummy PHI instructions from MBB, and
// pre-allocate create space for the ones we will put back in.
while (I != MBB.end())
MBB.remove(I++);
-
+
InstrSchedule::const_iterator NIend = S.isched.end();
for (InstrSchedule::const_iterator NI = S.isched.begin(); NI != NIend; ++NI)
MBB.push_back(const_cast<MachineInstr*>((*NI)->getMachineInstr()));
{
// Check if any successors are now ready that were not already marked
// ready before, and that have not yet been scheduled.
- //
+ //
for (sg_succ_const_iterator SI = succ_begin(node); SI !=succ_end(node); ++SI)
if (! (*SI)->isDummyNode()
&& ! S.isScheduled(*SI)
// instruction to all possible slots that do not violate feasibility.
// FEASIBLE means it should be guaranteed that the set
// of chosen instructions can be issued in a single group.
-//
+//
// Return value:
// maxIssue : total number of feasible instructions
// S.choicesForSlot[i=0..nslots] : set of instructions feasible in slot i
-//
+//
static unsigned
FindSlotChoices(SchedulingManager& S,
DelaySlotInfo*& getDelaySlotInfo)
{
// initialize result vectors to empty
S.resetChoices();
-
+
// find the slot to start from, in the current cycle
unsigned int startSlot = 0;
InstrGroup* igroup = S.isched.getIGroup(S.getTime());
startSlot = s+1;
break;
}
-
+
// Make sure we pick at most one instruction that would break the group.
// Also, if we do pick one, remember which it was.
unsigned int indexForBreakingNode = S.nslots;
DelaySlotInfo* delaySlotInfo = NULL;
getDelaySlotInfo = NULL;
-
+
// Choose instructions in order of priority.
// Add choices to the choice vector in the SchedulingManager class as
// we choose them so that subsequent choices will be correctly tested
// for feasibility, w.r.t. higher priority choices for the same cycle.
- //
+ //
while (S.getNumChoices() < S.nslots - startSlot) {
const SchedGraphNode* nextNode=S.schedPrio.getNextHighest(S,S.getTime());
if (nextNode == NULL)
break; // no more instructions for this cycle
-
+
if (S.getInstrInfo().getNumDelaySlots(nextNode->getOpcode()) > 0) {
delaySlotInfo = S.getDelaySlotInfoForInstr(nextNode);
if (delaySlotInfo != NULL) {
else
indexForBreakingNode = S.getNumChoices();
}
-
+
if (nextNode != NULL) {
S.addChoice(nextNode);
-
+
if (S.schedInfo.isSingleIssue(nextNode->getOpcode())) {
assert(S.getNumChoices() == 1 &&
"Prioritizer returned invalid instr for this cycle!");
break;
}
}
-
+
if (indexForDelayedInstr < S.nslots)
break; // leave the rest for delay slots
}
-
+
assert(S.getNumChoices() <= S.nslots);
assert(! (indexForDelayedInstr < S.nslots &&
indexForBreakingNode < S.nslots) && "Cannot have both in a cycle");
-
+
// Assign each chosen instruction to all possible slots for that instr.
// But if only one instruction was chosen, put it only in the first
// feasible slot; no more analysis will be needed.
- //
- if (indexForDelayedInstr >= S.nslots &&
+ //
+ if (indexForDelayedInstr >= S.nslots &&
indexForBreakingNode >= S.nslots)
{ // No instructions that break the issue group or that have delay slots.
// This is the common case, so handle it separately for efficiency.
-
+
if (S.getNumChoices() == 1) {
MachineOpCode opCode = S.getChoice(0)->getOpcode();
unsigned int s;
// Try to assign that instruction to a higher slot than any other
// instructions in the group, so that its delay slots can go
// right after it.
- //
+ //
assert(indexForDelayedInstr == S.getNumChoices() - 1 &&
"Instruction with delay slots should be last choice!");
assert(delaySlotInfo != NULL && "No delay slot info for instr?");
-
+
const SchedGraphNode* delayedNode = S.getChoice(indexForDelayedInstr);
MachineOpCode delayOpCode = delayedNode->getOpcode();
unsigned ndelays= S.getInstrInfo().getNumDelaySlots(delayOpCode);
-
+
unsigned delayedNodeSlot = S.nslots;
int highestSlotUsed;
-
+
// Find the last possible slot for the delayed instruction that leaves
// at least `d' slots vacant after it (d = #delay slots)
for (int s = S.nslots-ndelays-1; s >= (int) startSlot; s--)
delayedNodeSlot = s;
break;
}
-
+
highestSlotUsed = -1;
for (unsigned i=0; i < S.getNumChoices() - 1; i++) {
// Try to assign every other instruction to a lower numbered
S.addChoiceToSlot(s, S.getChoice(i));
noSlotFound = false;
}
-
+
// No slot before `delayedNodeSlot' was found for this opCode
// Use a later slot, and allow some delay slots to fall in
// the next cycle.
S.addChoiceToSlot(s, S.getChoice(i));
break;
}
-
+
assert(s < S.nslots && "No feasible slot for instruction?");
-
+
highestSlotUsed = std::max(highestSlotUsed, (int) s);
}
-
+
assert(highestSlotUsed <= (int) S.nslots-1 && "Invalid slot used?");
-
+
// We will put the delayed node in the first slot after the
// highest slot used. But we just mark that for now, and
// schedule it separately because we want to schedule the delay
const SchedGraphNode* breakingNode=S.getChoice(indexForBreakingNode);
unsigned breakingSlot = INT_MAX;
unsigned int nslotsToUse = S.nslots;
-
+
// Find the last possible slot for this instruction.
for (int s = S.nslots-1; s >= (int) startSlot; s--)
if (S.schedInfo.instrCanUseSlot(breakingNode->getOpcode(), s)) {
}
assert(breakingSlot < S.nslots &&
"No feasible slot for `breakingNode'?");
-
+
// Higher priority instructions than the one that breaks the group:
// These can be assigned to all slots, but will be assigned only
// to earlier slots if possible.
i < S.getNumChoices() && i < indexForBreakingNode; i++)
{
MachineOpCode opCode =S.getChoice(i)->getOpcode();
-
+
// If a higher priority instruction cannot be assigned to
// any earlier slots, don't schedule the breaking instruction.
- //
+ //
bool foundLowerSlot = false;
nslotsToUse = S.nslots; // May be modified in the loop
for (unsigned int s=startSlot; s < nslotsToUse; s++)
foundLowerSlot = true;
nslotsToUse = breakingSlot; // RESETS LOOP UPPER BOUND!
}
-
+
S.addChoiceToSlot(s, S.getChoice(i));
}
-
+
if (!foundLowerSlot)
breakingSlot = INT_MAX; // disable breaking instr
}
-
+
// Assign the breaking instruction (if any) to a single slot
// Otherwise, just ignore the instruction. It will simply be
// scheduled in a later cycle.
nslotsToUse = breakingSlot;
} else
nslotsToUse = S.nslots;
-
+
// For lower priority instructions than the one that breaks the
// group, only assign them to slots lower than the breaking slot.
// Otherwise, just ignore the instruction.
S.addChoiceToSlot(s, S.getChoice(i));
}
} // endif (no delay slots and no breaking slots)
-
+
return S.getNumChoices();
}
{
assert(S.schedPrio.getNumReady() > 0
&& "Don't get here without ready instructions.");
-
+
CycleCount_t firstCycle = S.getTime();
DelaySlotInfo* getDelaySlotInfo = NULL;
-
+
// Choose up to `nslots' feasible instructions and their possible slots.
unsigned numIssued = FindSlotChoices(S, getDelaySlotInfo);
-
+
while (numIssued == 0) {
S.updateTime(S.getTime()+1);
numIssued = FindSlotChoices(S, getDelaySlotInfo);
}
-
+
AssignInstructionsToSlots(S, numIssued);
-
+
if (getDelaySlotInfo != NULL)
- numIssued += getDelaySlotInfo->scheduleDelayedNode(S);
-
+ numIssued += getDelaySlotInfo->scheduleDelayedNode(S);
+
// Print trace of scheduled instructions before newly ready ones
if (SchedDebugLevel >= Sched_PrintSchedTrace) {
for (CycleCount_t c = firstCycle; c <= S.getTime(); c++) {
}
}
}
-
+
return numIssued;
}
{
unsigned N;
const SchedGraphNode* node;
-
+
S.schedPrio.initialize();
-
+
while ((N = S.schedPrio.getNumReady()) > 0) {
CycleCount_t nextCycle = S.getTime();
-
+
// Choose one group of instructions for a cycle, plus any delay slot
// instructions (which may overflow into successive cycles).
// This will advance S.getTime() to the last cycle in which
// instructions are actually issued.
- //
+ //
unsigned numIssued = ChooseOneGroup(S);
assert(numIssued > 0 && "Deadlock in list scheduling algorithm?");
-
+
// Notify the priority manager of scheduled instructions and mark
// any successors that may now be ready
- //
+ //
for (CycleCount_t c = nextCycle; c <= S.getTime(); c++) {
const InstrGroup* igroup = S.isched.getIGroup(c);
for (unsigned int s=0; s < S.nslots; s++)
MarkSuccessorsReady(S, node);
}
}
-
+
// Move to the next the next earliest cycle for which
// an instruction can be issued, or the next earliest in which
// one will be ready, or to the next cycle, whichever is latest.
- //
+ //
S.updateTime(std::max(S.getTime() + 1,
std::max(S.getEarliestIssueTime(),
S.schedPrio.getEarliestReadyTime())));
bool nodeIsPredecessor)
{
assert(! node->isDummyNode());
-
+
// don't put a branch in the delay slot of another branch
if (S.getInstrInfo().isBranch(node->getOpcode()))
return false;
-
+
// don't put a single-issue instruction in the delay slot of a branch
if (S.schedInfo.isSingleIssue(node->getOpcode()))
return false;
-
+
// don't put a load-use dependence in the delay slot of a branch
const TargetInstrInfo& mii = S.getInstrInfo();
-
+
for (SchedGraphNode::const_iterator EI = node->beginInEdges();
EI != node->endInEdges(); ++EI)
if (! ((SchedGraphNode*)(*EI)->getSrc())->isDummyNode()
&& mii.isLoad(((SchedGraphNode*)(*EI)->getSrc())->getOpcode())
&& (*EI)->getDepType() == SchedGraphEdge::CtrlDep)
return false;
-
+
// Finally, if the instruction precedes the branch, we make sure the
// instruction can be reordered relative to the branch. We simply check
// if the instr. has only 1 outgoing edge, viz., a CD edge to the branch.
- //
+ //
if (nodeIsPredecessor) {
bool onlyCDEdgeToBranch = true;
for (SchedGraphNode::const_iterator OEI = node->beginOutEdges();
onlyCDEdgeToBranch = false;
break;
}
-
+
if (!onlyCDEdgeToBranch)
return false;
}
-
+
return true;
}
// remove it and all its incident edges from the graph. Make sure we
// add dummy edges for pred/succ nodes that become entry/exit nodes.
graph->eraseIncidentEdges(node, /*addDummyEdges*/ true);
- } else {
+ } else {
// If the node was from a target block, add the node to the graph
// and add a CD edge from brNode to node.
assert(0 && "NOT IMPLEMENTED YET");
}
-
+
DelaySlotInfo* dinfo = S.getDelaySlotInfoForInstr(brNode, /*create*/ true);
dinfo->addDelayNode(node);
}
const TargetInstrInfo& mii = S.getInstrInfo();
unsigned ndelays =
mii.getNumDelaySlots(brNode->getOpcode());
-
+
if (ndelays == 0)
return;
-
+
sdelayNodeVec.reserve(ndelays);
-
+
// Use a separate vector to hold the feasible multi-cycle nodes.
// These will be used if not enough single-cycle nodes are found.
- //
+ //
std::vector<SchedGraphNode*> mdelayNodeVec;
-
+
for (sg_pred_iterator P = pred_begin(brNode);
P != pred_end(brNode) && sdelayNodeVec.size() < ndelays; ++P)
if (! (*P)->isDummyNode() &&
else
sdelayNodeVec.push_back(*P);
}
-
+
// If not enough single-cycle instructions were found, select the
// lowest-latency multi-cycle instructions and use them.
// Note that this is the most efficient code when only 1 (or even 2)
// values need to be selected.
- //
+ //
while (sdelayNodeVec.size() < ndelays && mdelayNodeVec.size() > 0) {
unsigned lmin =
mii.maxLatency(mdelayNodeVec[0]->getOpcode());
unsigned minIndex = 0;
for (unsigned i=1; i < mdelayNodeVec.size(); i++)
{
- unsigned li =
+ unsigned li =
mii.maxLatency(mdelayNodeVec[i]->getOpcode());
if (lmin >= li)
{
// Mark instructions specified in sdelayNodeVec to replace them.
// If not enough useful instructions were found, mark the NOPs to be used
// for filling delay slots, otherwise, otherwise just discard them.
-//
+//
static void ReplaceNopsWithUsefulInstr(SchedulingManager& S,
SchedGraphNode* node,
// FIXME: passing vector BY VALUE!!!
const MachineInstr* brInstr = node->getMachineInstr();
unsigned ndelays= mii.getNumDelaySlots(brInstr->getOpcode());
assert(ndelays > 0 && "Unnecessary call to replace NOPs");
-
+
// Remove the NOPs currently in delay slots from the graph.
// If not enough useful instructions were found, use the NOPs to
// fill delay slots, otherwise, just discard them.
- //
+ //
unsigned int firstDelaySlotIdx = node->getOrigIndexInBB() + 1;
MachineBasicBlock& MBB = node->getMachineBasicBlock();
MachineBasicBlock::iterator MBBI = MBB.begin();
std::cerr << "Incorrect instr. index in basic block for brInstr";
abort();
}
-
+
// First find all useful instructions already in the delay slots
// and USE THEM. We'll throw away the unused alternatives below
- //
+ //
MachineBasicBlock::iterator Tmp = MBBI;
for (unsigned i = 0; i != ndelays; ++i, ++MBBI)
if (!mii.isNop(MBBI->getOpcode()))
sdelayNodeVec.push_back(graph->getGraphNodeForInstr(MBBI));
else {
nopNodeVec.push_back(graph->getGraphNodeForInstr(MBBI));
-
+
//remove the MI from the Machine Code For Instruction
const TerminatorInst *TI = MBB.getBasicBlock()->getTerminator();
- MachineCodeForInstruction& llvmMvec =
+ MachineCodeForInstruction& llvmMvec =
MachineCodeForInstruction::get((const Instruction *)TI);
-
- for(MachineCodeForInstruction::iterator mciI=llvmMvec.begin(),
+
+ for(MachineCodeForInstruction::iterator mciI=llvmMvec.begin(),
mciE=llvmMvec.end(); mciI!=mciE; ++mciI){
if (*mciI == MBBI)
llvmMvec.erase(mciI);
}
assert(sdelayNodeVec.size() >= ndelays);
-
+
// If some delay slots were already filled, throw away that many new choices
if (sdelayNodeVec.size() > ndelays)
sdelayNodeVec.resize(ndelays);
-
+
// Mark the nodes chosen for delay slots. This removes them from the graph.
for (unsigned i=0; i < sdelayNodeVec.size(); i++)
MarkNodeForDelaySlot(S, graph, sdelayNodeVec[i], node, true);
-
+
// And remove the unused NOPs from the graph.
for (unsigned i=0; i < nopNodeVec.size(); i++)
graph->eraseIncidentEdges(nopNodeVec[i], /*addDummyEdges*/ true);
// slots and pull those out of the graph. Mark them for the delay slots
// in the DelaySlotInfo object for that graph node. If no useful work
// is found for a delay slot, use the NOP that is currently in that slot.
-//
+//
// We try to fill the delay slots with useful work for all instructions
// EXCEPT CALLS AND RETURNS.
// For CALLs and RETURNs, it is nearly always possible to use one of the
// call sequence instrs and putting anything else in the delay slot could be
// suboptimal. Also, it complicates generating the calling sequence code in
// regalloc.
-//
+//
static void
ChooseInstructionsForDelaySlots(SchedulingManager& S, MachineBasicBlock &MBB,
SchedGraph *graph)
MachineCodeForInstruction &termMvec=MachineCodeForInstruction::get(termInstr);
std::vector<SchedGraphNode*> delayNodeVec;
const MachineInstr* brInstr = NULL;
-
+
if (EnableFillingDelaySlots &&
termInstr->getOpcode() != Instruction::Ret)
{
// machine code, we assume that the only delayed instructions are CALLs
// or instructions generated for the terminator inst.
// Find the first branch instr in the sequence of machine instrs for term
- //
+ //
unsigned first = 0;
while (first < termMvec.size() &&
! mii.isBranch(termMvec[first]->getOpcode()))
}
assert(first < termMvec.size() &&
"No branch instructions for BR? Ok, but weird! Delete assertion.");
-
+
brInstr = (first < termMvec.size())? termMvec[first] : NULL;
-
+
// Compute a vector of the nodes chosen for delay slots and then
// mark delay slots to replace NOPs with these useful instructions.
- //
+ //
if (brInstr != NULL) {
SchedGraphNode* brNode = graph->getGraphNodeForInstr(brInstr);
FindUsefulInstructionsForDelaySlots(S, brNode, delayNodeVec);
ReplaceNopsWithUsefulInstr(S, brNode, delayNodeVec, graph);
}
}
-
- // Also mark delay slots for other delayed instructions to hold NOPs.
+
+ // Also mark delay slots for other delayed instructions to hold NOPs.
// Simply passing in an empty delayNodeVec will have this effect.
// If brInstr is not handled above (EnableFillingDelaySlots == false),
// brInstr will be NULL so this will handle the branch instrs. as well.
- //
+ //
delayNodeVec.clear();
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
if (I != brInstr && mii.getNumDelaySlots(I->getOpcode()) > 0) {
}
-//
+//
// Schedule the delayed branch and its delay slots
-//
+//
unsigned
DelaySlotInfo::scheduleDelayedNode(SchedulingManager& S)
{
assert(delayedNodeSlotNum < S.nslots && "Illegal slot for branch");
assert(S.isched.getInstr(delayedNodeSlotNum, delayedNodeCycle) == NULL
&& "Slot for branch should be empty");
-
+
unsigned int nextSlot = delayedNodeSlotNum;
CycleCount_t nextTime = delayedNodeCycle;
-
+
S.scheduleInstr(brNode, nextSlot, nextTime);
-
+
for (unsigned d=0; d < ndelays; d++) {
++nextSlot;
if (nextSlot == S.nslots) {
nextSlot = 0;
nextTime++;
}
-
+
// Find the first feasible instruction for this delay slot
// Note that we only check for issue restrictions here.
// We do *not* check for flow dependences but rely on pipeline
}
}
}
-
+
// Update current time if delay slots overflowed into later cycles.
// Do this here because we know exactly which cycle is the last cycle
// that contains delay slots. The next loop doesn't compute that.
if (nextTime > S.getTime())
S.updateTime(nextTime);
-
+
// Now put any remaining instructions in the unfilled delay slots.
// This could lead to suboptimal performance but needed for correctness.
nextSlot = delayedNodeSlotNum;
// Check if the instruction would conflict with instructions already
// chosen for the current cycle
-//
+//
static inline bool
ConflictsWithChoices(const SchedulingManager& S,
MachineOpCode opCode)
// choices have already been made for this cycle
if (S.getNumChoices() > 0 && S.schedInfo.isSingleIssue(opCode))
return true;
-
+
// For each class that opCode belongs to, check if there are too many
// instructions of that class.
- //
+ //
const InstrSchedClass sc = S.schedInfo.getSchedClass(opCode);
return (S.getNumChoicesInClass(sc) == S.schedInfo.getMaxIssueForClass(sc));
}
//---------------------------------------------------------------------------
// Function: ViolatesMinimumGap
-//
+//
// Purpose:
// Check minimum gap requirements relative to instructions scheduled in
// previous cycles.
//---------------------------------------------------------------------------
// Function: instrIsFeasible
-//
+//
// Purpose:
// Check if any issue restrictions would prevent the instruction from
// being issued in the current cycle
// caused by previously issued instructions
if (ViolatesMinimumGap(S, opCode, S.getTime()))
return false;
-
+
// skip the instruction if it cannot be issued due to issue restrictions
// caused by previously chosen instructions for the current cycle
if (ConflictsWithChoices(S, opCode))
return false;
-
+
return true;
}
//---------------------------------------------------------------------------
// Function: ScheduleInstructionsWithSSA
-//
+//
// Purpose:
// Entry point for instruction scheduling on SSA form.
// Schedules the machine instructions generated by instruction selection.
inline InstructionSchedulingWithSSA(const TargetMachine &T) : target(T) {}
const char *getPassName() const { return "Instruction Scheduling"; }
-
+
// getAnalysisUsage - We use LiveVarInfo...
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<FunctionLiveVarInfo>();
AU.setPreservesCFG();
}
-
+
bool runOnFunction(Function &F);
};
} // end anonymous namespace
bool InstructionSchedulingWithSSA::runOnFunction(Function &F)
{
SchedGraphSet graphSet(&F, target);
-
+
if (SchedDebugLevel >= Sched_PrintSchedGraphs) {
std::cerr << "\n*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING\n";
graphSet.dump();
}
-
+
for (SchedGraphSet::const_iterator GI=graphSet.begin(), GE=graphSet.end();
GI != GE; ++GI)
{
SchedGraph* graph = (*GI);
MachineBasicBlock &MBB = graph->getBasicBlock();
-
+
if (SchedDebugLevel >= Sched_PrintSchedTrace)
std::cerr << "\n*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n";
-
+
// expensive!
SchedPriorities schedPrio(&F, graph, getAnalysis<FunctionLiveVarInfo>());
SchedulingManager S(target, graph, schedPrio);
-
+
ChooseInstructionsForDelaySlots(S, MBB, graph); // modifies graph
ForwardListSchedule(S); // computes schedule in S
RecordSchedule(MBB, S); // records schedule in BB
}
-
+
if (SchedDebugLevel >= Sched_PrintMachineCode) {
std::cerr << "\n*** Machine instructions after INSTRUCTION SCHEDULING\n";
MachineFunction::get(&F).dump();
}
-
+
return false;
}
//===- SchedGraph.cpp - Scheduling Graph Implementation -------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Scheduling graph based on SSA graph plus extra dependence edges capturing
// The following two types need to be classes, not typedefs, so we can use
// opaque declarations in SchedGraph.h
-//
+//
struct RefVec: public std::vector<std::pair<SchedGraphNode*, int> > {
typedef std::vector<std::pair<SchedGraphNode*,int> >::iterator iterator;
typedef
};
-//
+//
// class SchedGraphNode
-//
+//
SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb,
int indexInBB, const TargetMachine& Target)
SchedGraphNode::~SchedGraphNode() {
}
-//
+//
// class SchedGraph
-//
+//
SchedGraph::SchedGraph(MachineBasicBlock &mbb, const TargetMachine& target)
: MBB(mbb) {
buildGraph(target);
void SchedGraph::addDummyEdges() {
assert(graphRoot->getNumOutEdges() == 0);
-
+
for (const_iterator I=begin(); I != end(); ++I) {
SchedGraphNode* node = (*I).second;
assert(node != graphRoot && node != graphLeaf);
const TargetMachine& target) {
const TargetInstrInfo& mii = *target.getInstrInfo();
MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
-
+
// Find the first branch instr in the sequence of machine instrs for term
- //
+ //
unsigned first = 0;
while (! mii.isBranch(termMvec[first]->getOpcode()) &&
! mii.isReturn(termMvec[first]->getOpcode()))
"No branch instructions for terminator? Ok, but weird!");
if (first == termMvec.size())
return;
-
+
SchedGraphNode* firstBrNode = getGraphNodeForInstr(termMvec[first]);
-
+
// Add CD edges from each instruction in the sequence to the
- // *last preceding* branch instr. in the sequence
+ // *last preceding* branch instr. in the sequence
// Use a latency of 0 because we only need to prevent out-of-order issue.
- //
+ //
for (unsigned i = termMvec.size(); i > first+1; --i) {
SchedGraphNode* toNode = getGraphNodeForInstr(termMvec[i-1]);
assert(toNode && "No node for instr generated for branch/ret?");
-
- for (unsigned j = i-1; j != 0; --j)
+
+ for (unsigned j = i-1; j != 0; --j)
if (mii.isBranch(termMvec[j-1]->getOpcode()) ||
mii.isReturn(termMvec[j-1]->getOpcode())) {
SchedGraphNode* brNode = getGraphNodeForInstr(termMvec[j-1]);
break; // only one incoming edge is enough
}
}
-
+
// Add CD edges from each instruction preceding the first branch
// to the first branch. Use a latency of 0 as above.
- //
+ //
for (unsigned i = first; i != 0; --i) {
SchedGraphNode* fromNode = getGraphNodeForInstr(termMvec[i-1]);
assert(fromNode && "No node for instr generated for branch?");
(void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0);
}
-
+
// Now add CD edges to the first branch instruction in the sequence from
// all preceding instructions in the basic block. Use 0 latency again.
- //
+ //
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
if (&*I == termMvec[first]) // reached the first branch
break;
-
+
SchedGraphNode* fromNode = getGraphNodeForInstr(I);
if (fromNode == NULL)
continue; // dummy instruction, e.g., PHI
-
+
(void) new SchedGraphEdge(fromNode, firstBrNode,
SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0);
-
+
// If we find any other machine instructions (other than due to
// the terminator) that also have delay slots, add an outgoing edge
// from the instruction to the instructions in the delay slots.
- //
+ //
unsigned d = mii.getNumDelaySlots(I->getOpcode());
MachineBasicBlock::iterator J = I; ++J;
// instructions, where at least one is a store or a call.
// Use latency 1 just to ensure that memory operations are ordered;
// latency does not otherwise matter (true dependences enforce that).
-//
+//
void SchedGraph::addMemEdges(const std::vector<SchedGraphNode*>& memNodeVec,
const TargetMachine& target) {
const TargetInstrInfo& mii = *target.getInstrInfo();
-
+
// Instructions in memNodeVec are in execution order within the basic block,
// so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
- //
+ //
for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++) {
MachineOpCode fromOpCode = memNodeVec[im]->getOpcode();
int fromType = (mii.isCall(fromOpCode)? SG_CALL_REF
int toType = (mii.isCall(toOpCode)? SG_CALL_REF
: (mii.isLoad(toOpCode)? SG_LOAD_REF
: SG_STORE_REF));
-
+
if (fromType != SG_LOAD_REF || toType != SG_LOAD_REF)
(void) new SchedGraphEdge(memNodeVec[im], memNodeVec[jm],
SchedGraphEdge::MemoryDep,
SG_DepOrderArray[fromType][toType], 1);
}
}
-}
+}
// Add edges from/to CC reg instrs to/from call instrs.
// Essentially this prevents anything that sets or uses a CC reg from being
// reordered w.r.t. a call.
// Use a latency of 0 because we only need to prevent out-of-order issue,
// like with control dependences.
-//
+//
void SchedGraph::addCallDepEdges(const std::vector<SchedGraphNode*>& callDepNodeVec,
const TargetMachine& target) {
const TargetInstrInfo& mii = *target.getInstrInfo();
-
+
// Instructions in memNodeVec are in execution order within the basic block,
// so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
- //
+ //
for (unsigned ic=0, NC=callDepNodeVec.size(); ic < NC; ic++)
if (mii.isCall(callDepNodeVec[ic]->getOpcode())) {
// Add SG_CALL_REF edges from all preds to this instruction.
(void) new SchedGraphEdge(callDepNodeVec[jc], callDepNodeVec[ic],
SchedGraphEdge::MachineRegister,
MachineIntRegsRID, 0);
-
+
// And do the same from this instruction to all successors.
for (unsigned jc=ic+1; jc < NC; jc++)
(void) new SchedGraphEdge(callDepNodeVec[ic], callDepNodeVec[jc],
SchedGraphEdge::MachineRegister,
MachineIntRegsRID, 0);
}
-
+
#ifdef CALL_DEP_NODE_VEC_CANNOT_WORK
// Find the call instruction nodes and put them in a vector.
std::vector<SchedGraphNode*> callNodeVec;
for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
if (mii.isCall(memNodeVec[im]->getOpcode()))
callNodeVec.push_back(memNodeVec[im]);
-
+
// Now walk the entire basic block, looking for CC instructions *and*
// call instructions, and keep track of the order of the instructions.
// Use the call node vec to quickly find earlier and later call nodes
// relative to the current CC instruction.
- //
+ //
int lastCallNodeIdx = -1;
for (unsigned i=0, N=bbMvec.size(); i < N; i++)
if (mii.isCall(bbMvec[i]->getOpcode())) {
const TargetMachine& target) {
// This code assumes that two registers with different numbers are
// not aliased!
- //
+ //
for (RegToRefVecMap::iterator I = regToRefVecMap.begin();
I != regToRefVecMap.end(); ++I) {
int regNum = (*I).first;
RefVec& regRefVec = (*I).second;
-
+
// regRefVec is ordered by control flow order in the basic block
for (unsigned i=0; i < regRefVec.size(); ++i) {
SchedGraphNode* node = regRefVec[i].first;
node->getMachineInstr()->getExplOrImplOperand(opNum);
bool isDef = mop.isDef() && !mop.isUse();
bool isDefAndUse = mop.isDef() && mop.isUse();
-
+
for (unsigned p=0; p < i; ++p) {
SchedGraphNode* prevNode = regRefVec[p].first;
if (prevNode != node) {
new SchedGraphEdge(prevNode, node, regNum,
SchedGraphEdge::AntiDep);
}
-
+
if (prevIsDef)
if (!isDef || isDefAndUse)
new SchedGraphEdge(prevNode, node, regNum,
// Adds dependences to/from refNode from/to all other defs
// in the basic block. refNode may be a use, a def, or both.
// We do not consider other uses because we are not building use-use deps.
-//
+//
void SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
const RefVec& defVec,
const Value* defValue,
for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I) {
if ((*I).first == refNode)
continue; // Dont add any self-loops
-
+
if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB()) {
// (*).first is before refNode
if (refNodeIsDef && !refNodeIsUse)
SchedGraphNode* node = getGraphNodeForInstr(&MI);
if (node == NULL)
return;
-
+
// Add edges for all operands of the machine instruction.
- //
+ //
for (unsigned i = 0, numOps = MI.getNumOperands(); i != numOps; ++i) {
switch (MI.getOperand(i).getType()) {
case MachineOperand::MO_VirtualRegister:
target);
}
break;
-
+
case MachineOperand::MO_MachineRegister:
- break;
-
+ break;
+
case MachineOperand::MO_SignExtendedImmed:
case MachineOperand::MO_UnextendedImmed:
case MachineOperand::MO_PCRelativeDisp:
case MachineOperand::MO_ConstantPoolIndex:
break; // nothing to do for immediate fields
-
+
default:
assert(0 && "Unknown machine operand type in SchedGraph builder");
break;
}
}
-
+
// Add edges for values implicitly used by the machine instruction.
// Examples include function arguments to a Call instructions or the return
// value of a Ret instruction.
- //
+ //
for (unsigned i=0, N=MI.getNumImplicitRefs(); i < N; ++i)
if (MI.getImplicitOp(i).isUse())
if (const Value* srcI = MI.getImplicitRef(i)) {
RegToRefVecMap& regToRefVecMap,
ValueToDefVecMap& valueToDefVecMap) {
const TargetInstrInfo& mii = *target.getInstrInfo();
-
+
MachineOpCode opCode = node->getOpcode();
-
+
if (mii.isCall(opCode) || mii.isCCInstr(opCode))
callDepNodeVec.push_back(node);
-
+
if (mii.isLoad(opCode) || mii.isStore(opCode) || mii.isCall(opCode))
memNodeVec.push_back(node);
-
+
// Collect the register references and value defs. for explicit operands
- //
+ //
const MachineInstr& MI = *node->getMachineInstr();
for (int i=0, numOps = (int) MI.getNumOperands(); i < numOps; i++) {
const MachineOperand& mop = MI.getOperand(i);
-
+
// if this references a register other than the hardwired
// "zero" register, record the reference.
if (mop.hasAllocatedReg()) {
unsigned regNum = mop.getReg();
-
+
// If this is not a dummy zero register, record the reference in order
if (regNum != target.getRegInfo()->getZeroRegNum())
regToRefVecMap[mop.getReg()]
->isRegVolatile(regInClass))
callDepNodeVec.push_back(node);
}
-
+
continue; // nothing more to do
}
-
+
// ignore all other non-def operands
if (!MI.getOperand(i).isDef())
continue;
-
+
// We must be defining a value.
assert((mop.getType() == MachineOperand::MO_VirtualRegister ||
mop.getType() == MachineOperand::MO_CCRegister)
&& "Do not expect any other kind of operand to be defined!");
assert(mop.getVRegValue() != NULL && "Null value being defined?");
-
- valueToDefVecMap[mop.getVRegValue()].push_back(std::make_pair(node, i));
+
+ valueToDefVecMap[mop.getVRegValue()].push_back(std::make_pair(node, i));
}
-
- //
+
+ //
// Collect value defs. for implicit operands. They may have allocated
// physical registers also.
- //
+ //
for (unsigned i=0, N = MI.getNumImplicitRefs(); i != N; ++i) {
const MachineOperand& mop = MI.getImplicitOp(i);
if (mop.hasAllocatedReg()) {
if (mop.isDef()) {
assert(MI.getImplicitRef(i) != NULL && "Null value being defined?");
valueToDefVecMap[MI.getImplicitRef(i)].push_back(
- std::make_pair(node, -i));
+ std::make_pair(node, -i));
}
}
}
RegToRefVecMap& regToRefVecMap,
ValueToDefVecMap& valueToDefVecMap) {
const TargetInstrInfo& mii = *target.getInstrInfo();
-
+
// Build graph nodes for each VM instruction and gather def/use info.
// Do both those together in a single pass over all machine instructions.
unsigned i = 0;
if (I->getOpcode() != V9::PHI) {
SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
noteGraphNodeForInstr(I, node);
-
+
// Remember all register references and value defs
findDefUseInfoAtInstr(target, node, memNodeVec, callDepNodeVec,
regToRefVecMap, valueToDefVecMap);
void SchedGraph::buildGraph(const TargetMachine& target) {
// Use this data structure to note all machine operands that compute
- // ordinary LLVM values. These must be computed defs (i.e., instructions).
+ // ordinary LLVM values. These must be computed defs (i.e., instructions).
// Note that there may be multiple machine instructions that define
// each Value.
ValueToDefVecMap valueToDefVecMap;
-
+
// Use this data structure to note all memory instructions.
// We use this to add memory dependence edges without a second full walk.
std::vector<SchedGraphNode*> memNodeVec;
// Use this data structure to note all instructions that access physical
// registers that can be modified by a call (including call instructions)
std::vector<SchedGraphNode*> callDepNodeVec;
-
+
// Use this data structure to note any uses or definitions of
// machine registers so we can add edges for those later without
// extra passes over the nodes.
// ordered according to control-flow order. This only works for a
// single basic block, hence the assertion. Each reference is identified
// by the pair: <node, operand-number>.
- //
+ //
RegToRefVecMap regToRefVecMap;
-
+
// Make a dummy root node. We'll add edges to the real roots later.
graphRoot = new SchedGraphNode(0, NULL, -1, target);
graphLeaf = new SchedGraphNode(1, NULL, -1, target);
buildNodesForBB(target, MBB, memNodeVec, callDepNodeVec,
regToRefVecMap, valueToDefVecMap);
-
+
//----------------------------------------------------------------
// Now add edges for the following (all are incoming edges except (4)):
// (1) operands of the machine instruction, including hidden operands
// 2-way conditional branches, multiple CD edges are needed
// (see addCDEdges for details).
// Also, note any uses or defs of machine registers.
- //
+ //
//----------------------------------------------------------------
-
+
// First, add edges to the terminator instruction of the basic block.
this->addCDEdges(MBB.getBasicBlock()->getTerminator(), target);
-
+
// Then add memory dep edges: store->load, load->store, and store->store.
// Call instructions are treated as both load and store.
this->addMemEdges(memNodeVec, target);
// Then add edges between call instructions and CC set/use instructions
this->addCallDepEdges(callDepNodeVec, target);
-
+
// Then add incoming def-use (SSA) edges for each machine instruction.
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
addEdgesForInstruction(*I, valueToDefVecMap, target);
}
-//
+//
// class SchedGraphSet
-//
+//
SchedGraphSet::SchedGraphSet(const Function* _function,
const TargetMachine& target) :
function(_function) {
void SchedGraphSet::dump() const {
std::cerr << "======== Sched graphs for function `" << function->getName()
<< "' ========\n\n";
-
+
for (const_iterator I=begin(); I != end(); ++I)
(*I)->dump();
-
+
std::cerr << "\n====== End graphs for function `" << function->getName()
<< "' ========\n\n";
}
void SchedGraphEdge::print(std::ostream &os) const {
os << "edge [" << src->getNodeId() << "] -> ["
<< sink->getNodeId() << "] : ";
-
+
switch(depType) {
case SchedGraphEdge::CtrlDep:
- os<< "Control Dep";
+ os<< "Control Dep";
break;
- case SchedGraphEdge::ValueDep:
- os<< "Reg Value " << *val;
+ case SchedGraphEdge::ValueDep:
+ os<< "Reg Value " << *val;
break;
case SchedGraphEdge::MemoryDep:
- os<< "Memory Dep";
+ os<< "Memory Dep";
break;
- case SchedGraphEdge::MachineRegister:
+ case SchedGraphEdge::MachineRegister:
os<< "Reg " << machineRegNum;
break;
case SchedGraphEdge::MachineResource:
os<<"Resource "<< resourceId;
break;
- default:
- assert(0);
+ default:
+ assert(0);
break;
}
-
+
os << " : delay = " << minDelay << "\n";
}
os << std::string(8, ' ')
<< "Node " << ID << " : "
<< "latency = " << latency << "\n" << std::string(12, ' ');
-
+
if (getMachineInstr() == NULL)
os << "(Dummy node)\n";
else {
os << inEdges.size() << " Incoming Edges:\n";
for (unsigned i=0, N = inEdges.size(); i < N; i++)
os << std::string(16, ' ') << *inEdges[i];
-
+
os << std::string(12, ' ') << outEdges.size()
<< " Outgoing Edges:\n";
for (unsigned i=0, N= outEdges.size(); i < N; i++)
//===-- SchedGraph.h - Scheduling Graph -------------------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This is a scheduling graph based on SSA graph plus extra dependence edges
// capturing dependences due to machine resources (machine registers, CC
// registers, and any others).
-//
+//
// This graph tries to leverage the SSA graph as much as possible, but captures
// the extra dependences through a common interface.
-//
+//
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_SCHEDGRAPH_H
const MachineInstr *MI;
- SchedGraphNode(unsigned nodeId, MachineBasicBlock *mbb, int indexInBB,
+ SchedGraphNode(unsigned nodeId, MachineBasicBlock *mbb, int indexInBB,
const TargetMachine& Target);
~SchedGraphNode();
class SchedGraph : public SchedGraphCommon {
MachineBasicBlock &MBB;
hash_map<const MachineInstr*, SchedGraphNode*> GraphMap;
-
+
public:
typedef hash_map<const MachineInstr*, SchedGraphNode*>::const_iterator iterator;
typedef hash_map<const MachineInstr*, SchedGraphNode*>::const_iterator const_iterator;
-
+
MachineBasicBlock& getBasicBlock() const{return MBB;}
const unsigned int getNumNodes() const { return GraphMap.size()+2; }
SchedGraphNode* getGraphNodeForInstr(const MachineInstr* MI) const {
const_iterator onePair = find(MI);
return (onePair != end())? onePair->second : NULL;
}
-
+
// Debugging support
void dump() const;
-
+
protected:
SchedGraph(MachineBasicBlock& mbb, const TargetMachine& TM);
~SchedGraph();
hash_map<const MachineInstr*, SchedGraphNode*>::const_iterator end() const {
return GraphMap.end();
}
-
+
unsigned size() { return GraphMap.size(); }
iterator find(const MachineInstr *MI) const { return GraphMap.find(MI); }
-
+
SchedGraphNode *&operator[](const MachineInstr *MI) {
return GraphMap[MI];
}
-
+
private:
friend class SchedGraphSet; // give access to ctor
-
+
inline void noteGraphNodeForInstr (const MachineInstr* minstr,
SchedGraphNode* node) {
assert((*this)[minstr] == NULL);
// Graph builder
//
void buildGraph(const TargetMachine& target);
-
+
void buildNodesForBB(const TargetMachine& target,MachineBasicBlock &MBB,
std::vector<SchedGraphNode*>& memNV,
std::vector<SchedGraphNode*>& callNV,
RegToRefVecMap& regToRefVecMap,
ValueToDefVecMap& valueToDefVecMap);
-
+
void findDefUseInfoAtInstr(const TargetMachine& target, SchedGraphNode* node,
std::vector<SchedGraphNode*>& memNV,
std::vector<SchedGraphNode*>& callNV,
RegToRefVecMap& regToRefVecMap,
ValueToDefVecMap& valueToDefVecMap);
-
+
void addEdgesForInstruction(const MachineInstr& minstr,
const ValueToDefVecMap& valueToDefVecMap,
const TargetMachine& target);
-
+
void addCDEdges(const TerminatorInst* term, const TargetMachine& target);
-
+
void addMemEdges(const std::vector<SchedGraphNode*>& memNod,
const TargetMachine& target);
-
+
void addCallCCEdges(const std::vector<SchedGraphNode*>& memNod,
MachineBasicBlock& bbMvec,
const TargetMachine& target);
void addCallDepEdges(const std::vector<SchedGraphNode*>& callNV,
const TargetMachine& target);
-
+
void addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
const TargetMachine& target);
-
+
void addEdgesForValue(SchedGraphNode* refNode, const RefVec& defVec,
const Value* defValue, bool refNodeIsDef,
bool refNodeIsDefAndUse,
inline void addGraph(SchedGraph* graph) {
assert(graph != NULL);
Graphs.push_back(graph);
- }
+ }
public:
SchedGraphSet(const Function *function, const TargetMachine& target);
~SchedGraphSet();
-
+
//iterators
typedef std::vector<SchedGraph*>::const_iterator iterator;
typedef std::vector<SchedGraph*>::const_iterator const_iterator;
-//
+//
// sg_pred_iterator
// sg_pred_const_iterator
//
}
-//
+//
// sg_succ_iterator
// sg_succ_const_iterator
//
typedef sg_succ_iterator ChildIteratorType;
static inline NodeType *getEntryNode(SchedGraph *SG) { return (NodeType*)SG->getRoot(); }
- static inline ChildIteratorType child_begin(NodeType *N) {
- return succ_begin(N);
+ static inline ChildIteratorType child_begin(NodeType *N) {
+ return succ_begin(N);
}
- static inline ChildIteratorType child_end(NodeType *N) {
+ static inline ChildIteratorType child_end(NodeType *N) {
return succ_end(N);
}
};
static inline NodeType *getEntryNode(const SchedGraph *SG) {
return (NodeType*)SG->getRoot();
}
- static inline ChildIteratorType child_begin(NodeType *N) {
- return succ_begin(N);
+ static inline ChildIteratorType child_begin(NodeType *N) {
+ return succ_begin(N);
}
- static inline ChildIteratorType child_end(NodeType *N) {
+ static inline ChildIteratorType child_end(NodeType *N) {
return succ_end(N);
}
};
//===- SchedGraphCommon.cpp - Scheduling Graphs Base Class- ---------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Scheduling graph base class that contains common information for SchedGraph
//
// class SchedGraphEdge
-//
+//
SchedGraphEdge::SchedGraphEdge(SchedGraphNodeCommon* _src,
SchedGraphNodeCommon* _sink,
SchedGraphEdgeDepType _depType,
int _minDelay)
: src(_src), sink(_sink), depType(_depType), depOrderType(_depOrderType),
minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()), val(NULL) {
-
+
iteDiff=0;
assert(src != sink && "Self-loop in scheduling graph!");
src->addOutEdge(this);
void SchedGraphEdge::dump(int indent) const {
- std::cerr << std::string(indent*2, ' ') << *this;
+ std::cerr << std::string(indent*2, ' ') << *this;
}
/*dtor*/
void SchedGraphNodeCommon::removeInEdge(const SchedGraphEdge* edge) {
assert(edge->getSink() == this);
-
+
for (iterator I = beginInEdges(); I != endInEdges(); ++I)
if ((*I) == edge) {
inEdges.erase(I);
void SchedGraphNodeCommon::removeOutEdge(const SchedGraphEdge* edge) {
assert(edge->getSrc() == this);
-
+
for (iterator I = beginOutEdges(); I != endOutEdges(); ++I)
if ((*I) == edge) {
outEdges.erase(I);
}
void SchedGraphNodeCommon::dump(int indent) const {
- std::cerr << std::string(indent*2, ' ') << *this;
+ std::cerr << std::string(indent*2, ' ') << *this;
}
//class SchedGraphCommon
}
-void SchedGraphCommon::eraseIncomingEdges(SchedGraphNodeCommon* node,
+void SchedGraphCommon::eraseIncomingEdges(SchedGraphNodeCommon* node,
bool addDummyEdges) {
// Delete and disconnect all in-edges for the node
for (SchedGraphNodeCommon::iterator I = node->beginInEdges();
SchedGraphNodeCommon* srcNode = (*I)->getSrc();
srcNode->removeOutEdge(*I);
delete *I;
-
+
if (addDummyEdges && srcNode != getRoot() &&
- srcNode->beginOutEdges() == srcNode->endOutEdges()) {
-
+ srcNode->beginOutEdges() == srcNode->endOutEdges()) {
+
// srcNode has no more out edges, so add an edge to dummy EXIT node
assert(node != getLeaf() && "Adding edge that was just removed?");
(void) new SchedGraphEdge(srcNode, getLeaf(),
- SchedGraphEdge::CtrlDep,
+ SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0);
}
}
-
+
node->inEdges.clear();
}
-void SchedGraphCommon::eraseOutgoingEdges(SchedGraphNodeCommon* node,
+void SchedGraphCommon::eraseOutgoingEdges(SchedGraphNodeCommon* node,
bool addDummyEdges) {
// Delete and disconnect all out-edges for the node
for (SchedGraphNodeCommon::iterator I = node->beginOutEdges();
SchedGraphNodeCommon* sinkNode = (*I)->getSink();
sinkNode->removeInEdge(*I);
delete *I;
-
+
if (addDummyEdges &&
sinkNode != getLeaf() &&
sinkNode->beginInEdges() == sinkNode->endInEdges()) {
-
+
//sinkNode has no more in edges, so add an edge from dummy ENTRY node
assert(node != getRoot() && "Adding edge that was just removed?");
(void) new SchedGraphEdge(getRoot(), sinkNode,
- SchedGraphEdge::CtrlDep,
+ SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0);
}
}
-
+
node->outEdges.clear();
}
-void SchedGraphCommon::eraseIncidentEdges(SchedGraphNodeCommon* node,
+void SchedGraphCommon::eraseIncidentEdges(SchedGraphNodeCommon* node,
bool addDummyEdges) {
this->eraseIncomingEdges(node, addDummyEdges);
this->eraseOutgoingEdges(node, addDummyEdges);
//===-- SchedPriorities.h - Encapsulate scheduling heuristics -------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// Strategy:
// Priority ordering rules:
// (1) Max delay, which is the order of the heap S.candsAsHeap.
SchedPriorities::initializeReadyHeap(const SchedGraph* graph) {
const SchedGraphNode* graphRoot = (const SchedGraphNode*)graph->getRoot();
assert(graphRoot->getMachineInstr() == NULL && "Expect dummy root");
-
+
// Insert immediate successors of dummy root, which are the actual roots
sg_succ_const_iterator SEnd = succ_end(graphRoot);
for (sg_succ_const_iterator S = succ_begin(graphRoot); S != SEnd; ++S)
this->insertReady(*S);
-
+
#undef TEST_HEAP_CONVERSION
#ifdef TEST_HEAP_CONVERSION
std::cerr << "Before heap conversion:\n";
copy(candsAsHeap.begin(), candsAsHeap.end(),
ostream_iterator<NodeDelayPair*>(std::cerr,"\n"));
#endif
-
+
candsAsHeap.makeHeap();
-
+
nextToTry = candsAsHeap.begin();
-
+
#ifdef TEST_HEAP_CONVERSION
std::cerr << "After heap conversion:\n";
copy(candsAsHeap.begin(), candsAsHeap.end(),
mcands.clear(); // ensure reset choices is called before any more choices
earliestReadyTime = std::min(earliestReadyTime,
getEarliestReadyTimeForNode(node));
-
+
if (SchedDebugLevel >= Sched_PrintSchedTrace) {
std::cerr << " Node " << node->getNodeId() << " will be ready in Cycle "
<< getEarliestReadyTimeForNode(node) << "; "
candsAsHeap.removeNode(node);
candsAsSet.erase(node);
mcands.clear(); // ensure reset choices is called before any more choices
-
+
if (earliestReadyTime == getEarliestReadyTimeForNode(node)) {
// earliestReadyTime may have been due to this node, so recompute it
earliestReadyTime = HUGE_LATENCY;
for (NodeHeap::const_iterator I=candsAsHeap.begin();
I != candsAsHeap.end(); ++I)
if (candsAsHeap.getNode(I)) {
- earliestReadyTime =
- std::min(earliestReadyTime,
+ earliestReadyTime =
+ std::min(earliestReadyTime,
getEarliestReadyTimeForNode(candsAsHeap.getNode(I)));
}
}
-
+
// Now update ready times for successors
for (SchedGraphNode::const_iterator E=node->beginOutEdges();
E != node->endOutEdges(); ++E) {
CycleCount_t& etime =
getEarliestReadyTimeForNodeRef((SchedGraphNode*)(*E)->getSink());
etime = std::max(etime, curTime + (*E)->getMinDelay());
- }
+ }
}
indexWithMaxUses = i;
}
}
- return indexWithMaxUses;
+ return indexWithMaxUses;
}
const SchedGraphNode*
CycleCount_t curTime) {
int nextIdx = -1;
const SchedGraphNode* nextChoice = NULL;
-
+
if (mcands.size() == 0)
findSetWithMaxDelay(mcands, S);
-
+
while (nextIdx < 0 && mcands.size() > 0) {
nextIdx = chooseByRule1(mcands); // rule 1
-
+
if (nextIdx == -1)
nextIdx = chooseByRule2(mcands); // rule 2
-
+
if (nextIdx == -1)
nextIdx = chooseByRule3(mcands); // rule 3
-
+
if (nextIdx == -1)
nextIdx = 0; // default to first choice by delays
-
+
// We have found the next best candidate. Check if it ready in
// the current cycle, and if it is feasible.
// If not, remove it from mcands and continue. Refill mcands if
findSetWithMaxDelay(mcands, S);
}
}
-
+
if (nextIdx >= 0) {
mcands.erase(mcands.begin() + nextIdx);
return nextChoice;
for (; next != candsAsHeap.end()
&& candsAsHeap.getDelay(next) == maxDelay; ++next)
mcands.push_back(next);
-
+
nextToTry = next;
-
+
if (SchedDebugLevel >= Sched_PrintSchedTrace) {
std::cerr << " Cycle " << (long)getTime() << ": "
<< "Next highest delay = " << (long)maxDelay << " : "
SchedPriorities::instructionHasLastUse(FunctionLiveVarInfo &LVI,
const SchedGraphNode* graphNode) {
const MachineInstr *MI = graphNode->getMachineInstr();
-
+
hash_map<const MachineInstr*, bool>::const_iterator
ui = lastUseMap.find(MI);
if (ui != lastUseMap.end())
return ui->second;
-
+
// else check if instruction is a last use and save it in the hash_map
bool hasLastUse = false;
const BasicBlock* bb = graphNode->getMachineBasicBlock().getBasicBlock();
const ValueSet &LVs = LVI.getLiveVarSetBeforeMInst(MI, bb);
-
+
for (MachineInstr::const_val_op_iterator OI = MI->begin(), OE = MI->end();
OI != OE; ++OI)
if (!LVs.count(*OI)) {
//===-- SchedPriorities.h - Encapsulate scheduling heuristics --*- C++ -*--===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// Strategy:
// Priority ordering rules:
// (1) Max delay, which is the order of the heap S.candsAsHeap.
enum SchedDebugLevel_t {
Sched_NoDebugInfo,
Sched_Disable,
- Sched_PrintMachineCode,
+ Sched_PrintMachineCode,
Sched_PrintSchedTrace,
Sched_PrintSchedGraphs,
};
//---------------------------------------------------------------------------
// Function: instrIsFeasible
-//
+//
// Purpose:
// Used by the priority analysis to filter out instructions
// that are not feasible to issue in the current cycle.
public:
typedef std::list<NodeDelayPair*>::iterator iterator;
typedef std::list<NodeDelayPair*>::const_iterator const_iterator;
-
+
public:
NodeHeap() : _size(0) {}
-
+
inline unsigned size() const { return _size; }
-
+
const SchedGraphNode* getNode (const_iterator i) const { return (*i)->node; }
CycleCount_t getDelay(const_iterator i) const { return (*i)->delay;}
-
- inline void makeHeap() {
+
+ inline void makeHeap() {
// make_heap(begin(), end(), NDPLessThan);
}
-
+
inline iterator findNode(const SchedGraphNode* node) {
for (iterator I=begin(); I != end(); ++I)
if (getNode(I) == node)
return I;
return end();
}
-
+
inline void removeNode (const SchedGraphNode* node) {
iterator ndpPtr = findNode(node);
if (ndpPtr != end())
--_size;
}
};
-
+
void insert(const SchedGraphNode* node, CycleCount_t delay) {
NodeDelayPair* ndp = new NodeDelayPair(node, delay);
if (_size == 0 || front()->delay < delay)
public:
SchedPriorities(const Function *F, const SchedGraph *G,
FunctionLiveVarInfo &LVI);
-
-
+
+
// This must be called before scheduling begins.
void initialize ();
-
+
CycleCount_t getTime () const { return curTime; }
CycleCount_t getEarliestReadyTime () const { return earliestReadyTime; }
unsigned getNumReady () const { return candsAsHeap.size(); }
bool nodeIsReady (const SchedGraphNode* node) const {
return (candsAsSet.find(node) != candsAsSet.end());
}
-
+
void issuedReadyNodeAt (CycleCount_t curTime,
const SchedGraphNode* node);
-
+
void insertReady (const SchedGraphNode* node);
-
+
void updateTime (CycleCount_t /*unused*/);
-
+
const SchedGraphNode* getNextHighest (const SchedulingManager& S,
CycleCount_t curTime);
// choose next highest priority instr
-
+
private:
typedef NodeHeap::iterator candIndex;
-
+
private:
CycleCount_t curTime;
const SchedGraph* graph;
std::vector<candIndex> mcands; // holds pointers into cands
candIndex nextToTry; // next cand after the last
// one tried in this cycle
-
+
int chooseByRule1 (std::vector<candIndex>& mcands);
int chooseByRule2 (std::vector<candIndex>& mcands);
int chooseByRule3 (std::vector<candIndex>& mcands);
-
+
void findSetWithMaxDelay (std::vector<candIndex>& mcands,
const SchedulingManager& S);
-
+
void computeDelays (const SchedGraph* graph);
-
+
void initializeReadyHeap (const SchedGraph* graph);
-
+
bool instructionHasLastUse (FunctionLiveVarInfo& LVI,
const SchedGraphNode* graphNode);
-
+
// NOTE: The next two return references to the actual vector entries.
// Use the following two if you don't need to modify the value.
CycleCount_t& getNodeDelayRef (const SchedGraphNode* node) {
assert(node->getNodeId() < earliestReadyTimeForNode.size());
return earliestReadyTimeForNode[node->getNodeId()];
}
-
+
CycleCount_t getNodeDelay (const SchedGraphNode* node) const {
- return ((SchedPriorities*) this)->getNodeDelayRef(node);
+ return ((SchedPriorities*) this)->getNodeDelayRef(node);
}
CycleCount_t getEarliestReadyTimeForNode(const SchedGraphNode* node) const {
return ((SchedPriorities*) this)->getEarliestReadyTimeForNodeRef(node);
//===-- InternalGlobalMapper.cpp - Mapping Info for Internal Globals ------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// InternalGlobalMapper is a pass that helps the runtime trace optimizer map
std::vector<Constant *> FieldValues;
FieldValues.push_back (ConstantUInt::get (Type::UIntTy, gvvector.size ()));
FieldValues.push_back (ConstantArray::get (ATy, gvvector));
-
+
// Add the constant struct to M as an external global symbol named
// "_llvm_internalGlobals".
new GlobalVariable (STy, true, GlobalValue::ExternalLinkage,
//===-- BBLiveVar.cpp - Live Variable Analysis for a BasicBlock -----------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This is a wrapper class for BasicBlock which is used by live var analysis.
for (MachineBasicBlock::const_reverse_iterator MII = MBB.rbegin(),
MIE = MBB.rend(); MII != MIE; ++MII) {
const MachineInstr *MI = &*MII;
-
+
if (DEBUG_LV >= LV_DEBUG_Verbose) {
std::cerr << " *Iterating over machine instr ";
MI->dump();
for (unsigned i = 0; i < MI->getNumImplicitRefs(); ++i)
if (MI->getImplicitOp(i).isDef())
addDef(MI->getImplicitRef(i));
-
+
// iterate over MI operands to find uses
for (MachineInstr::const_val_op_iterator OpI = MI->begin(), OpE = MI->end();
OpI != OpE; ++OpI) {
// instructions is untested. The previous code was broken and I
// fixed it, but it turned out to be unused as long as Phi
// elimination is performed during instruction selection.
- //
+ //
// Put Phi operands in UseSet for the incoming edge, not node.
// They must not "hide" later defs, and must be handled specially
// during set propagation over the CFG.
if (MI->getOpcode() == V9::PHI) { // for a phi node
const Value *ArgVal = Op;
const BasicBlock *PredBB = cast<BasicBlock>(*++OpI); // next ptr is BB
-
- PredToEdgeInSetMap[PredBB].insert(ArgVal);
-
+
+ PredToEdgeInSetMap[PredBB].insert(ArgVal);
+
if (DEBUG_LV >= LV_DEBUG_Verbose)
std::cerr << " - phi operand " << RAV(ArgVal) << " came from BB "
<< RAV(PredBB) << "\n";
addUse(Op);
}
} // for all machine instructions
-}
+}
void BBLiveVar::addDef(const Value *Op) {
DefSet.insert(Op); // operand is a def - so add to def set
InSet.erase(Op); // this definition kills any later uses
- InSetChanged = true;
+ InSetChanged = true;
if (DEBUG_LV >= LV_DEBUG_Verbose) std::cerr << " +Def: " << RAV(Op) << "\n";
}
void BBLiveVar::addUse(const Value *Op) {
InSet.insert(Op); // An operand is a use - so add to use set
DefSet.erase(Op); // remove if there is a def below this use
- InSetChanged = true;
+ InSetChanged = true;
if (DEBUG_LV >= LV_DEBUG_Verbose) std::cerr << " Use: " << RAV(Op) << "\n";
}
//-----------------------------------------------------------------------------
// Applies the transfer function to a basic block to produce the InSet using
-// the OutSet.
+// the OutSet.
//-----------------------------------------------------------------------------
bool BBLiveVar::applyTransferFunc() {
- // IMPORTANT: caller should check whether the OutSet changed
+ // IMPORTANT: caller should check whether the OutSet changed
// (else no point in calling)
ValueSet OutMinusDef = set_difference(OutSet, DefSet);
InSetChanged = set_union(InSet, OutMinusDef);
-
+
OutSetChanged = false; // no change to OutSet since transf func applied
return InSetChanged;
}
// calculates Out set using In sets of the successors
//-----------------------------------------------------------------------------
-bool BBLiveVar::setPropagate(ValueSet *OutSet, const ValueSet *InSet,
+bool BBLiveVar::setPropagate(ValueSet *OutSet, const ValueSet *InSet,
const BasicBlock *PredBB) {
bool Changed = false;
-
+
// merge all members of InSet into OutSet of the predecessor
for (ValueSet::const_iterator InIt = InSet->begin(), InE = InSet->end();
InIt != InE; ++InIt)
if ((OutSet->insert(*InIt)).second)
Changed = true;
-
- //
+
+ //
//**** WARNING: The following code for handling dummy PHI machine
// instructions is untested. See explanation above.
- //
+ //
// then merge all members of the EdgeInSet for the predecessor into the OutSet
const ValueSet& EdgeInSet = PredToEdgeInSetMap[PredBB];
for (ValueSet::const_iterator InIt = EdgeInSet.begin(), InE = EdgeInSet.end();
InIt != InE; ++InIt)
if ((OutSet->insert(*InIt)).second)
Changed = true;
- //
+ //
//****
-
+
return Changed;
-}
+}
//-----------------------------------------------------------------------------
bool BBLiveVar::applyFlowFunc(hash_map<const BasicBlock*,
BBLiveVar*> &BBLiveVarInfo) {
- // IMPORTANT: caller should check whether inset changed
+ // IMPORTANT: caller should check whether inset changed
// (else no point in calling)
-
+
// If this BB changed any OutSets of preds whose POID is lower, than we need
// another iteration...
//
- bool needAnotherIt = false;
+ bool needAnotherIt = false;
for (pred_const_iterator PI = pred_begin(&BB), PE = pred_end(&BB);
PI != PE ; ++PI) {
BBLiveVar *PredLVBB = BBLiveVarInfo[*PI];
// do set union
- if (setPropagate(&PredLVBB->OutSet, &InSet, *PI)) {
+ if (setPropagate(&PredLVBB->OutSet, &InSet, *PI)) {
PredLVBB->OutSetChanged = true;
// if the predec POID is lower than mine
if (PredLVBB->getPOId() <= POID)
- needAnotherIt = true;
+ needAnotherIt = true;
}
} // for
//===-- BBLiveVar.h - Live Variable Analysis for a BasicBlock ---*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This is a BasicBlock annotation class that is used by live var analysis to
// coming in on that edge. such uses have to be
// treated differently from ordinary uses.
hash_map<const BasicBlock *, ValueSet> PredToEdgeInSetMap;
-
+
// method to propagate an InSet to OutSet of a predecessor
- bool setPropagate(ValueSet *OutSetOfPred,
+ bool setPropagate(ValueSet *OutSetOfPred,
const ValueSet *InSetOfThisBB,
const BasicBlock *PredBB);
// To add an operand which is a def
- void addDef(const Value *Op);
+ void addDef(const Value *Op);
// To add an operand which is a use
void addUse(const Value *Op);
BBLiveVar(const BasicBlock &BB, const MachineBasicBlock &MBB, unsigned POID);
- inline bool isInSetChanged() const { return InSetChanged; }
+ inline bool isInSetChanged() const { return InSetChanged; }
inline bool isOutSetChanged() const { return OutSetChanged; }
const MachineBasicBlock &getMachineBasicBlock() const { return MBB; }
inline unsigned getPOId() const { return POID; }
- bool applyTransferFunc(); // calcultes the In in terms of Out
+ bool applyTransferFunc(); // calcultes the In in terms of Out
// calculates Out set using In sets of the predecessors
bool applyFlowFunc(hash_map<const BasicBlock*, BBLiveVar*> &BBLiveVarInfo);
//===-- FunctionLiveVarInfo.cpp - Live Variable Analysis for a Function ---===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This is the interface to function level live variable information that is
unsigned int iter=0;
while (doSingleBackwardPass(M, iter++))
; // Iterate until we are done.
-
+
if (DEBUG_LV) std::cerr << "Live Variable Analysis complete!\n";
return false;
}
MachineFunction &MF = MachineFunction::get(F);
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
- const BasicBlock &BB = *I->getBasicBlock(); // get the current BB
+ const BasicBlock &BB = *I->getBasicBlock(); // get the current BB
if (DEBUG_LV) std::cerr << " For BB " << RAV(BB) << ":\n";
BBLiveVar *LVBB;
LVBB = new BBLiveVar(BB, *I, ++POId);
}
BBLiveVarInfo[&BB] = LVBB;
-
+
if (DEBUG_LV)
LVBB->printAllSets();
}
if (DEBUG_LV) std::cerr << " For BB " << (*BBI)->getName() << ":\n";
// InSets are initialized to "GenSet". Recompute only if OutSet changed.
- if(LVBB->isOutSetChanged())
+ if(LVBB->isOutSetChanged())
LVBB->applyTransferFunc(); // apply the Tran Func to calc InSet
-
+
// OutSets are initialized to EMPTY. Recompute on first iter or if InSet
// changed.
if (iter == 0 || LVBB->isInSetChanged()) // to calc Outsets of preds
NeedAnotherIteration |= LVBB->applyFlowFunc(BBLiveVarInfo);
-
+
if (DEBUG_LV) LVBB->printInOutSets();
}
// true if we need to reiterate over the CFG
- return NeedAnotherIteration;
+ return NeedAnotherIteration;
}
// Following functions will give the LiveVar info for any machine instr in
// a function. It should be called after a call to analyze().
//
-// These functions calculate live var info for all the machine instrs in a
-// BB when LVInfo for one inst is requested. Hence, this function is useful
-// when live var info is required for many (or all) instructions in a basic
-// block. Also, the arguments to this function does not require specific
+// These functions calculate live var info for all the machine instrs in a
+// BB when LVInfo for one inst is requested. Hence, this function is useful
+// when live var info is required for many (or all) instructions in a basic
+// block. Also, the arguments to this function does not require specific
// iterators.
//-----------------------------------------------------------------------------
// Gives live variable information after a machine instruction
//-----------------------------------------------------------------------------
-const ValueSet &
+const ValueSet &
FunctionLiveVarInfo::getLiveVarSetAfterMInst(const MachineInstr *MI,
const BasicBlock *BB) {
ValueSet* &LVSet = MInst2LVSetAI[MI]; // ref. to map entry
- if (LVSet == NULL && BB != NULL) { // if not found and BB provided
+ if (LVSet == NULL && BB != NULL) { // if not found and BB provided
calcLiveVarSetsForBB(BB); // calc LVSet for all instrs in BB
assert(LVSet != NULL);
}
// This function applies a machine instr to a live var set (accepts OutSet) and
// makes necessary changes to it (produces InSet). Note that two for loops are
// used to first kill all defs and then to add all uses. This is because there
-// can be instructions like Val = Val + 1 since we allow multiple defs to a
+// can be instructions like Val = Val + 1 since we allow multiple defs to a
// machine instruction operand.
//
static void applyTranferFuncForMInst(ValueSet &LVS, const MachineInstr *MInst) {
}
//-----------------------------------------------------------------------------
-// This method calculates the live variable information for all the
+// This method calculates the live variable information for all the
// instructions in a basic block and enter the newly constructed live
// variable sets into a the caches (MInst2LVSetAI, MInst2LVSetBI)
//-----------------------------------------------------------------------------
if (DEBUG_LV >= LV_DEBUG_Instr)
std::cerr << "\n======For BB " << BB->getName()
<< ": Live var sets for instructions======\n";
-
+
ValueSet *SetAI = &getOutSetOfBB(BB); // init SetAI with OutSet
ValueSet CurSet(*SetAI); // CurSet now contains OutSet
// iterate over all the machine instructions in BB
for (MachineBasicBlock::const_reverse_iterator MII = MIVec.rbegin(),
- MIE = MIVec.rend(); MII != MIE; ++MII) {
+ MIE = MIVec.rend(); MII != MIE; ++MII) {
// MI is cur machine inst
- const MachineInstr *MI = &*MII;
+ const MachineInstr *MI = &*MII;
MInst2LVSetAI[MI] = SetAI; // record in After Inst map
}
// SetAI will be used in the next iteration
- SetAI = NewSet;
+ SetAI = NewSet;
}
}
//===-- CodeGen/FunctionLiveVarInfo.h - LiveVar Analysis --------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
-// This is the interface for live variable info of a function that is required
+// This is the interface for live variable info of a function that is required
// by any other part of the compiler
//
-// After the analysis, getInSetOfBB or getOutSetofBB can be called to get
+// After the analysis, getInSetOfBB or getOutSetofBB can be called to get
// live var info of a BB.
//
// The live var set before an instruction can be obtained in 2 ways:
//
-// 1. Use the method getLiveVarSetAfterInst(Instruction *) to get the LV Info
+// 1. Use the method getLiveVarSetAfterInst(Instruction *) to get the LV Info
// just after an instruction. (also exists getLiveVarSetBeforeInst(..))
//
-// This function caluclates the LV info for a BB only once and caches that
-// info. If the cache does not contain the LV info of the instruction, it
+// This function caluclates the LV info for a BB only once and caches that
+// info. If the cache does not contain the LV info of the instruction, it
// calculates the LV info for the whole BB and caches them.
//
-// Getting liveVar info this way uses more memory since, LV info should be
+// Getting liveVar info this way uses more memory since, LV info should be
// cached. However, if you need LV info of nearly all the instructions of a
// BB, this is the best and simplest interfrace.
//
-// 2. Use the OutSet and applyTranferFuncForInst(const Instruction *const Inst)
-// declared in LiveVarSet and traverse the instructions of a basic block in
-// reverse (using const_reverse_iterator in the BB class).
+// 2. Use the OutSet and applyTranferFuncForInst(const Instruction *const Inst)
+// declared in LiveVarSet and traverse the instructions of a basic block in
+// reverse (using const_reverse_iterator in the BB class).
//
//===----------------------------------------------------------------------===//
class FunctionLiveVarInfo : public FunctionPass {
// Machine Instr to LiveVarSet Map for providing LVset BEFORE each inst
// These sets are owned by this map and will be freed in releaseMemory().
- hash_map<const MachineInstr *, ValueSet *> MInst2LVSetBI;
+ hash_map<const MachineInstr *, ValueSet *> MInst2LVSetBI;
// Machine Instr to LiveVarSet Map for providing LVset AFTER each inst.
// These sets are just pointers to sets in MInst2LVSetBI or BBLiveVar.
// constructs BBLiveVars and init Def and In sets
void constructBBs(const Function *F);
-
+
// do one backward pass over the CFG
- bool doSingleBackwardPass(const Function *F, unsigned int iter);
+ bool doSingleBackwardPass(const Function *F, unsigned int iter);
// calculates live var sets for instructions in a BB
void calcLiveVarSetsForBB(const BasicBlock *BB);
-
+
public:
// --------- Implement the FunctionPass interface ----------------------
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
// FIXME: Eliminate this file.
namespace llvm {
-std::ostream &operator<<(std::ostream &O, RAV V) { // func to print a Value
+std::ostream &operator<<(std::ostream &O, RAV V) { // func to print a Value
const Value &v = V.V;
if (v.hasName())
return O << (void*)&v << "(" << v.getName() << ") ";
//===-- MachineCodeForInstruction.cpp -------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Container for the sequence of MachineInstrs created for a single
// they can be deleted when they are no longer needed, and finally, it also
// holds some extra information for 'call' Instructions (using the
// CallArgsDescriptor object, which is also implemented in this file).
-//
+//
//===----------------------------------------------------------------------===//
#include "MachineCodeForInstruction.h"
MachineCodeForInstruction::~MachineCodeForInstruction() {
// Let go of all uses in temp. instructions
dropAllReferences();
-
+
// Free the Value objects created to hold intermediate values
for (unsigned i=0, N=tempVec.size(); i < N; i++)
delete tempVec[i];
-
+
// do not free the MachineInstr objects allocated. they are managed
// by the ilist in MachineBasicBlock
// Enter this object in the MachineCodeForInstr object of the CallInst.
// This transfers ownership of this object.
- MachineCodeForInstruction::get(callInstr).setCallArgsDescriptor(this);
+ MachineCodeForInstruction::get(callInstr).setCallArgsDescriptor(this);
}
CallInst *CallArgsDescriptor::getReturnValue() const {
/// the CallArgsDescriptor from the MachineCodeForInstruction object for the
/// CallInstr. This is roundabout but avoids adding a new map or annotation
/// just to keep track of CallArgsDescriptors.
-///
+///
CallArgsDescriptor *CallArgsDescriptor::get(const MachineInstr *MI) {
const Value *retAddrVal = 0;
if ((MI->getOperand (0).getType () == MachineOperand::MO_MachineRegister
const CallInst* callInstr = cast<CallInst>(retAddrReg->getOperand(0));
CallArgsDescriptor* desc =
- MachineCodeForInstruction::get(callInstr).getCallArgsDescriptor();
+ MachineCodeForInstruction::get(callInstr).getCallArgsDescriptor();
assert(desc->getCallInst()==callInstr && "Incorrect call args descriptor?");
return desc;
}
//===-- MachineCodeForInstruction.h -----------------------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
-// FIXME: This file is SparcV9 specific. Do not rely on this class for new
+// FIXME: This file is SparcV9 specific. Do not rely on this class for new
// targets, it will go away in the future.
//
// Representation of the sequence of machine instructions created for a single
// VM instruction. Additionally records information about hidden and implicit
// values used by the machine instructions: about hidden values used by the
// machine instructions:
-//
+//
// "Temporary values" are intermediate values used in the machine instruction
// sequence, but not in the VM instruction Note that such values should be
// treated as pure SSA values with no interpretation of their operands (i.e., as
// a TmpInstruction object which actually represents such a value).
-//
+//
// (2) "Implicit uses" are values used in the VM instruction but not in
// the machine instruction sequence
-//
+//
//===----------------------------------------------------------------------===//
#ifndef MACHINECODE_FOR_INSTRUCTION_H
public:
MachineCodeForInstruction() : callArgsDesc(NULL) {}
~MachineCodeForInstruction();
-
+
static MachineCodeForInstruction &get(const Instruction *I);
static void destroy(const Instruction *I);
}
iterator erase(iterator where) { return Contents.erase(where); }
iterator erase(iterator s, iterator e) { return Contents.erase(s, e); }
-
+
// dropAllReferences() - This function drops all references within
// temporary (hidden) instructions created in implementing the original
const std::vector<Value*> &getTempValues() const { return tempVec; }
std::vector<Value*> &getTempValues() { return tempVec; }
-
+
MachineCodeForInstruction &addTemp(Value *tmp) {
tempVec.push_back(tmp);
return *this;
//===-- SparcV9FunctionInfo.cpp -------------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This implements the SparcV9 specific MachineFunctionInfo class.
//
//===----------------------------------------------------------------------===//
unsigned &maxOptionalNumArgs)
{
unsigned maxSize = 0;
-
+
for (Function::const_iterator BB = F->begin(), BBE = F->end(); BB !=BBE; ++BB)
for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I)
if (const CallInst *callInst = dyn_cast<CallInst>(I))
int numExtra = numOperands-6;
if (numExtra <= 0)
continue;
-
+
unsigned sizeForThisCall = numExtra * 8;
-
+
if (maxSize < sizeForThisCall)
maxSize = sizeForThisCall;
-
+
if ((int)maxOptionalNumArgs < numExtra)
maxOptionalNumArgs = (unsigned) numExtra;
}
-
+
return maxSize;
}
// This function is similar to the corresponding function in EmitAssembly.cpp
// but they are unrelated. This one does not align at more than a
// double-word boundary whereas that one might.
-//
+//
inline unsigned
SizeToAlignment(unsigned size, const TargetMachine& target)
{
assert(! automaticVarsAreaFrozen &&
"Size of auto vars area has been used to compute an offset so "
"no more automatic vars should be allocated!");
-
+
// Check if we've allocated a stack slot for this value already
- //
+ //
hash_map<const Value*, int>::const_iterator pair = offsets.find(val);
if (pair != offsets.end())
return pair->second;
assert(! spillsAreaFrozen &&
"Size of reg spills area has been used to compute an offset so "
"no more register spill slots should be allocated!");
-
+
unsigned size = MF.getTarget().getTargetData().getTypeSize(type);
unsigned char align = MF.getTarget().getTargetData().getTypeAlignment(type);
-
+
bool growUp;
int firstOffset = MF.getTarget().getFrameInfo()->getRegSpillAreaOffset(MF, growUp);
-
+
int offset = growUp? firstOffset + getRegSpillsSize()
: firstOffset - (getRegSpillsSize() + size);
int aligned = MF.getTarget().getFrameInfo()->adjustAlignment(offset, growUp, align);
size += abs(aligned - offset); // include alignment padding in size
-
+
incrementRegSpillsSize(size); // update size of reg. spills area
return aligned;
//===-- SparcV9FunctionInfo.h -----------------------------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This class keeps track of information about the stack frame and about the
// per-function constant pool.
//
// FIXME: This class is completely SparcV9 specific. Do not use it for future
// targets. This file will be eliminated in future versions of LLVM.
-//
+//
//===----------------------------------------------------------------------===//
#ifndef MACHINEFUNCTIONINFO_H
//
// Accessors for global information about generated code for a method.
- //
+ //
bool isCompiledAsLeafMethod() const { return compiledAsLeaf; }
unsigned getStaticStackSize() const { return staticStackSize; }
unsigned getAutomaticVarsSize() const { return automaticVarsSize; }
const hash_set<const Constant*> &getConstantPoolValues() const {
return constantsForConstPool;
}
-
+
//
// Modifiers used during code generation
- //
+ //
void initializeFrameLayout ();
-
+
void addToConstantPool (const Constant* constVal) {
constantsForConstPool.insert(constVal);
}
-
+
void markAsLeafMethod() { compiledAsLeaf = true; }
-
+
int computeOffsetforLocalVar (const Value* local,
unsigned& getPaddedSize,
unsigned sizeToUse = 0);
int allocateLocalVar (const Value* local,
unsigned sizeToUse = 0);
-
+
int allocateSpilledValue (const Type* type);
int pushTempValue (unsigned size);
void popAllTempValues ();
-
- void freezeSpillsArea () { spillsAreaFrozen = true; }
+
+ void freezeSpillsArea () { spillsAreaFrozen = true; }
void freezeAutomaticVarsArea () { automaticVarsAreaFrozen=true; }
-
+
private:
void incrementAutomaticVarsSize(int incr) {
automaticVarsSize+= incr;
//===-- MachineInstrAnnot.h -------------------------------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Annotations used to pass information between SparcV9 code generation phases.
-//
+//
//===----------------------------------------------------------------------===//
#ifndef MACHINEINSTRANNOT_H
static const unsigned char IntArgReg = 0x1;
static const unsigned char FPArgReg = 0x2;
static const unsigned char StackSlot = 0x4;
-
+
Value* argVal; // this argument
int argCopyReg; // register used for second copy of arg. when
// multiple copies must be passed in registers
unsigned char passingMethod; // flags recording passing methods
-
+
public:
// Constructors
CallArgInfo(Value* _argVal)
: argVal(_argVal), argCopyReg(SparcV9RegInfo::getInvalidRegNum()),
passingMethod(0x0) {}
-
+
CallArgInfo(const CallArgInfo& obj)
: argVal(obj.argVal), argCopyReg(obj.argCopyReg),
passingMethod(obj.passingMethod) {}
-
+
// Accessor methods
Value* getArgVal() { return argVal; }
int getArgCopy() { return argCopyReg; }
- bool usesIntArgReg() { return (bool) (passingMethod & IntArgReg);}
- bool usesFPArgReg() { return (bool) (passingMethod & FPArgReg); }
- bool usesStackSlot() { return (bool) (passingMethod & StackSlot);}
-
+ bool usesIntArgReg() { return (bool) (passingMethod & IntArgReg);}
+ bool usesFPArgReg() { return (bool) (passingMethod & FPArgReg); }
+ bool usesStackSlot() { return (bool) (passingMethod & StackSlot);}
+
// Modifier methods
void replaceArgVal(Value* newVal) { argVal = newVal; }
void setUseIntArgReg() { passingMethod |= IntArgReg; }
std::vector<CallArgInfo> argInfoVec; // Descriptor for each argument
CallInst* callInstr; // The call instruction == result value
- Value* funcPtr; // Pointer for indirect calls
+ Value* funcPtr; // Pointer for indirect calls
TmpInstruction* retAddrReg; // Tmp value for return address reg.
bool isVarArgs; // Is this a varargs call?
bool noPrototype; // Is this a call with no prototype?
-
+
public:
CallArgsDescriptor(CallInst* _callInstr, TmpInstruction* _retAddrReg,
bool _isVarArgs, bool _noPrototype);
-
+
// Accessor methods to retrieve information about the call
// Note that operands are numbered 1..#CallArgs
unsigned int getNumArgs() const { return argInfoVec.size(); }
bool hasNoPrototype() const { return noPrototype; }
// Mechanism to get the descriptor for a CALL MachineInstr.
- //
+ //
static CallArgsDescriptor *get(const MachineInstr* MI);
};
//===- MappingInfo.cpp - create LLVM info and output to .s file -----------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains a FunctionPass called MappingInfoAsmPrinter,
namespace llvm {
namespace {
- class MappingInfoAsmPrinter : public FunctionPass {
+ class MappingInfoAsmPrinter : public FunctionPass {
std::ostream &Out;
public:
MappingInfoAsmPrinter(std::ostream &out) : Out(out){}
// Now, write out the maps.
BBMIMap.dumpAssembly (Out);
- return false;
-}
+ return false;
+}
/// writeNumber - Write out the number X as a sequence of .byte
/// directives to the current output stream Out. This method performs a
create_BB_to_MInumber_Key(FI, BBkey);
selectOutputMap (Map);
- MachineFunction &MF = MachineFunction::get(&FI);
+ MachineFunction &MF = MachineFunction::get(&FI);
for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
BI != BE; ++BI, ++bb) {
MachineBasicBlock &miBB = *BI;
const std::string &symName) {
// Prologue:
// Output a comment describing the object.
- Out << "!" << comment << "\n";
+ Out << "!" << comment << "\n";
// Switch the current section to .rodata in the assembly output:
- Out << "\t.section \".rodata\"\n\t.align 8\n";
+ Out << "\t.section \".rodata\"\n\t.align 8\n";
// Output a global symbol naming the object:
- Out << "\t.global " << symName << "\n";
- Out << "\t.type " << symName << ",#object\n";
- Out << symName << ":\n";
+ Out << "\t.global " << symName << "\n";
+ Out << "\t.type " << symName << ",#object\n";
+ Out << symName << ":\n";
}
static void writeEpilogue (std::ostream &Out, const std::string &symName) {
// Epilogue:
// Output a local symbol marking the end of the object:
- Out << ".end_" << symName << ":\n";
+ Out << ".end_" << symName << ":\n";
// Output size directive giving the size of the object:
Out << "\t.size " << symName << ", .end_" << symName << "-" << symName
<< "\n";
///
bool MappingInfoAsmPrinter::doFinalization (Module &M) {
unsigned f;
-
+
writePrologue(Out, "FUNCTION TO BB MAP", "FunctionBB");
f=0;
for(Module::iterator FI = M.begin (), FE = M.end (); FE != FI; ++FI) {
++f;
}
writeEpilogue(Out, "FunctionBB");
-
+
return false;
}
//===- lib/Target/SparcV9/MappingInfo.h -------------------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Data structures to support the Reoptimizer's Instruction-to-MachineInstr
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-//
-//
-//
-//
+//
+//
+//
+//
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "ModuloSched"
///
namespace llvm {
FunctionPass *createDependenceAnalyzer() {
- return new DependenceAnalyzer();
+ return new DependenceAnalyzer();
}
}
bool DependenceAnalyzer::runOnFunction(Function &F) {
AA = &getAnalysis<AliasAnalysis>();
TD = &getAnalysis<TargetData>();
-
+
return false;
}
static RegisterAnalysis<DependenceAnalyzer>X("depanalyzer", "Dependence Analyzer");
-
+
DependenceResult DependenceAnalyzer::getDependenceInfo(Instruction *inst1, Instruction *inst2) {
std::vector<Dependence> deps;
DEBUG(std::cerr << "Inst1: " << *inst1 << "\n");
DEBUG(std::cerr << "Inst2: " << *inst2 << "\n");
-
+
if(LoadInst *ldInst = dyn_cast<LoadInst>(inst1)) {
if(AA->alias(ldOp, (unsigned)TD->getTypeSize(ldOp->getType()),
stOp,(unsigned)TD->getTypeSize(stOp->getType()))
!= AliasAnalysis::NoAlias) {
-
+
//Anti Dep
deps.push_back(Dependence(0, Dependence::AntiDep));
}
}
else if(StoreInst *stInst = dyn_cast<StoreInst>(inst1)) {
-
+
if(LoadInst *ldInst = dyn_cast<LoadInst>(inst2)) {
//Get load mem ref
Value *ldOp = ldInst->getOperand(0);
if(AA->alias(ldOp, (unsigned)TD->getTypeSize(ldOp->getType()),
stOp,(unsigned)TD->getTypeSize(stOp->getType()))
!= AliasAnalysis::NoAlias) {
-
+
//Anti Dep
deps.push_back(Dependence(0, Dependence::TrueDep));
}
//Get store mem ref
Value *stOp2 = stInst2->getOperand(1);
-
+
if(AA->alias(stOp1, (unsigned)TD->getTypeSize(stOp1->getType()),
stOp2,(unsigned)TD->getTypeSize(stOp2->getType()))
!= AliasAnalysis::NoAlias) {
-
+
//Anti Dep
deps.push_back(Dependence(0, Dependence::OutputDep));
}
}
-
+
}
else
assert("Expected a load or a store\n");
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-//
-//
+//
+//
//===----------------------------------------------------------------------===//
#ifndef LLVM_DEPENDENCEANALYZER_H
//class to represent a dependence
struct Dependence {
-
+
enum DataDepType {
TrueDep, AntiDep, OutputDep, NonDateDep,
};
-
+
Dependence(int diff, DataDepType dep) : iteDiff(diff), depType(dep) {}
unsigned getIteDiff() { return iteDiff; }
unsigned getDepType() { return depType; }
-
+
private:
-
+
unsigned iteDiff;
unsigned depType;
};
-
+
struct DependenceResult {
std::vector<Dependence> dependences;
DependenceResult(const std::vector<Dependence> &d) : dependences(d) {}
class DependenceAnalyzer : public FunctionPass {
AliasAnalysis *AA;
TargetData *TD;
-
+
public:
DependenceAnalyzer() { AA = 0; TD = 0; }
virtual bool runOnFunction(Function &F);
virtual const char* getPassName() const { return "DependenceAnalyzer"; }
-
+
// getAnalysisUsage
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<AliasAnalysis>();
//
//===----------------------------------------------------------------------===//
//
-//
+//
//
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "ModuloSched"
//Returns a boolean indicating if the start cycle needs to be increased/decreased
bool MSSchedule::insert(MSchedGraphNode *node, int cycle) {
-
+
//First, check if the cycle has a spot free to start
if(schedule.find(cycle) != schedule.end()) {
//Check if we have a free issue slot at this cycle
DEBUG(std::cerr << "All issue slots taken\n");
return true;
-
+
}
void MSSchedule::addToSchedule(int cycle, MSchedGraphNode *node) {
std::vector<MSchedGraphNode*> nodes;
for(std::map<unsigned, MSchedGraphNode*>::iterator I = indexMap.begin(), E = indexMap.end(); I != E; ++I)
nodes.push_back(I->second);
-
+
schedule[cycle] = nodes;
}
bool MSSchedule::resourcesFree(MSchedGraphNode *node, int cycle) {
-
+
//Get Resource usage for this instruction
const TargetSchedInfo *msi = node->getParent()->getTarget()->getSchedInfo();
int currentCycle = cycle;
bool success = true;
-
+
//Get resource usage for this instruction
InstrRUsage rUsage = msi->getInstrRUsage(node->getInst()->getOpcode());
std::vector<std::vector<resourceId_t> > resources = rUsage.resourcesByCycle;
-
+
//Loop over resources in each cycle and increments their usage count
for(unsigned i=0; i < resources.size(); ++i) {
for(unsigned j=0; j < resources[i].size(); ++j) {
-
+
//Get Resource to check its availability
int resourceNum = resources[i][j];
-
+
DEBUG(std::cerr << "Attempting to schedule Resource Num: " << resourceNum << " in cycle: " << currentCycle << "\n");
-
+
//Check if this resource is available for this cycle
std::map<int, std::map<int,int> >::iterator resourcesForCycle = resourceNumPerCycle.find(currentCycle);
//Check if there are enough of this resource and if so, increase count and move on
if(resourceUse->second < CPUResource::getCPUResource(resourceNum)->maxNumUsers)
++resourceUse->second;
-
+
else {
DEBUG(std::cerr << "No resource num " << resourceNum << " available for cycle " << currentCycle << "\n");
success = false;
if(!success)
break;
-
+
//Increase cycle
currentCycle++;
}
-
+
if(!success) {
int oldCycle = cycle;
DEBUG(std::cerr << "Backtrack\n");
//Get resource usage for this instruction
InstrRUsage rUsage = msi->getInstrRUsage(node->getInst()->getOpcode());
std::vector<std::vector<resourceId_t> > resources = rUsage.resourcesByCycle;
-
+
//Loop over resources in each cycle and increments their usage count
for(unsigned i=0; i < resources.size(); ++i) {
if(oldCycle < currentCycle) {
oldCycle++;
}
return false;
-
+
}
return true;
}
bool MSSchedule::constructKernel(int II, std::vector<MSchedGraphNode*> &branches, std::map<const MachineInstr*, unsigned> &indVar) {
-
+
//Our schedule is allowed to have negative numbers, so lets calculate this offset
int offset = schedule.begin()->first;
if(offset > 0)
int maxSN = 0;
DEBUG(std::cerr << "Number of Stages: " << stageNum << "\n");
-
+
for(int index = offset; index < (II+offset); ++index) {
int count = 0;
- for(int i = index; i <= (schedule.rbegin()->first); i+=II) {
+ for(int i = index; i <= (schedule.rbegin()->first); i+=II) {
if(schedule.count(i)) {
- for(std::vector<MSchedGraphNode*>::iterator I = schedule[i].begin(),
+ for(std::vector<MSchedGraphNode*>::iterator I = schedule[i].begin(),
E = schedule[i].end(); I != E; ++I) {
//Check if its a branch
if((*I)->isBranch()) {
indVar.erase(N->second);
}
}
-
+
kernel.push_back(std::make_pair((MachineInstr*) I->first->getInst(), I->second));
}
void MSSchedule::print(std::ostream &os) const {
os << "Schedule:\n";
-
+
for(schedule_const_iterator I = schedule.begin(), E = schedule.end(); I != E; ++I) {
os << "Cycle: " << I->first << "\n";
for(std::vector<MSchedGraphNode*>::const_iterator node = I->second.begin(), nodeEnd = I->second.end(); node != nodeEnd; ++node)
E = kernel.end(); I != E; ++I)
os << "Node: " << *(I->first) << " Stage: " << I->second << "\n";
}
-
+
class MSSchedule {
std::map<int, std::vector<MSchedGraphNode*> > schedule;
unsigned numIssue;
-
+
//Internal map to keep track of explicit resources
std::map<int, std::map<int, int> > resourceNumPerCycle;
bool constructKernel(int II, std::vector<MSchedGraphNode*> &branches, std::map<const MachineInstr*, unsigned> &indVar);
int getMaxStage() { return maxStage; }
-
+
//iterators
typedef std::map<int, std::vector<MSchedGraphNode*> >::iterator schedule_iterator;
typedef std::map<int, std::vector<MSchedGraphNode*> >::const_iterator schedule_const_iterator;
typedef std::vector<std::pair<MachineInstr*, int> >::const_iterator kernel_const_iterator;
kernel_iterator kernel_begin() { return kernel.begin(); }
kernel_iterator kernel_end() { return kernel.end(); }
-
+
};
}
// A graph class for dependencies. This graph only contains true, anti, and
// output data dependencies for a given MachineBasicBlock. Dependencies
// across iterations are also computed. Unless data dependence analysis
-// is provided, a conservative approach of adding dependencies between all
+// is provided, a conservative approach of adding dependencies between all
// loads and stores is taken.
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "ModuloSched"
using namespace llvm;
//MSchedGraphNode constructor
-MSchedGraphNode::MSchedGraphNode(const MachineInstr* inst,
+MSchedGraphNode::MSchedGraphNode(const MachineInstr* inst,
MSchedGraph *graph, unsigned idx,
- unsigned late, bool isBranch)
+ unsigned late, bool isBranch)
: Inst(inst), Parent(graph), index(idx), latency(late), isBranchInstr(isBranch) {
//Add to the graph
}
//MSchedGraphNode copy constructor
-MSchedGraphNode::MSchedGraphNode(const MSchedGraphNode &N)
+MSchedGraphNode::MSchedGraphNode(const MSchedGraphNode &N)
: Predecessors(N.Predecessors), Successors(N.Successors) {
Inst = N.Inst;
//Print the node (instruction and latency)
void MSchedGraphNode::print(std::ostream &os) const {
- os << "MSchedGraphNode: Inst=" << *Inst << ", latency= " << latency << "\n";
+ os << "MSchedGraphNode: Inst=" << *Inst << ", latency= " << latency << "\n";
}
MSchedGraphEdge MSchedGraphNode::getInEdge(MSchedGraphNode *pred) {
//Loop over all the successors of our predecessor
//return the edge the corresponds to this in edge
- for (MSchedGraphNode::succ_iterator I = pred->succ_begin(),
+ for (MSchedGraphNode::succ_iterator I = pred->succ_begin(),
E = pred->succ_end(); I != E; ++I) {
if (*I == this)
return I.getEdge();
//Add a node to the graph
void MSchedGraph::addNode(const MachineInstr *MI,
MSchedGraphNode *node) {
-
- //Make sure node does not already exist
- assert(GraphMap.find(MI) == GraphMap.end()
+
+ //Make sure node does not already exist
+ assert(GraphMap.find(MI) == GraphMap.end()
&& "New MSchedGraphNode already exists for this instruction");
-
+
GraphMap[MI] = node;
}
//Delete a node to the graph
void MSchedGraph::deleteNode(MSchedGraphNode *node) {
-
+
//Delete the edge to this node from all predecessors
while(node->pred_size() > 0) {
- //DEBUG(std::cerr << "Delete edge from: " << **P << " to " << *node << "\n");
+ //DEBUG(std::cerr << "Delete edge from: " << **P << " to " << *node << "\n");
MSchedGraphNode *pred = *(node->pred_begin());
pred->deleteSuccessor(node);
}
-
+
//Remove this node from the graph
GraphMap.erase(node->getInst());
//Create a graph for a machine block. The ignoreInstrs map is so that we ignore instructions
//associated to the index variable since this is a special case in Modulo Scheduling.
//We only want to deal with the body of the loop.
-MSchedGraph::MSchedGraph(const MachineBasicBlock *bb, const TargetMachine &targ,
- std::map<const MachineInstr*, unsigned> &ignoreInstrs,
+MSchedGraph::MSchedGraph(const MachineBasicBlock *bb, const TargetMachine &targ,
+ std::map<const MachineInstr*, unsigned> &ignoreInstrs,
DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm
)
: BB(bb), Target(targ) {
-
- //Make sure BB is not null,
+
+ //Make sure BB is not null,
assert(BB != NULL && "Basic Block is null");
-
+
//DEBUG(std::cerr << "Constructing graph for " << bb << "\n");
//Create nodes and edges for this BB
}
//Copies the graph and keeps a map from old to new nodes
-MSchedGraph::MSchedGraph(const MSchedGraph &G, std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes)
+MSchedGraph::MSchedGraph(const MSchedGraph &G, std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes)
: BB(G.BB), Target(G.Target) {
-
+
std::map<MSchedGraphNode*, MSchedGraphNode*> oldToNew;
//Copy all nodes
- for(MSchedGraph::const_iterator N = G.GraphMap.begin(), NE = G.GraphMap.end();
+ for(MSchedGraph::const_iterator N = G.GraphMap.begin(), NE = G.GraphMap.end();
N != NE; ++N) {
MSchedGraphNode *newNode = new MSchedGraphNode(*(N->second));
oldToNew[&*(N->second)] = newNode;
newNodes[newNode] = &*(N->second);
GraphMap[&*(N->first)] = newNode;
}
-
+
//Loop over nodes and update edges to point to new nodes
for(MSchedGraph::iterator N = GraphMap.begin(), NE = GraphMap.end(); N != NE; ++N) {
-
+
//Get the node we are dealing with
MSchedGraphNode *node = &*(N->second);
for(unsigned i = 0; i < node->pred_size(); ++i) {
node->setPredecessor(i, oldToNew[node->getPredecessor(i)]);
}
-
+
for(unsigned i = 0; i < node->succ_size(); ++i) {
MSchedGraphEdge *edge = node->getSuccessor(i);
MSchedGraphNode *oldDest = edge->getDest();
edge->setDest(oldToNew[oldDest]);
}
- }
+ }
}
//Deconstructor, deletes all nodes in the graph
//Experimental code to add edges from the branch to all nodes dependent upon it.
-void hasPath(MSchedGraphNode *node, std::set<MSchedGraphNode*> &visited,
+void hasPath(MSchedGraphNode *node, std::set<MSchedGraphNode*> &visited,
std::set<MSchedGraphNode*> &branches, MSchedGraphNode *startNode,
std::set<std::pair<MSchedGraphNode*,MSchedGraphNode*> > &newEdges ) {
MSchedGraphNode *dest = edge->getDest();
if(branches.count(dest))
newEdges.insert(std::make_pair(dest, startNode));
-
+
//only visit if we have not already
else if(!visited.count(dest)) {
if(edge->getIteDiff() == 0)
//Spit out all edges we are going to add
unsigned min = GraphMap.size();
if(newEdges.size() == 1) {
- ((newEdges.begin())->first)->addOutEdge(((newEdges.begin())->second),
- MSchedGraphEdge::BranchDep,
+ ((newEdges.begin())->first)->addOutEdge(((newEdges.begin())->second),
+ MSchedGraphEdge::BranchDep,
MSchedGraphEdge::NonDataDep, 1);
}
else {
-
+
unsigned count = 0;
MSchedGraphNode *start;
MSchedGraphNode *end;
for(std::set<std::pair<MSchedGraphNode*, MSchedGraphNode*> >::iterator I = newEdges.begin(), E = newEdges.end(); I != E; ++I) {
-
+
DEBUG(std::cerr << "Branch Edge from: " << *(I->first) << " to " << *(I->second) << "\n");
-
+
// if(I->second->getIndex() <= min) {
start = I->first;
end = I->second;
//min = I->second->getIndex();
//}
- start->addOutEdge(end,
- MSchedGraphEdge::BranchDep,
+ start->addOutEdge(end,
+ MSchedGraphEdge::BranchDep,
MSchedGraphEdge::NonDataDep, 1);
}
}
void MSchedGraph::buildNodesAndEdges(std::map<const MachineInstr*, unsigned> &ignoreInstrs,
DependenceAnalyzer &DA,
std::map<MachineInstr*, Instruction*> &machineTollvm) {
-
+
//Get Machine target information for calculating latency
const TargetInstrInfo *MTI = Target.getInstrInfo();
//Get each instruction of machine basic block, get the delay
//using the op code, create a new node for it, and add to the
//graph.
-
+
MachineOpCode opCode = MI->getOpcode();
int delay;
#endif
//Get delay
delay = MTI->maxLatency(opCode);
-
+
//Create new node for this machine instruction and add to the graph.
//Create only if not a nop
if(MTI->isNop(opCode))
continue;
-
+
//Sparc BE does not use PHI opcode, so assert on this case
assert(opCode != TargetInstrInfo::PHI && "Did not expect PHI opcode");
//Node is created and added to the graph automatically
MSchedGraphNode *node = new MSchedGraphNode(MI, this, index, delay, isBranch);
- DEBUG(std::cerr << "Created Node: " << *node << "\n");
+ DEBUG(std::cerr << "Created Node: " << *node << "\n");
- //Check OpCode to keep track of memory operations to add memory dependencies later.
+ //Check OpCode to keep track of memory operations to add memory dependencies later.
if(MTI->isLoad(opCode) || MTI->isStore(opCode))
memInstructions.push_back(node);
for(unsigned i=0; i < MI->getNumOperands(); ++i) {
//Get Operand
const MachineOperand &mOp = MI->getOperand(i);
-
- //Check if it has an allocated register
+
+ //Check if it has an allocated register
if(mOp.hasAllocatedReg()) {
int regNum = mOp.getReg();
}
continue;
}
-
-
+
+
//Add virtual registers dependencies
//Check if any exist in the value map already and create dependencies
//between them.
DEBUG(std::cerr << "Read Operation in a PHI node\n");
continue;
}
-
+
if (const Value* srcI = mOp.getVRegValue()) {
-
+
//Find value in the map
- std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
+ std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
= valuetoNodeMap.find(srcI);
-
+
//If there is something in the map already, add edges from
//those instructions
//to this one we are processing
if(V != valuetoNodeMap.end()) {
addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs);
-
+
//Add to value map
V->second.push_back(std::make_pair(i,node));
}
//Put into value map
valuetoNodeMap[mOp.getVRegValue()].push_back(std::make_pair(i, node));
}
- }
+ }
}
++index;
}
if (const Value* srcI = mOp.getVRegValue()) {
//Find value in the map
- std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
+ std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
= valuetoNodeMap.find(srcI);
//If there is something in the map already, add edges from
}
}
}
- }
+ }
}
//Add dependencies for Value*s
void MSchedGraph::addValueEdges(std::vector<OpIndexNodePair> &NodesInMap,
- MSchedGraphNode *destNode, bool nodeIsUse,
+ MSchedGraphNode *destNode, bool nodeIsUse,
bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff) {
- for(std::vector<OpIndexNodePair>::iterator I = NodesInMap.begin(),
+ for(std::vector<OpIndexNodePair>::iterator I = NodesInMap.begin(),
E = NodesInMap.end(); I != E; ++I) {
-
+
//Get node in vectors machine operand that is the same value as node
MSchedGraphNode *srcNode = I->second;
MachineOperand mOp = srcNode->getInst()->getOperand(I->first);
if(nodeIsDef) {
if(mOp.isUse()) {
DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=anti)\n");
- srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
+ srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
MSchedGraphEdge::AntiDep, diff);
}
if(mOp.isDef()) {
DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=output)\n");
- srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
+ srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
MSchedGraphEdge::OutputDep, diff);
}
}
if(nodeIsUse) {
if(mOp.isDef()) {
DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=true)\n");
- srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
+ srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
MSchedGraphEdge::TrueDep, diff);
}
}
- }
+ }
}
//Add dependencies for machine registers across iterations
//Get Vector of nodes that use this register
std::vector<OpIndexNodePair> Nodes = (*I).second;
-
+
//Loop over nodes and determine the dependence between the other
//nodes in the vector
for(unsigned i =0; i < Nodes.size(); ++i) {
-
+
//Get src node operator index that uses this machine register
int srcOpIndex = Nodes[i].first;
-
+
//Get the actual src Node
MSchedGraphNode *srcNode = Nodes[i].second;
-
+
//Get Operand
const MachineOperand &srcMOp = srcNode->getInst()->getOperand(srcOpIndex);
-
+
bool srcIsUseandDef = srcMOp.isDef() && srcMOp.isUse();
bool srcIsUse = srcMOp.isUse() && !srcMOp.isDef();
-
-
+
+
//Look at all instructions after this in execution order
for(unsigned j=i+1; j < Nodes.size(); ++j) {
if(srcIsUse)
srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister,
MSchedGraphEdge::AntiDep);
-
+
else if(srcIsUseandDef) {
srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister,
MSchedGraphEdge::AntiDep);
-
+
srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister,
MSchedGraphEdge::OutputDep);
}
srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister,
MSchedGraphEdge::TrueDep);
}
-
+
}
-
+
//Look at all the instructions before this one since machine registers
//could live across iterations.
for(unsigned j = 0; j < i; ++j) {
if(srcIsUse)
srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister,
MSchedGraphEdge::AntiDep, 1);
-
+
else if(srcIsUseandDef) {
srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister,
MSchedGraphEdge::AntiDep, 1);
-
+
srcNode->addOutEdge(Nodes[j].second, MSchedGraphEdge::MachineRegister,
MSchedGraphEdge::OutputDep, 1);
}
}
}
-
+
}
-
+
}
//Add edges between all loads and stores
//Can be less strict with alias analysis and data dependence analysis.
-void MSchedGraph::addMemEdges(const std::vector<MSchedGraphNode*>& memInst, DependenceAnalyzer &DA,
+void MSchedGraph::addMemEdges(const std::vector<MSchedGraphNode*>& memInst, DependenceAnalyzer &DA,
std::map<MachineInstr*, Instruction*> &machineTollvm) {
//Get Target machine instruction info
const TargetInstrInfo *TMI = Target.getInstrInfo();
-
+
//Loop over all memory instructions in the vector
//Knowing that they are in execution, add true, anti, and output dependencies
for (unsigned srcIndex = 0; srcIndex < memInst.size(); ++srcIndex) {
//Get the machine opCode to determine type of memory instruction
MachineOpCode srcNodeOpCode = srcInst->getOpcode();
-
+
//All instructions after this one in execution order have an iteration delay of 0
for(unsigned destIndex = srcIndex + 1; destIndex < memInst.size(); ++destIndex) {
-
+
MachineInstr *destInst = (MachineInstr*) memInst[destIndex]->getInst();
-
+
DEBUG(std::cerr << "MInst1: " << *srcInst << "\n");
DEBUG(std::cerr << "Inst1: " << *machineTollvm[srcInst] << "\n");
DEBUG(std::cerr << "MInst2: " << *destInst << "\n");
for(std::vector<Dependence>::iterator d = dr.dependences.begin(), de = dr.dependences.end();
d != de; ++d) {
//Add edge from load to store
- memInst[srcIndex]->addOutEdge(memInst[destIndex],
- MSchedGraphEdge::MemoryDep,
+ memInst[srcIndex]->addOutEdge(memInst[destIndex],
+ MSchedGraphEdge::MemoryDep,
d->getDepType(), d->getIteDiff());
}
}
-
+
//All instructions before the src in execution order have an iteration delay of 1
for(unsigned destIndex = 0; destIndex < srcIndex; ++destIndex) {
-
+
MachineInstr *destInst = (MachineInstr*) memInst[destIndex]->getInst();
bool malias = false;
malias = true;
//Only add the edge if we can't verify that they do not alias
- /*if(AA.alias(mOp2.getVRegValue(),
+ /*if(AA.alias(mOp2.getVRegValue(),
(unsigned)TD.getTypeSize(mOp2.getVRegValue()->getType()),
- mOp.getVRegValue(),
+ mOp.getVRegValue(),
(unsigned)TD.getTypeSize(mOp.getVRegValue()->getType()))
!= AliasAnalysis::NoAlias) {*/
if(TMI->isStore(memInst[destIndex]->getInst()->getOpcode()))
- memInst[srcIndex]->addOutEdge(memInst[destIndex],
- MSchedGraphEdge::MemoryDep,
+ memInst[srcIndex]->addOutEdge(memInst[destIndex],
+ MSchedGraphEdge::MemoryDep,
MSchedGraphEdge::AntiDep, 1);
//}
}
malias = true;
//Only add the edge if we can't verify that they do not alias
- /*if(AA.alias(mOp2.getVRegValue(),
+ /*if(AA.alias(mOp2.getVRegValue(),
(unsigned)TD.getTypeSize(mOp2.getVRegValue()->getType()),
- mOp.getVRegValue(),
+ mOp.getVRegValue(),
(unsigned)TD.getTypeSize(mOp.getVRegValue()->getType()))
!= AliasAnalysis::NoAlias) {*/
if(TMI->isStore(memInst[destIndex]->getInst()->getOpcode()))
- memInst[srcIndex]->addOutEdge(memInst[destIndex],
- MSchedGraphEdge::MemoryDep,
+ memInst[srcIndex]->addOutEdge(memInst[destIndex],
+ MSchedGraphEdge::MemoryDep,
MSchedGraphEdge::OutputDep, 1);
else
- memInst[srcIndex]->addOutEdge(memInst[destIndex],
- MSchedGraphEdge::MemoryDep,
+ memInst[srcIndex]->addOutEdge(memInst[destIndex],
+ MSchedGraphEdge::MemoryDep,
MSchedGraphEdge::TrueDep, 1);
//}
}
-
+
}
-
+
}
}
// A graph class for dependencies. This graph only contains true, anti, and
// output data dependencies for a given MachineBasicBlock. Dependencies
// across iterations are also computed. Unless data dependence analysis
-// is provided, a conservative approach of adding dependencies between all
+// is provided, a conservative approach of adding dependencies between all
// loads and stores is taken.
//===----------------------------------------------------------------------===//
#include <vector>
namespace llvm {
-
+
class MSchedGraph;
class MSchedGraphNode;
template<class IteratorType, class NodeType>
enum DataDepOrderType {
TrueDep, AntiDep, OutputDep, NonDataDep
};
-
+
enum MSchedGraphEdgeType {
MemoryDep, ValueDep, MachineRegister, BranchDep
};
- //Get or set edge data
+ //Get or set edge data
MSchedGraphNode *getDest() const { return dest; }
unsigned getIteDiff() { return iteDiff; }
unsigned getDepOrderType() { return depOrderType; }
private:
friend class MSchedGraphNode;
- MSchedGraphEdge(MSchedGraphNode *destination, MSchedGraphEdgeType type,
- unsigned deptype, unsigned diff)
+ MSchedGraphEdge(MSchedGraphNode *destination, MSchedGraphEdgeType type,
+ unsigned deptype, unsigned diff)
: dest(destination), depType(type), depOrderType(deptype), iteDiff(diff) {}
-
+
MSchedGraphNode *dest;
MSchedGraphEdgeType depType;
unsigned depOrderType;
//corresponding latency. Each node also contains a list of its
//predecessors and sucessors.
class MSchedGraphNode {
-
+
const MachineInstr* Inst; //Machine Instruction
MSchedGraph* Parent; //Graph this node belongs to
unsigned index; //Index in BB
unsigned latency; //Latency of Instruction
bool isBranchInstr; //Is this node the branch instr or not
-
+
std::vector<MSchedGraphNode*> Predecessors; //Predecessor Nodes
std::vector<MSchedGraphEdge> Successors; //Successor edges
public:
- MSchedGraphNode(const MachineInstr *inst, MSchedGraph *graph,
+ MSchedGraphNode(const MachineInstr *inst, MSchedGraph *graph,
unsigned index, unsigned late=0, bool isBranch=false);
MSchedGraphNode(const MSchedGraphNode &N);
typedef std::vector<MSchedGraphNode*>::const_iterator pred_const_iterator;
pred_const_iterator pred_begin() const { return Predecessors.begin(); }
pred_const_iterator pred_end() const { return Predecessors.end(); }
-
+
typedef MSchedGraphNodeIterator<std::vector<MSchedGraphEdge>::const_iterator,
const MSchedGraphNode> succ_const_iterator;
succ_const_iterator succ_begin() const;
void setPredecessor(unsigned index, MSchedGraphNode *dest) {
Predecessors[index] = dest;
}
-
+
MSchedGraphNode* getPredecessor(unsigned index) {
return Predecessors[index];
}
-
+
MSchedGraphEdge* getSuccessor(unsigned index) {
return &Successors[index];
}
-
+
void deleteSuccessor(MSchedGraphNode *node) {
for (unsigned i = 0; i != Successors.size(); ++i)
if (Successors[i].getDest() == node) {
}
}
- void addOutEdge(MSchedGraphNode *destination,
- MSchedGraphEdge::MSchedGraphEdgeType type,
+ void addOutEdge(MSchedGraphNode *destination,
+ MSchedGraphEdge::MSchedGraphEdgeType type,
unsigned deptype, unsigned diff=0) {
Successors.push_back(MSchedGraphEdge(destination, type, deptype,diff));
destination->Predecessors.push_back(this);
return I->getDest();
}
NodeType* operator->() const { return operator*(); }
-
+
MSchedGraphNodeIterator& operator++() { // Preincrement
++I;
return *this;
}
MSchedGraphNodeIterator operator++(int) { // Postincrement
- MSchedGraphNodeIterator tmp = *this; ++*this; return tmp;
+ MSchedGraphNodeIterator tmp = *this; ++*this; return tmp;
}
MSchedGraphEdge &getEdge() {
}
// ostream << operator for MSGraphNode class
- inline std::ostream &operator<<(std::ostream &os,
+ inline std::ostream &operator<<(std::ostream &os,
const MSchedGraphNode &node) {
node.print(os);
return os;
template <> struct GraphTraits<MSchedGraphNode*> {
typedef MSchedGraphNode NodeType;
typedef MSchedGraphNode::succ_iterator ChildIteratorType;
-
- static inline ChildIteratorType child_begin(NodeType *N) {
- return N->succ_begin();
+
+ static inline ChildIteratorType child_begin(NodeType *N) {
+ return N->succ_begin();
}
- static inline ChildIteratorType child_end(NodeType *N) {
+ static inline ChildIteratorType child_end(NodeType *N) {
return N->succ_end();
}
static NodeType *getEntryNode(NodeType* N) { return N; }
};
-
+
//Graph class to represent dependence graph
class MSchedGraph {
-
+
const MachineBasicBlock *BB; //Machine basic block
const TargetMachine &Target; //Target Machine
-
+
//Nodes
std::map<const MachineInstr*, MSchedGraphNode*> GraphMap;
//Add Nodes and Edges to this graph for our BB
typedef std::pair<int, MSchedGraphNode*> OpIndexNodePair;
void buildNodesAndEdges(std::map<const MachineInstr*, unsigned> &ignoreInstrs, DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
- void addValueEdges(std::vector<OpIndexNodePair> &NodesInMap,
+ void addValueEdges(std::vector<OpIndexNodePair> &NodesInMap,
MSchedGraphNode *node,
bool nodeIsUse, bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff=0);
- void addMachRegEdges(std::map<int,
+ void addMachRegEdges(std::map<int,
std::vector<OpIndexNodePair> >& regNumtoNodeMap);
void addMemEdges(const std::vector<MSchedGraphNode*>& memInst,
DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
void addBranchEdges();
public:
- MSchedGraph(const MachineBasicBlock *bb, const TargetMachine &targ,
- std::map<const MachineInstr*, unsigned> &ignoreInstrs,
+ MSchedGraph(const MachineBasicBlock *bb, const TargetMachine &targ,
+ std::map<const MachineInstr*, unsigned> &ignoreInstrs,
DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
//Copy constructor with maps to link old nodes to new nodes
MSchedGraph(const MSchedGraph &G, std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes);
-
+
//Deconstructor!
~MSchedGraph();
-
+
//Add or delete nodes from the Graph
void addNode(const MachineInstr* MI, MSchedGraphNode *node);
void deleteNode(MSchedGraphNode *node);
- //iterators
+ //iterators
typedef std::map<const MachineInstr*, MSchedGraphNode*>::iterator iterator;
typedef std::map<const MachineInstr*, MSchedGraphNode*>::const_iterator const_iterator;
typedef std::map<const MachineInstr*, MSchedGraphNode*>::reverse_iterator reverse_iterator;
};
-
+
// Provide specializations of GraphTraits to be able to use graph
template <> struct GraphTraits<MSchedGraph*> {
typedef MSchedGraphNode NodeType;
typedef MSchedGraphNode::succ_iterator ChildIteratorType;
-
- static inline ChildIteratorType child_begin(NodeType *N) {
- return N->succ_begin();
+
+ static inline ChildIteratorType child_begin(NodeType *N) {
+ return N->succ_begin();
}
- static inline ChildIteratorType child_end(NodeType *N) {
+ static inline ChildIteratorType child_end(NodeType *N) {
return N->succ_end();
}
}
};
-
+
template <> struct GraphTraits<const MSchedGraph*> {
typedef const MSchedGraphNode NodeType;
typedef MSchedGraphNode::succ_const_iterator ChildIteratorType;
-
- static inline ChildIteratorType child_begin(NodeType *N) {
- return N->succ_begin();
+
+ static inline ChildIteratorType child_begin(NodeType *N) {
+ return N->succ_begin();
}
- static inline ChildIteratorType child_end(NodeType *N) {
+ static inline ChildIteratorType child_end(NodeType *N) {
return N->succ_end();
}
typedef std::pointer_to_unary_function<std::pair<const MachineInstr* const,
MSchedGraphNode*>&, MSchedGraphNode&> DerefFun;
-
+
typedef mapped_iterator<MSchedGraph::iterator, DerefFun> nodes_iterator;
static nodes_iterator nodes_begin(MSchedGraph *G) {
return map_iterator(((MSchedGraph*)G)->begin(), DerefFun(getSecond));
return map_iterator(((MSchedGraph*)G)->end(), DerefFun(getSecond));
}
};
-
+
template <> struct GraphTraits<Inverse<MSchedGraph*> > {
typedef MSchedGraphNode NodeType;
typedef MSchedGraphNode::pred_iterator ChildIteratorType;
-
- static inline ChildIteratorType child_begin(NodeType *N) {
+
+ static inline ChildIteratorType child_begin(NodeType *N) {
return N->pred_begin();
}
- static inline ChildIteratorType child_end(NodeType *N) {
+ static inline ChildIteratorType child_end(NodeType *N) {
return N->pred_end();
}
typedef std::pointer_to_unary_function<std::pair<const MachineInstr* const,
return map_iterator(((MSchedGraph*)G)->end(), DerefFun(getSecond));
}
};
-
+
template <> struct GraphTraits<Inverse<const MSchedGraph*> > {
typedef const MSchedGraphNode NodeType;
typedef MSchedGraphNode::pred_const_iterator ChildIteratorType;
-
- static inline ChildIteratorType child_begin(NodeType *N) {
+
+ static inline ChildIteratorType child_begin(NodeType *N) {
return N->pred_begin();
}
- static inline ChildIteratorType child_end(NodeType *N) {
+ static inline ChildIteratorType child_end(NodeType *N) {
return N->pred_end();
}
typedef std::pointer_to_unary_function<std::pair<const MachineInstr* const,
MSchedGraphNode*>&, MSchedGraphNode&> DerefFun;
-
+
typedef mapped_iterator<MSchedGraph::iterator, DerefFun> nodes_iterator;
static nodes_iterator nodes_begin(MSchedGraph *G) {
return map_iterator(((MSchedGraph*)G)->begin(), DerefFun(getSecond));
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-//
-// This ModuloScheduling pass is based on the Swing Modulo Scheduling
-// algorithm.
-//
+//
+// This ModuloScheduling pass is based on the Swing Modulo Scheduling
+// algorithm.
+//
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "ModuloSched"
///
FunctionPass *llvm::createModuloSchedulingPass(TargetMachine & targ) {
DEBUG(std::cerr << "Created ModuloSchedulingPass\n");
- return new ModuloSchedulingPass(targ);
+ return new ModuloSchedulingPass(targ);
}
std::string Filename = GraphName + ".dot";
O << "Writing '" << Filename << "'...";
std::ofstream F(Filename.c_str());
-
+
if (F.good())
WriteGraph(F, GT);
else
static std::string getGraphName(MSchedGraph *F) {
return "Dependence Graph";
}
-
+
static std::string getNodeLabel(MSchedGraphNode *Node, MSchedGraph *Graph) {
if (Node->getInst()) {
std::stringstream ss;
std::string edgelabel = "";
switch (I.getEdge().getDepOrderType()) {
- case MSchedGraphEdge::TrueDep:
+ case MSchedGraphEdge::TrueDep:
edgelabel = "True";
break;
-
- case MSchedGraphEdge::AntiDep:
+
+ case MSchedGraphEdge::AntiDep:
edgelabel = "Anti";
break;
- case MSchedGraphEdge::OutputDep:
+ case MSchedGraphEdge::OutputDep:
edgelabel = "Output";
break;
/// 1) Computation and Analysis of the dependence graph
/// 2) Ordering of the nodes
/// 3) Scheduling
-///
+///
bool ModuloSchedulingPass::runOnFunction(Function &F) {
alarm(300);
bool Changed = false;
int numMS = 0;
-
+
DEBUG(std::cerr << "Creating ModuloSchedGraph for each valid BasicBlock in " + F.getName() + "\n");
-
+
//Get MachineFunction
MachineFunction &MF = MachineFunction::get(&F);
-
+
DependenceAnalyzer &DA = getAnalysis<DependenceAnalyzer>();
-
+
//Worklist
std::vector<MachineBasicBlock*> Worklist;
-
+
//Iterate over BasicBlocks and put them into our worklist if they are valid
for (MachineFunction::iterator BI = MF.begin(); BI != MF.end(); ++BI)
- if(MachineBBisValid(BI)) {
+ if(MachineBBisValid(BI)) {
Worklist.push_back(&*BI);
++ValidLoops;
}
-
+
defaultInst = 0;
DEBUG(if(Worklist.size() == 0) std::cerr << "No single basic block loops in function to ModuloSchedule\n");
//Iterate over the worklist and perform scheduling
- for(std::vector<MachineBasicBlock*>::iterator BI = Worklist.begin(),
+ for(std::vector<MachineBasicBlock*>::iterator BI = Worklist.begin(),
BE = Worklist.end(); BI != BE; ++BI) {
//Print out BB for debugging
}
MSchedGraph *MSG = new MSchedGraph(*BI, target, indVarInstrs[*BI], DA, machineTollvm[*BI]);
-
+
//Write Graph out to file
DEBUG(WriteGraphToFile(std::cerr, F.getName(), MSG));
-
+
//Calculate Resource II
int ResMII = calculateResMII(*BI);
-
+
//Calculate Recurrence II
int RecMII = calculateRecMII(MSG, ResMII);
DEBUG(std::cerr << "Number of reccurrences found: " << recurrenceList.size() << "\n");
-
-
+
+
//Our starting initiation interval is the maximum of RecMII and ResMII
II = std::max(RecMII, ResMII);
-
+
//Print out II, RecMII, and ResMII
DEBUG(std::cerr << "II starts out as " << II << " ( RecMII=" << RecMII << " and ResMII=" << ResMII << ")\n");
-
+
//Dump node properties if in debug mode
- DEBUG(for(std::map<MSchedGraphNode*, MSNodeAttributes>::iterator I = nodeToAttributesMap.begin(),
+ DEBUG(for(std::map<MSchedGraphNode*, MSNodeAttributes>::iterator I = nodeToAttributesMap.begin(),
E = nodeToAttributesMap.end(); I !=E; ++I) {
- std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: "
- << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth
+ std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: "
+ << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth
<< " Height: " << I->second.height << "\n";
});
//Calculate Node Properties
calculateNodeAttributes(MSG, ResMII);
-
+
//Dump node properties if in debug mode
- DEBUG(for(std::map<MSchedGraphNode*, MSNodeAttributes>::iterator I = nodeToAttributesMap.begin(),
+ DEBUG(for(std::map<MSchedGraphNode*, MSNodeAttributes>::iterator I = nodeToAttributesMap.begin(),
E = nodeToAttributesMap.end(); I !=E; ++I) {
- std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: "
- << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth
+ std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: "
+ << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth
<< " Height: " << I->second.height << "\n";
});
-
+
//Put nodes in order to schedule them
computePartialOrder();
-
+
//Dump out partial order
- DEBUG(for(std::vector<std::set<MSchedGraphNode*> >::iterator I = partialOrder.begin(),
+ DEBUG(for(std::vector<std::set<MSchedGraphNode*> >::iterator I = partialOrder.begin(),
E = partialOrder.end(); I !=E; ++I) {
std::cerr << "Start set in PO\n";
for(std::set<MSchedGraphNode*>::iterator J = I->begin(), JE = I->end(); J != JE; ++J)
std::cerr << "PO:" << **J << "\n";
});
-
+
//Place nodes in final order
orderNodes();
-
+
//Dump out order of nodes
DEBUG(for(std::vector<MSchedGraphNode*>::iterator I = FinalNodeOrder.begin(), E = FinalNodeOrder.end(); I != E; ++I) {
std::cerr << "FO:" << **I << "\n";
});
-
+
//Finally schedule nodes
bool haveSched = computeSchedule(*BI);
-
+
//Print out final schedule
DEBUG(schedule.print(std::cerr));
-
+
//Final scheduling step is to reconstruct the loop only if we actual have
//stage > 0
if(haveSched) {
}
else
++NoSched;
-
+
//Clear out our maps for the next basic block that is processed
nodeToAttributesMap.clear();
partialOrder.clear();
//Should't std::find work??
//parent->getBasicBlockList().erase(std::find(parent->getBasicBlockList().begin(), parent->getBasicBlockList().end(), *llvmBB));
//parent->getBasicBlockList().erase(llvmBB);
-
+
//delete(llvmBB);
//delete(*BI);
}
- alarm(0);
+ alarm(0);
return Changed;
}
const MachineOperand &mOp = I->getOperand(opNum);
if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
//assert if this is the second def we have seen
- //DEBUG(std::cerr << "Putting " << *(mOp.getVRegValue()) << " into map\n");
+ //DEBUG(std::cerr << "Putting " << *(mOp.getVRegValue()) << " into map\n");
assert(!defMap.count(mOp.getVRegValue()) && "Def already in the map");
defMap[mOp.getVRegValue()] = &*I;
}
-
+
//See if we can use this Value* as our defaultInst
if(!defaultInst && mOp.getType() == MachineOperand::MO_VirtualRegister) {
Value *V = mOp.getVRegValue();
}
}
}
-
+
if(!defaultInst)
return false;
-
+
return true;
-
+
}
/// This function checks if a Machine Basic Block is valid for modulo
/// scheduling. This means that it has no control flow (if/else or
bool ModuloSchedulingPass::MachineBBisValid(const MachineBasicBlock *BI) {
bool isLoop = false;
-
+
//Check first if its a valid loop
- for(succ_const_iterator I = succ_begin(BI->getBasicBlock()),
+ for(succ_const_iterator I = succ_begin(BI->getBasicBlock()),
E = succ_end(BI->getBasicBlock()); I != E; ++I) {
if (*I == BI->getBasicBlock()) // has single block loop
isLoop = true;
}
-
+
if(!isLoop)
return false;
//Get Target machine instruction info
const TargetInstrInfo *TMI = target.getInstrInfo();
-
+
//Check each instruction and look for calls, keep map to get index later
std::map<const MachineInstr*, unsigned> indexMap;
for(MachineBasicBlock::const_iterator I = BI->begin(), E = BI->end(); I != E; ++I) {
//Get opcode to check instruction type
MachineOpCode OC = I->getOpcode();
-
+
//Look for calls
if(TMI->isCall(OC))
return false;
-
+
//Look for conditional move
- if(OC == V9::MOVRZr || OC == V9::MOVRZi || OC == V9::MOVRLEZr || OC == V9::MOVRLEZi
+ if(OC == V9::MOVRZr || OC == V9::MOVRZi || OC == V9::MOVRLEZr || OC == V9::MOVRLEZi
|| OC == V9::MOVRLZr || OC == V9::MOVRLZi || OC == V9::MOVRNZr || OC == V9::MOVRNZi
- || OC == V9::MOVRGZr || OC == V9::MOVRGZi || OC == V9::MOVRGEZr
+ || OC == V9::MOVRGZr || OC == V9::MOVRGZi || OC == V9::MOVRGEZr
|| OC == V9::MOVRGEZi || OC == V9::MOVLEr || OC == V9::MOVLEi || OC == V9::MOVLEUr
|| OC == V9::MOVLEUi || OC == V9::MOVFLEr || OC == V9::MOVFLEi
|| OC == V9::MOVNEr || OC == V9::MOVNEi || OC == V9::MOVNEGr || OC == V9::MOVNEGi
|| OC == V9::MOVFNEr || OC == V9::MOVFNEi)
return false;
-
+
indexMap[I] = count;
if(TMI->isNop(OC))
//Convert list of LLVM Instructions to list of Machine instructions
std::map<const MachineInstr*, unsigned> mIndVar;
for(std::set<Instruction*>::iterator N = indVar.begin(), NE = indVar.end(); N != NE; ++N) {
-
+
//If we have a load, we can't handle this loop because there is no way to preserve dependences
//between loads and stores
if(isa<LoadInst>(*N))
return true;
}
-bool ModuloSchedulingPass::assocIndVar(Instruction *I, std::set<Instruction*> &indVar,
+bool ModuloSchedulingPass::assocIndVar(Instruction *I, std::set<Instruction*> &indVar,
std::vector<Instruction*> &stack, BasicBlock *BB) {
stack.push_back(I);
//FIXME: In future there should be a way to get alternative resources
//for each instruction
int ModuloSchedulingPass::calculateResMII(const MachineBasicBlock *BI) {
-
+
TIME_REGION(X, "calculateResMII");
const TargetInstrInfo *mii = target.getInstrInfo();
const TargetSchedInfo *msi = target.getSchedInfo();
int ResMII = 0;
-
+
//Map to keep track of usage count of each resource
std::map<unsigned, unsigned> resourceUsageCount;
}
//Find maximum usage count
-
+
//Get max number of instructions that can be issued at once. (FIXME)
int issueSlots = msi->maxNumIssueTotal;
for(std::map<unsigned,unsigned>::iterator RB = resourceUsageCount.begin(), RE = resourceUsageCount.end(); RB != RE; ++RB) {
-
+
//Get the total number of the resources in our cpu
int resourceNum = CPUResource::getCPUResource(RB->first)->maxNumUsers;
-
+
//Get total usage count for this resources
unsigned usageCount = RB->second;
-
+
//Divide the usage count by either the max number we can issue or the number of
//resources (whichever is its upper bound)
double finalUsageCount;
finalUsageCount = ceil(1.0 * usageCount / resourceNum);
else
finalUsageCount = ceil(1.0 * usageCount / issueSlots);
-
-
+
+
//Only keep track of the max
ResMII = std::max( (int) finalUsageCount, ResMII);
findAllReccurrences(I->second, vNodes, MII);
vNodes.clear();
}*/
-
+
TIME_REGION(X, "calculateRecMII");
findAllCircuits(graph, MII);
int RecMII = 0;
-
+
for(std::set<std::pair<int, std::vector<MSchedGraphNode*> > >::iterator I = recurrenceList.begin(), E=recurrenceList.end(); I !=E; ++I) {
RecMII = std::max(RecMII, I->first);
}
-
+
return MII;
}
//Assert if its already in the map
assert(nodeToAttributesMap.count(I->second) == 0 &&
"Node attributes are already in the map");
-
+
//Put into the map with default attribute values
nodeToAttributesMap[I->second] = MSNodeAttributes();
}
//Create set to deal with reccurrences
std::set<MSchedGraphNode*> visitedNodes;
-
+
//Now Loop over map and calculate the node attributes
for(std::map<MSchedGraphNode*, MSNodeAttributes>::iterator I = nodeToAttributesMap.begin(), E = nodeToAttributesMap.end(); I != E; ++I) {
calculateASAP(I->first, MII, (MSchedGraphNode*) 0);
visitedNodes.clear();
}
-
+
int maxASAP = findMaxASAP();
//Calculate ALAP which depends on ASAP being totally calculated
for(std::map<MSchedGraphNode*, MSNodeAttributes>::iterator I = nodeToAttributesMap.begin(), E = nodeToAttributesMap.end(); I != E; ++I) {
//Calculate MOB which depends on ASAP being totally calculated, also do depth and height
for(std::map<MSchedGraphNode*, MSNodeAttributes>::iterator I = nodeToAttributesMap.begin(), E = nodeToAttributesMap.end(); I != E; ++I) {
(I->second).MOB = std::max(0,(I->second).ALAP - (I->second).ASAP);
-
+
DEBUG(std::cerr << "MOB: " << (I->second).MOB << " (" << *(I->first) << ")\n");
calculateDepth(I->first, (MSchedGraphNode*) 0);
calculateHeight(I->first, (MSchedGraphNode*) 0);
bool ModuloSchedulingPass::ignoreEdge(MSchedGraphNode *srcNode, MSchedGraphNode *destNode) {
if(destNode == 0 || srcNode ==0)
return false;
-
+
bool findEdge = edgesToIgnore.count(std::make_pair(srcNode, destNode->getInEdgeNum(srcNode)));
-
+
DEBUG(std::cerr << "Ignoring edge? from: " << *srcNode << " to " << *destNode << "\n");
return findEdge;
}
-/// calculateASAP - Calculates the
+/// calculateASAP - Calculates the
int ModuloSchedulingPass::calculateASAP(MSchedGraphNode *node, int MII, MSchedGraphNode *destNode) {
-
+
DEBUG(std::cerr << "Calculating ASAP for " << *node << "\n");
//Get current node attributes
if(attributes.ASAP != -1)
return attributes.ASAP;
-
+
int maxPredValue = 0;
-
+
//Iterate over all of the predecessors and find max
for(MSchedGraphNode::pred_iterator P = node->pred_begin(), E = node->pred_end(); P != E; ++P) {
-
+
//Only process if we are not ignoring the edge
if(!ignoreEdge(*P, node)) {
int predASAP = -1;
predASAP = calculateASAP(*P, MII, node);
-
+
assert(predASAP != -1 && "ASAP has not been calculated");
int iteDiff = node->getInEdge(*P).getIteDiff();
-
+
int currentPredValue = predASAP + (*P)->getLatency() - (iteDiff * MII);
DEBUG(std::cerr << "pred ASAP: " << predASAP << ", iteDiff: " << iteDiff << ", PredLatency: " << (*P)->getLatency() << ", Current ASAP pred: " << currentPredValue << "\n");
maxPredValue = std::max(maxPredValue, currentPredValue);
}
}
-
+
attributes.ASAP = maxPredValue;
DEBUG(std::cerr << "ASAP: " << attributes.ASAP << " (" << *node << ")\n");
-
+
return maxPredValue;
}
-int ModuloSchedulingPass::calculateALAP(MSchedGraphNode *node, int MII,
+int ModuloSchedulingPass::calculateALAP(MSchedGraphNode *node, int MII,
int maxASAP, MSchedGraphNode *srcNode) {
-
+
DEBUG(std::cerr << "Calculating ALAP for " << *node << "\n");
-
+
MSNodeAttributes &attributes = nodeToAttributesMap.find(node)->second;
-
+
if(attributes.ALAP != -1)
return attributes.ALAP;
-
+
if(node->hasSuccessors()) {
-
+
//Trying to deal with the issue where the node has successors, but
//we are ignoring all of the edges to them. So this is my hack for
//now.. there is probably a more elegant way of doing this (FIXME)
//FIXME, set to something high to start
int minSuccValue = 9999999;
-
+
//Iterate over all of the predecessors and fine max
- for(MSchedGraphNode::succ_iterator P = node->succ_begin(),
+ for(MSchedGraphNode::succ_iterator P = node->succ_begin(),
E = node->succ_end(); P != E; ++P) {
-
+
//Only process if we are not ignoring the edge
if(!ignoreEdge(node, *P)) {
processedOneEdge = true;
minSuccValue = std::min(minSuccValue, currentSuccValue);
}
}
-
+
if(processedOneEdge)
attributes.ALAP = minSuccValue;
-
+
else
attributes.ALAP = maxASAP;
}
int ModuloSchedulingPass::calculateHeight(MSchedGraphNode *node,MSchedGraphNode *srcNode) {
-
+
MSNodeAttributes &attributes = nodeToAttributesMap.find(node)->second;
if(attributes.height != -1)
return attributes.height;
int maxHeight = 0;
-
+
//Iterate over all of the predecessors and find max
- for(MSchedGraphNode::succ_iterator P = node->succ_begin(),
+ for(MSchedGraphNode::succ_iterator P = node->succ_begin(),
E = node->succ_end(); P != E; ++P) {
-
-
+
+
if(!ignoreEdge(node, *P)) {
int succHeight = calculateHeight(*P, node);
}
-int ModuloSchedulingPass::calculateDepth(MSchedGraphNode *node,
+int ModuloSchedulingPass::calculateDepth(MSchedGraphNode *node,
MSchedGraphNode *destNode) {
MSNodeAttributes &attributes = nodeToAttributesMap.find(node)->second;
return attributes.depth;
int maxDepth = 0;
-
+
//Iterate over all of the predecessors and fine max
for(MSchedGraphNode::pred_iterator P = node->pred_begin(), E = node->pred_end(); P != E; ++P) {
if(!ignoreEdge(*P, node)) {
int predDepth = -1;
predDepth = calculateDepth(*P, node);
-
+
assert(predDepth != -1 && "Predecessors ASAP should have been caclulated");
int currentDepth = predDepth + (*P)->getLatency();
}
}
attributes.depth = maxDepth;
-
+
DEBUG(std::cerr << "Depth: " << attributes.depth << " (" << *node << "*)\n");
return maxDepth;
}
//Loop over all recurrences already in our list
for(std::set<std::pair<int, std::vector<MSchedGraphNode*> > >::iterator R = recurrenceList.begin(), RE = recurrenceList.end(); R != RE; ++R) {
-
+
bool all_same = true;
//First compare size
if(R->second.size() == recurrence.size()) {
-
+
for(std::vector<MSchedGraphNode*>::const_iterator node = R->second.begin(), end = R->second.end(); node != end; ++node) {
if(std::find(recurrence.begin(), recurrence.end(), *node) == recurrence.end()) {
all_same = all_same && false;
}
}
}
-
+
if(!same) {
srcBENode = recurrence.back();
destBENode = recurrence.front();
-
+
//FIXME
if(destBENode->getInEdge(srcBENode).getIteDiff() == 0) {
//DEBUG(std::cerr << "NOT A BACKEDGE\n");
- //find actual backedge HACK HACK
+ //find actual backedge HACK HACK
for(unsigned i=0; i< recurrence.size()-1; ++i) {
if(recurrence[i+1]->getInEdge(recurrence[i]).getIteDiff() == 1) {
srcBENode = recurrence[i];
destBENode = recurrence[i+1];
break;
}
-
+
}
-
+
}
DEBUG(std::cerr << "Back Edge to Remove: " << *srcBENode << " to " << *destBENode << "\n");
edgesToIgnore.insert(std::make_pair(srcBENode, destBENode->getInEdgeNum(srcBENode)));
recurrenceList.insert(std::make_pair(II, recurrence));
}
-
+
}
int CircCount;
}
-bool ModuloSchedulingPass::circuit(MSchedGraphNode *v, std::vector<MSchedGraphNode*> &stack,
- std::set<MSchedGraphNode*> &blocked, std::vector<MSchedGraphNode*> &SCC,
- MSchedGraphNode *s, std::map<MSchedGraphNode*, std::set<MSchedGraphNode*> > &B,
+bool ModuloSchedulingPass::circuit(MSchedGraphNode *v, std::vector<MSchedGraphNode*> &stack,
+ std::set<MSchedGraphNode*> &blocked, std::vector<MSchedGraphNode*> &SCC,
+ MSchedGraphNode *s, std::map<MSchedGraphNode*, std::set<MSchedGraphNode*> > &B,
int II, std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes) {
bool f = false;
-
+
DEBUG(std::cerr << "Finding Circuits Starting with: ( " << v << ")"<< *v << "\n");
//Push node onto the stack
for(std::set<MSchedGraphNode*>::iterator I = AkV.begin(), E = AkV.end(); I != E; ++I) {
if(*I == s) {
//We have a circuit, so add it to our list
-
+
std::vector<MSchedGraphNode*> recc;
//Dump recurrence for now
DEBUG(std::cerr << "Starting Recc\n");
int value = totalDelay-(RecMII * totalDistance);
int lastII = II;
while(value <= 0) {
-
+
lastII = RecMII;
RecMII--;
value = totalDelay-(RecMII * totalDistance);
unblock(v, blocked, B);
}
else {
- for(std::set<MSchedGraphNode*>::iterator I = AkV.begin(), E = AkV.end(); I != E; ++I)
+ for(std::set<MSchedGraphNode*>::iterator I = AkV.begin(), E = AkV.end(); I != E; ++I)
B[*I].insert(v);
}
CircCount = 0;
- //Keep old to new node mapping information
+ //Keep old to new node mapping information
std::map<MSchedGraphNode*, MSchedGraphNode*> newNodes;
//copy the graph
//Iterate over the graph until its down to one node or empty
while(MSG->size() > 1) {
-
+
//Write Graph out to file
//WriteGraphToFile(std::cerr, "Graph" + utostr(MSG->size()), MSG);
}
}
}
-
-
+
+
//Process SCC
DEBUG(for(std::vector<MSchedGraphNode*>::iterator N = Vk.begin(), NE = Vk.end();
N != NE; ++N) { std::cerr << *((*N)->getInst()); });
-
+
//Iterate over all nodes in this scc
for(std::vector<MSchedGraphNode*>::iterator N = Vk.begin(), NE = Vk.end();
N != NE; ++N) {
}
if(Vk.size() > 1) {
circuit(s, stack, blocked, Vk, s, B, II, newNodes);
-
+
//Find all nodes up to s and delete them
std::vector<MSchedGraphNode*> nodesToRemove;
nodesToRemove.push_back(s);
}
-void ModuloSchedulingPass::findAllReccurrences(MSchedGraphNode *node,
+void ModuloSchedulingPass::findAllReccurrences(MSchedGraphNode *node,
std::vector<MSchedGraphNode*> &visitedNodes,
int II) {
-
+
if(std::find(visitedNodes.begin(), visitedNodes.end(), node) != visitedNodes.end()) {
std::vector<MSchedGraphNode*> recurrence;
MSchedGraphNode *last = node;
MSchedGraphNode *srcBackEdge = 0;
MSchedGraphNode *destBackEdge = 0;
-
+
for(std::vector<MSchedGraphNode*>::iterator I = visitedNodes.begin(), E = visitedNodes.end();
I !=E; ++I) {
- if(*I == node)
+ if(*I == node)
first = false;
if(first)
continue;
}
-
+
//Get final distance calc
distance += node->getInEdge(last).getIteDiff();
DEBUG(std::cerr << "Reccurrence Distance: " << distance << "\n");
//Adjust II until we get close to the inequality delay - II*distance <= 0
-
+
int value = delay-(RecMII * distance);
int lastII = II;
while(value <= 0) {
-
+
lastII = RecMII;
RecMII--;
value = delay-(RecMII * distance);
}
-
-
+
+
DEBUG(std::cerr << "Final II for this recurrence: " << lastII << "\n");
addReccurrence(recurrence, lastII, srcBackEdge, destBackEdge);
assert(distance != 0 && "Recurrence distance should not be zero");
}
}
-void ModuloSchedulingPass::searchPath(MSchedGraphNode *node,
+void ModuloSchedulingPass::searchPath(MSchedGraphNode *node,
std::vector<MSchedGraphNode*> &path,
std::set<MSchedGraphNode*> &nodesToAdd) {
//Push node onto the path
path.push_back(node);
- //Loop over all successors and see if there is a path from this node to
+ //Loop over all successors and see if there is a path from this node to
//a recurrence in the partial order, if so.. add all nodes to be added to recc
- for(MSchedGraphNode::succ_iterator S = node->succ_begin(), SE = node->succ_end(); S != SE;
+ for(MSchedGraphNode::succ_iterator S = node->succ_begin(), SE = node->succ_end(); S != SE;
++S) {
//If this node exists in a recurrence already in the partial order, then add all
//nodes in the path to the set of nodes to add
//Check if its already in our partial order, if not add it to the final vector
- for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
+ for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
PE = partialOrder.end(); PO != PE; ++PO) {
-
+
//Check if we should ignore this edge first
if(ignoreEdge(node,*S))
continue;
searchPath(*S, path, nodesToAdd);
}
}
-
+
//Pop Node off the path
path.pop_back();
}
-void ModuloSchedulingPass::pathToRecc(MSchedGraphNode *node,
+void ModuloSchedulingPass::pathToRecc(MSchedGraphNode *node,
std::vector<MSchedGraphNode*> &path,
std::set<MSchedGraphNode*> &poSet,
std::set<MSchedGraphNode*> &lastNodes) {
DEBUG(std::cerr << "Current node: " << *node << "\n");
- //Loop over all successors and see if there is a path from this node to
+ //Loop over all successors and see if there is a path from this node to
//a recurrence in the partial order, if so.. add all nodes to be added to recc
- for(MSchedGraphNode::succ_iterator S = node->succ_begin(), SE = node->succ_end(); S != SE;
+ for(MSchedGraphNode::succ_iterator S = node->succ_begin(), SE = node->succ_end(); S != SE;
++S) {
DEBUG(std::cerr << "Succ:" << **S << "\n");
//Check if we should ignore this edge first
if(ignoreEdge(node,*S))
continue;
-
+
if(poSet.count(*S)) {
DEBUG(std::cerr << "Found path to recc from no pred\n");
//Loop over path, if it exists in lastNodes, then add to poset, and remove from lastNodes
else
pathToRecc(*S, path, poSet, lastNodes);
}
-
+
//Pop Node off the path
path.pop_back();
}
void ModuloSchedulingPass::computePartialOrder() {
TIME_REGION(X, "calculatePartialOrder");
-
+
//Only push BA branches onto the final node order, we put other branches after it
//FIXME: Should we really be pushing branches on it a specific order instead of relying
//on BA being there?
std::vector<MSchedGraphNode*> branches;
-
+
//Steps to add a recurrence to the partial order
// 1) Find reccurrence with the highest RecMII. Add it to the partial order.
// 2) For each recurrence with decreasing RecMII, add it to the partial order along with
// any nodes that connect this recurrence to recurrences already in the partial order
- for(std::set<std::pair<int, std::vector<MSchedGraphNode*> > >::reverse_iterator
+ for(std::set<std::pair<int, std::vector<MSchedGraphNode*> > >::reverse_iterator
I = recurrenceList.rbegin(), E=recurrenceList.rend(); I !=E; ++I) {
std::set<MSchedGraphNode*> new_recurrence;
//Loop through recurrence and remove any nodes already in the partial order
- for(std::vector<MSchedGraphNode*>::const_iterator N = I->second.begin(),
+ for(std::vector<MSchedGraphNode*>::const_iterator N = I->second.begin(),
NE = I->second.end(); N != NE; ++N) {
bool found = false;
- for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
+ for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
PE = partialOrder.end(); PO != PE; ++PO) {
if(PO->count(*N))
found = true;
}
}
-
+
if(new_recurrence.size() > 0) {
-
+
std::vector<MSchedGraphNode*> path;
std::set<MSchedGraphNode*> nodesToAdd;
for(std::set<MSchedGraphNode*>::iterator N = new_recurrence.begin(),
NE = new_recurrence.end(); N != NE; ++N)
searchPath(*N, path, nodesToAdd);
-
+
//Add nodes to this recurrence if they are not already in the partial order
for(std::set<MSchedGraphNode*>::iterator N = nodesToAdd.begin(), NE = nodesToAdd.end();
N != NE; ++N) {
bool found = false;
- for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
+ for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
PE = partialOrder.end(); PO != PE; ++PO) {
if(PO->count(*N))
found = true;
}
}
-
+
//Add any nodes that are not already in the partial order
//Add them in a set, one set per connected component
std::set<MSchedGraphNode*> lastNodes;
std::set<MSchedGraphNode*> noPredNodes;
- for(std::map<MSchedGraphNode*, MSNodeAttributes>::iterator I = nodeToAttributesMap.begin(),
+ for(std::map<MSchedGraphNode*, MSNodeAttributes>::iterator I = nodeToAttributesMap.begin(),
E = nodeToAttributesMap.end(); I != E; ++I) {
-
+
bool found = false;
-
+
//Check if its already in our partial order, if not add it to the final vector
- for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
+ for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
PE = partialOrder.end(); PO != PE; ++PO) {
if(PO->count(I->first))
found = true;
/*for(std::set<MSchedGraphNode*>::iterator N = noPredNodes.begin(), NE = noPredNodes.end();
N != NE; ++N) {
DEBUG(std::cerr << "No Pred Path from: " << **N << "\n");
- for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
+ for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
PE = partialOrder.end(); PO != PE; ++PO) {
std::vector<MSchedGraphNode*> path;
pathToRecc(*N, path, *PO, lastNodes);
}
}*/
-
+
//Break up remaining nodes that are not in the partial order
///into their connected compoenents
if(ccSet.size() > 0)
partialOrder.push_back(ccSet);
}
-
-
+
+
//Clean up branches by putting them in final order
assert(branches.size() == 0 && "We should not have any branches in our graph");
}
}
else
return;
-
+
//Loop over successors and recurse if we have not seen this node before
for(MSchedGraphNode::succ_iterator node_succ = node->succ_begin(), end=node->succ_end(); node_succ != end; ++node_succ) {
connectedComponentSet(*node_succ, ccSet, lastNodes);
}
-
+
}
void ModuloSchedulingPass::predIntersect(std::set<MSchedGraphNode*> &CurrentSet, std::set<MSchedGraphNode*> &IntersectResult) {
-
+
for(unsigned j=0; j < FinalNodeOrder.size(); ++j) {
- for(MSchedGraphNode::pred_iterator P = FinalNodeOrder[j]->pred_begin(),
+ for(MSchedGraphNode::pred_iterator P = FinalNodeOrder[j]->pred_begin(),
E = FinalNodeOrder[j]->pred_end(); P != E; ++P) {
-
+
//Check if we are supposed to ignore this edge or not
if(ignoreEdge(*P,FinalNodeOrder[j]))
continue;
-
+
if(CurrentSet.count(*P))
if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end())
IntersectResult.insert(*P);
}
- }
+ }
}
-
+
void ModuloSchedulingPass::succIntersect(std::set<MSchedGraphNode*> &CurrentSet, std::set<MSchedGraphNode*> &IntersectResult) {
for(unsigned j=0; j < FinalNodeOrder.size(); ++j) {
- for(MSchedGraphNode::succ_iterator P = FinalNodeOrder[j]->succ_begin(),
+ for(MSchedGraphNode::succ_iterator P = FinalNodeOrder[j]->succ_begin(),
E = FinalNodeOrder[j]->succ_end(); P != E; ++P) {
//Check if we are supposed to ignore this edge or not
void ModuloSchedulingPass::orderNodes() {
-
+
TIME_REGION(X, "orderNodes");
int BOTTOM_UP = 0;
//Set default order
int order = BOTTOM_UP;
-
+
//Loop over all the sets and place them in the final node order
for(std::vector<std::set<MSchedGraphNode*> >::iterator CurrentSet = partialOrder.begin(), E= partialOrder.end(); CurrentSet != E; ++CurrentSet) {
//Get node attributes
MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*J)->second;
//assert(nodeAttr != nodeToAttributesMap.end() && "Node not in attributes map!");
-
+
if(maxASAP <= nodeAttr.ASAP) {
maxASAP = nodeAttr.ASAP;
node = *J;
order = BOTTOM_UP;
}
}
-
+
//Repeat until all nodes are put into the final order from current set
while(IntersectCurrent.size() > 0) {
while(IntersectCurrent.size() > 0) {
DEBUG(std::cerr << "Intersection is not empty, so find heighest height\n");
-
+
int MOB = 0;
int height = 0;
MSchedGraphNode *highestHeightNode = *(IntersectCurrent.begin());
-
+
//Find node in intersection with highest heigh and lowest MOB
- for(std::set<MSchedGraphNode*>::iterator I = IntersectCurrent.begin(),
+ for(std::set<MSchedGraphNode*>::iterator I = IntersectCurrent.begin(),
E = IntersectCurrent.end(); I != E; ++I) {
-
+
//Get current nodes properties
MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*I)->second;
}
}
}
-
+
//Append our node with greatest height to the NodeOrder
if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestHeightNode) == FinalNodeOrder.end()) {
DEBUG(std::cerr << "Adding node to Final Order: " << *highestHeightNode << "\n");
}
//Remove V from IntersectOrder
- IntersectCurrent.erase(std::find(IntersectCurrent.begin(),
+ IntersectCurrent.erase(std::find(IntersectCurrent.begin(),
IntersectCurrent.end(), highestHeightNode));
//Intersect V's successors with CurrentSet
for(MSchedGraphNode::succ_iterator P = highestHeightNode->succ_begin(),
E = highestHeightNode->succ_end(); P != E; ++P) {
- //if(lower_bound(CurrentSet->begin(),
+ //if(lower_bound(CurrentSet->begin(),
// CurrentSet->end(), *P) != CurrentSet->end()) {
- if(std::find(CurrentSet->begin(), CurrentSet->end(), *P) != CurrentSet->end()) {
+ if(std::find(CurrentSet->begin(), CurrentSet->end(), *P) != CurrentSet->end()) {
if(ignoreEdge(highestHeightNode, *P))
continue;
//If not already in Intersect, add
int MOB = 0;
int depth = 0;
MSchedGraphNode *highestDepthNode = *(IntersectCurrent.begin());
-
- for(std::set<MSchedGraphNode*>::iterator I = IntersectCurrent.begin(),
+
+ for(std::set<MSchedGraphNode*>::iterator I = IntersectCurrent.begin(),
E = IntersectCurrent.end(); I != E; ++I) {
//Find node attribute in graph
MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*I)->second;
-
+
if(depth < nodeAttr.depth) {
highestDepthNode = *I;
depth = nodeAttr.depth;
}
}
}
-
-
+
+
//Append highest depth node to the NodeOrder
if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestDepthNode) == FinalNodeOrder.end()) {
}
//Remove heightestDepthNode from IntersectOrder
IntersectCurrent.erase(highestDepthNode);
-
+
//Intersect heightDepthNode's pred with CurrentSet
- for(MSchedGraphNode::pred_iterator P = highestDepthNode->pred_begin(),
+ for(MSchedGraphNode::pred_iterator P = highestDepthNode->pred_begin(),
E = highestDepthNode->pred_end(); P != E; ++P) {
if(CurrentSet->count(*P)) {
if(ignoreEdge(*P, highestDepthNode))
continue;
-
+
//If not already in Intersect, add
if(!IntersectCurrent.count(*P))
IntersectCurrent.insert(*P);
}
}
-
+
} //End while loop over Intersect Size
//Change order
DEBUG(std::cerr << "Current Intersection Size: " << IntersectCurrent.size() << "\n");
}
//End Wrapping while loop
- DEBUG(std::cerr << "Ending Size of Current Set: " << CurrentSet->size() << "\n");
+ DEBUG(std::cerr << "Ending Size of Current Set: " << CurrentSet->size() << "\n");
}//End for over all sets of nodes
-
+
//FIXME: As the algorithm stands it will NEVER add an instruction such as ba (with no
//data dependencies) to the final order. We add this manually. It will always be
//in the last set of S since its not part of a recurrence
TIME_REGION(X, "computeSchedule");
bool success = false;
-
+
//FIXME: Should be set to max II of the original loop
//Cap II in order to prevent infinite loop
int capII = 100;
std::vector<MSchedGraphNode*> branches;
//Loop over the final node order and process each node
- for(std::vector<MSchedGraphNode*>::iterator I = FinalNodeOrder.begin(),
+ for(std::vector<MSchedGraphNode*>::iterator I = FinalNodeOrder.begin(),
E = FinalNodeOrder.end(); I != E; ++I) {
-
+
//CalculateEarly and Late start
int EarlyStart = -1;
int LateStart = 99999; //Set to something higher then we would ever expect (FIXME)
if(sched) {
//Loop over nodes in the schedule and determine if they are predecessors
//or successors of the node we are trying to schedule
- for(MSSchedule::schedule_iterator nodesByCycle = schedule.begin(), nodesByCycleEnd = schedule.end();
+ for(MSSchedule::schedule_iterator nodesByCycle = schedule.begin(), nodesByCycleEnd = schedule.end();
nodesByCycle != nodesByCycleEnd; ++nodesByCycle) {
-
+
//For this cycle, get the vector of nodes schedule and loop over it
for(std::vector<MSchedGraphNode*>::iterator schedNode = nodesByCycle->second.begin(), SNE = nodesByCycle->second.end(); schedNode != SNE; ++schedNode) {
-
+
if((*I)->isPredecessor(*schedNode)) {
int diff = (*I)->getInEdge(*schedNode).getIteDiff();
int ES_Temp = nodesByCycle->first + (*schedNode)->getLatency() - diff * II;
count--;
}
-
+
//Check if the node has no pred or successors and set Early Start to its ASAP
if(!hasSucc && !hasPred)
EarlyStart = nodeToAttributesMap.find(*I)->second.ASAP;
-
+
DEBUG(std::cerr << "Has Successors: " << hasSucc << ", Has Pred: " << hasPred << "\n");
DEBUG(std::cerr << "EarlyStart: " << EarlyStart << ", LateStart: " << LateStart << "\n");
}
else
success = scheduleNode(*I, EarlyStart, EarlyStart + II - 1);
-
+
if(!success) {
++IncreasedII;
- ++II;
+ ++II;
schedule.clear();
break;
}
-
+
}
if(success) {
}
DEBUG(std::cerr << "Final II: " << II << "\n");
}
-
+
if(II >= capII) {
DEBUG(std::cerr << "Maximum II reached, giving up\n");
return false;
}
assert(II < capII && "The II should not exceed the original loop number of cycles");
- }
+ }
return true;
}
-bool ModuloSchedulingPass::scheduleNode(MSchedGraphNode *node,
+bool ModuloSchedulingPass::scheduleNode(MSchedGraphNode *node,
int start, int end) {
bool success = false;
//Make sure start and end are not negative
//if(start < 0) {
//start = 0;
-
+
//}
//if(end < 0)
//end = 0;
while(increaseSC) {
-
+
increaseSC = false;
increaseSC = schedule.insert(node, cycle);
-
- if(!increaseSC)
+
+ if(!increaseSC)
return true;
//Increment cycle to try again
for(MSSchedule::kernel_iterator I = schedule.kernel_begin(), E = schedule.kernel_end(); I != E; ++I) {
maxStageCount = std::max(maxStageCount, I->second);
-
+
//Put int the map so we know what instructions in each stage are in the kernel
DEBUG(std::cerr << "Inserting instruction " << *(I->first) << " into map at stage " << I->second << "\n");
inKernel[I->second].insert(I->first);
for(int i = 0; i < maxStageCount; ++i) {
BasicBlock *llvmBB = new BasicBlock("PROLOGUE", (Function*) (origBB->getBasicBlock()->getParent()));
MachineBasicBlock *machineBB = new MachineBasicBlock(llvmBB);
-
+
DEBUG(std::cerr << "i=" << i << "\n");
for(int j = i; j >= 0; --j) {
for(MachineBasicBlock::const_iterator MI = origBB->begin(), ME = origBB->end(); ME != MI; ++MI) {
//If its a branch, insert a nop
if(mii->isBranch(instClone->getOpcode()))
BuildMI(machineBB, V9::NOP, 0);
-
-
+
+
DEBUG(std::cerr << "Cloning: " << *MI << "\n");
//After cloning, we may need to save the value that this instruction defines
for(unsigned opNum=0; opNum < MI->getNumOperands(); ++opNum) {
Instruction *tmp;
-
+
//get machine operand
MachineOperand &mOp = instClone->getOperand(opNum);
if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
saveValue = BuildMI(machineBB, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else
+ else
saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
/*for(std::vector<MSchedGraphNode*>::iterator BR = branches.begin(), BE = branches.end(); BR != BE; ++BR) {
-
+
//Stick in branch at the end
machineBB->push_back((*BR)->getInst()->clone());
}*/
- (((MachineBasicBlock*)origBB)->getParent())->getBasicBlockList().push_back(machineBB);
+ (((MachineBasicBlock*)origBB)->getParent())->getBasicBlockList().push_back(machineBB);
prologues.push_back(machineBB);
llvm_prologues.push_back(llvmBB);
}
}
void ModuloSchedulingPass::writeEpilogues(std::vector<MachineBasicBlock *> &epilogues, const MachineBasicBlock *origBB, std::vector<BasicBlock*> &llvm_epilogues, std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave, std::map<Value*, std::map<int, Value*> > &newValues,std::map<Value*, MachineBasicBlock*> &newValLocation, std::map<Value*, std::map<int, Value*> > &kernelPHIs ) {
-
+
std::map<int, std::set<const MachineInstr*> > inKernel;
-
+
for(MSSchedule::kernel_iterator I = schedule.kernel_begin(), E = schedule.kernel_end(); I != E; ++I) {
-
+
//Ignore the branch, we will handle this separately
//if(I->first->isBranch())
//continue;
for(int i = schedule.getMaxStage()-1; i >= 0; --i) {
BasicBlock *llvmBB = new BasicBlock("EPILOGUE", (Function*) (origBB->getBasicBlock()->getParent()));
MachineBasicBlock *machineBB = new MachineBasicBlock(llvmBB);
-
+
DEBUG(std::cerr << " Epilogue #: " << i << "\n");
if(inKernel[j].count(&*MI)) {
DEBUG(std::cerr << "Cloning instruction " << *MI << "\n");
MachineInstr *clone = MI->clone();
-
+
//Update operands that need to use the result from the phi
for(unsigned opNum=0; opNum < clone->getNumOperands(); ++opNum) {
//get machine operand
const MachineOperand &mOp = clone->getOperand(opNum);
-
+
if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse())) {
-
+
DEBUG(std::cerr << "Writing PHI for " << (mOp.getVRegValue()) << "\n");
-
+
//If this is the last instructions for the max iterations ago, don't update operands
if(inEpilogue.count(mOp.getVRegValue()))
if(inEpilogue[mOp.getVRegValue()] == i)
continue;
-
+
//Quickly write appropriate phis for this operand
if(newValues.count(mOp.getVRegValue())) {
if(newValues[mOp.getVRegValue()].count(i)) {
Instruction *tmp = new TmpInstruction(newValues[mOp.getVRegValue()][i]);
-
+
//Get machine code for this instruction
MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
tempMvec.addTemp((Value*) tmp);
valPHIs[mOp.getVRegValue()] = tmp;
}
}
-
+
if(valPHIs.count(mOp.getVRegValue())) {
//Update the operand in the cloned instruction
- clone->getOperand(opNum).setValueReg(valPHIs[mOp.getVRegValue()]);
+ clone->getOperand(opNum).setValueReg(valPHIs[mOp.getVRegValue()]);
}
}
else if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef())) {
(((MachineBasicBlock*)origBB)->getParent())->getBasicBlockList().push_back(machineBB);
epilogues.push_back(machineBB);
llvm_epilogues.push_back(llvmBB);
-
+
DEBUG(std::cerr << "EPILOGUE #" << i << "\n");
DEBUG(machineBB->print(std::cerr));
}
}
void ModuloSchedulingPass::writeKernel(BasicBlock *llvmBB, MachineBasicBlock *machineBB, std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave, std::map<Value*, std::map<int, Value*> > &newValues, std::map<Value*, MachineBasicBlock*> &newValLocation, std::map<Value*, std::map<int, Value*> > &kernelPHIs) {
-
+
//Keep track of operands that are read and saved from a previous iteration. The new clone
//instruction will use the result of the phi instead.
std::map<Value*, Value*> finalPHIValue;
//Get target information to look at machine operands
const TargetInstrInfo *mii = target.getInstrInfo();
-
+
//Create TmpInstructions for the final phis
for(MSSchedule::kernel_iterator I = schedule.kernel_begin(), E = schedule.kernel_end(); I != E; ++I) {
branches.push_back(instClone);
continue;
}*/
-
+
//Clone instruction
const MachineInstr *inst = I->first;
MachineInstr *instClone = inst->clone();
for(unsigned i=0; i < inst->getNumOperands(); ++i) {
//get machine operand
const MachineOperand &mOp = inst->getOperand(i);
-
+
if(I->second != 0) {
if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
//Check if we already have a final PHI value for this
if(!finalPHIValue.count(mOp.getVRegValue())) {
TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
-
+
//Get machine code for this instruction
MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
tempMvec.addTemp((Value*) tmp);
-
+
//Update the operand in the cloned instruction
instClone->getOperand(i).setValueReg(tmp);
-
+
//save this as our final phi
finalPHIValue[mOp.getVRegValue()] = tmp;
newValLocation[tmp] = machineBB;
}
else {
//Use the previous final phi value
- instClone->getOperand(i).setValueReg(finalPHIValue[mOp.getVRegValue()]);
+ instClone->getOperand(i).setValueReg(finalPHIValue[mOp.getVRegValue()]);
}
}
}
if(I->second != schedule.getMaxStage()) {
if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
if(valuesToSave.count(mOp.getVRegValue())) {
-
+
TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
-
+
//Get machine code for this instruction
MachineCodeForInstruction & tempVec = MachineCodeForInstruction::get(defaultInst);
tempVec.addTemp((Value*) tmp);
saveValue = BuildMI(machineBB, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else
+ else
saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
-
-
+
+
//Save for future cleanup
kernelValue[mOp.getVRegValue()] = tmp;
newValLocation[tmp] = machineBB;
}
}
}
-
+
}
//Add branches
//Loop over each value we need to generate phis for
- for(std::map<Value*, std::map<int, Value*> >::iterator V = newValues.begin(),
+ for(std::map<Value*, std::map<int, Value*> >::iterator V = newValues.begin(),
E = newValues.end(); V != E; ++V) {
DEBUG(std::cerr << "Writing phi for" << *(V->first));
DEBUG(std::cerr << "\nMap of Value* for this phi\n");
- DEBUG(for(std::map<int, Value*>::iterator I = V->second.begin(),
- IE = V->second.end(); I != IE; ++I) {
+ DEBUG(for(std::map<int, Value*>::iterator I = V->second.begin(),
+ IE = V->second.end(); I != IE; ++I) {
std::cerr << "Stage: " << I->first;
std::cerr << " Value: " << *(I->second) << "\n";
});
//If we only have one current iteration live, its safe to set lastPhi = to kernel value
if(V->second.size() == 1) {
assert(kernelValue[V->first] != 0 && "Kernel value* must exist to create phi");
- MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(),V9::PHI, 3).addReg(V->second.begin()->second).addReg(kernelValue[V->first]).addRegDef(finalPHIValue[V->first]);
+ MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(),V9::PHI, 3).addReg(V->second.begin()->second).addReg(kernelValue[V->first]).addRegDef(finalPHIValue[V->first]);
DEBUG(std::cerr << "Resulting PHI (one live): " << *saveValue << "\n");
kernelPHIs[V->first][V->second.begin()->first] = kernelValue[V->first];
DEBUG(std::cerr << "Put kernel phi in at stage: " << schedule.getMaxStage()-1 << " (map stage = " << V->second.begin()->first << ")\n");
//Keep track of last phi created.
Instruction *lastPhi = 0;
-
+
unsigned count = 1;
//Loop over the the map backwards to generate phis
- for(std::map<int, Value*>::reverse_iterator I = V->second.rbegin(), IE = V->second.rend();
+ for(std::map<int, Value*>::reverse_iterator I = V->second.rbegin(), IE = V->second.rend();
I != IE; ++I) {
if(count < (V->second).size()) {
//Get machine code for this instruction
MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
tempMvec.addTemp((Value*) tmp);
-
+
MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(tmp);
DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
}
}
- }
+ }
DEBUG(std::cerr << "KERNEL after PHIs\n");
DEBUG(machineBB->print(std::cerr));
//Worklist of TmpInstructions that need to be added to a MCFI
std::vector<Instruction*> addToMCFI;
-
+
//Worklist to add OR instructions to end of kernel so not to invalidate the iterator
//std::vector<std::pair<Instruction*, Value*> > newORs;
//Start with the kernel and for each phi insert a copy for the phi def and for each arg
for(MachineBasicBlock::iterator I = kernelBB->begin(), E = kernelBB->end(); I != E; ++I) {
-
+
DEBUG(std::cerr << "Looking at Instr: " << *I << "\n");
//Get op code and check if its a phi
if(I->getOpcode() == V9::PHI) {
-
+
DEBUG(std::cerr << "Replacing PHI: " << *I << "\n");
Instruction *tmp = 0;
BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else
+ else
BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
-
+
break;
}
-
+
}
}
BuildMI(*kernelBB, I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
else if(tmp->getType() == Type::DoubleTy)
BuildMI(*kernelBB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
- else
+ else
BuildMI(*kernelBB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue());
-
-
+
+
worklist.push_back(std::make_pair(kernelBB, I));
}
}
-
+
}
-
+
}
//Add TmpInstructions to some MCFI
//Remove phis from epilogue
for(std::vector<MachineBasicBlock*>::iterator MB = epilogues.begin(), ME = epilogues.end(); MB != ME; ++MB) {
for(MachineBasicBlock::iterator I = (*MB)->begin(), E = (*MB)->end(); I != E; ++I) {
-
+
DEBUG(std::cerr << "Looking at Instr: " << *I << "\n");
//Get op code and check if its a phi
if(I->getOpcode() == V9::PHI) {
//Get Operand
const MachineOperand &mOp = I->getOperand(i);
assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n");
-
+
if(!tmp) {
tmp = new TmpInstruction(mOp.getVRegValue());
addToMCFI.push_back(tmp);
}
-
+
//Now for all our arguments we read, OR to the new TmpInstruction that we created
if(mOp.isUse()) {
DEBUG(std::cerr << "Use: " << mOp << "\n");
BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else
+ else
BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
break;
}
-
+
}
-
+
}
else {
//Remove the phi and replace it with an OR
BuildMI(**MB, I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
else if(tmp->getType() == Type::DoubleTy)
BuildMI(**MB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
- else
+ else
BuildMI(**MB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue());
worklist.push_back(std::make_pair(*MB,I));
}
-
+
}
}
-
+
}
}
//Delete the phis
for(std::vector<std::pair<MachineBasicBlock*, MachineBasicBlock::iterator> >::iterator I = worklist.begin(), E = worklist.end(); I != E; ++I) {
-
+
DEBUG(std::cerr << "Deleting PHI " << *I->second << "\n");
I->first->erase(I->second);
-
+
}
//make sure its def is not of the same stage as this instruction
//because it will be consumed before its used
Instruction *defInst = (Instruction*) srcI;
-
+
//Should we save this value?
bool save = true;
continue;
MachineInstr *defInstr = defMap[srcI];
-
+
if(lastInstrs.count(defInstr)) {
if(lastInstrs[defInstr] == I->second) {
}
}
-
+
if(save)
valuesToSave[srcI] = std::make_pair(I->first, i);
- }
+ }
}
if(mOp.getType() != MachineOperand::MO_VirtualRegister && mOp.isUse()) {
//Map to keep track of old to new values
std::map<Value*, std::map<int, Value*> > newValues;
-
+
//Map to keep track of old to new values in kernel
std::map<Value*, std::map<int, Value*> > kernelPHIs;
//Write prologue
if(schedule.getMaxStage() != 0)
writePrologues(prologues, BB, llvm_prologues, valuesToSave, newValues, newValLocation);
-
+
//Print out epilogues and prologue
- DEBUG(for(std::vector<MachineBasicBlock*>::iterator I = prologues.begin(), E = prologues.end();
+ DEBUG(for(std::vector<MachineBasicBlock*>::iterator I = prologues.begin(), E = prologues.end();
I != E; ++I) {
std::cerr << "PROLOGUE\n";
(*I)->print(std::cerr);
MachineBasicBlock *machineKernelBB = new MachineBasicBlock(llvmKernelBB);
(((MachineBasicBlock*)BB)->getParent())->getBasicBlockList().push_back(machineKernelBB);
writeKernel(llvmKernelBB, machineKernelBB, valuesToSave, newValues, newValLocation, kernelPHIs);
-
-
+
+
std::vector<MachineBasicBlock*> epilogues;
std::vector<BasicBlock*> llvm_epilogues;
//Remove phis
removePHIs(BB, prologues, epilogues, machineKernelBB, newValLocation);
-
+
//Print out epilogues and prologue
- DEBUG(for(std::vector<MachineBasicBlock*>::iterator I = prologues.begin(), E = prologues.end();
+ DEBUG(for(std::vector<MachineBasicBlock*>::iterator I = prologues.begin(), E = prologues.end();
I != E; ++I) {
std::cerr << "PROLOGUE\n";
(*I)->print(std::cerr);
});
-
+
DEBUG(std::cerr << "KERNEL\n");
DEBUG(machineKernelBB->print(std::cerr));
- DEBUG(for(std::vector<MachineBasicBlock*>::iterator I = epilogues.begin(), E = epilogues.end();
+ DEBUG(for(std::vector<MachineBasicBlock*>::iterator I = epilogues.begin(), E = epilogues.end();
I != E; ++I) {
std::cerr << "EPILOGUE\n";
(*I)->print(std::cerr);
if(schedule.getMaxStage() != 0) {
//Fix prologue branches
for(unsigned I = 0; I < prologues.size(); ++I) {
-
+
//Find terminator since getFirstTerminator does not work!
for(MachineBasicBlock::reverse_iterator mInst = prologues[I]->rbegin(), mInstEnd = prologues[I]->rend(); mInst != mInstEnd; ++mInst) {
MachineOpCode OC = mInst->getOpcode();
MachineOperand &mOp = mInst->getOperand(opNum);
if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
//Check if we are branching to the kernel, if not branch to epilogue
- if(mOp.getVRegValue() == BB->getBasicBlock()) {
+ if(mOp.getVRegValue() == BB->getBasicBlock()) {
if(I == prologues.size()-1)
mOp.setValueReg(llvmKernelBB);
else
//Update llvm basic block with our new branch instr
DEBUG(std::cerr << BB->getBasicBlock()->getTerminator() << "\n");
const BranchInst *branchVal = dyn_cast<BranchInst>(BB->getBasicBlock()->getTerminator());
-
+
if(I == prologues.size()-1) {
TerminatorInst *newBranch = new BranchInst(llvmKernelBB,
- llvm_epilogues[(llvm_epilogues.size()-1-I)],
- branchVal->getCondition(),
+ llvm_epilogues[(llvm_epilogues.size()-1-I)],
+ branchVal->getCondition(),
llvm_prologues[I]);
}
else
TerminatorInst *newBranch = new BranchInst(llvm_prologues[I+1],
- llvm_epilogues[(llvm_epilogues.size()-1-I)],
- branchVal->getCondition(),
+ llvm_epilogues[(llvm_epilogues.size()-1-I)],
+ branchVal->getCondition(),
llvm_prologues[I]);
}
else
if(llvm_epilogues.size() > 0) {
assert(origBranchExit == 0 && "There should only be one branch out of the loop");
-
+
origBranchExit = mOp.getVRegValue();
mOp.setValueReg(llvm_epilogues[0]);
}
}
}
}
-
+
//Update kernelLLVM branches
const BranchInst *branchVal = dyn_cast<BranchInst>(BB->getBasicBlock()->getTerminator());
-
+
assert(origBranchExit != 0 && "We must have the original bb the kernel exits to!");
-
+
if(epilogues.size() > 0) {
TerminatorInst *newBranch = new BranchInst(llvmKernelBB,
- llvm_epilogues[0],
- branchVal->getCondition(),
+ llvm_epilogues[0],
+ branchVal->getCondition(),
llvmKernelBB);
}
else {
assert(origBBExit !=0 && "Original exit basic block must be set");
TerminatorInst *newBranch = new BranchInst(llvmKernelBB,
origBBExit,
- branchVal->getCondition(),
+ branchVal->getCondition(),
llvmKernelBB);
}
if(schedule.getMaxStage() != 0) {
//Lastly add unconditional branches for the epilogues
for(unsigned I = 0; I < epilogues.size(); ++I) {
-
+
//Now since we don't have fall throughs, add a unconditional branch to the next prologue
if(I != epilogues.size()-1) {
BuildMI(epilogues[I], V9::BA, 1).addPCDisp(llvm_epilogues[I+1]);
//Add unconditional branch to end of epilogue
- TerminatorInst *newBranch = new BranchInst(llvm_epilogues[I+1],
+ TerminatorInst *newBranch = new BranchInst(llvm_epilogues[I+1],
llvm_epilogues[I]);
}
else {
BuildMI(epilogues[I], V9::BA, 1).addPCDisp(origBranchExit);
-
-
+
+
//Update last epilogue exit branch
BranchInst *branchVal = (BranchInst*) dyn_cast<BranchInst>(BB->getBasicBlock()->getTerminator());
//Find where we are supposed to branch to
if(branchVal->getSuccessor(j) != BB->getBasicBlock())
nextBlock = branchVal->getSuccessor(j);
}
-
+
assert((nextBlock != 0) && "Next block should not be null!");
TerminatorInst *newBranch = new BranchInst(nextBlock, llvm_epilogues[I]);
}
//Add one more nop!
BuildMI(epilogues[I], V9::NOP, 0);
-
+
}
}
//FIX UP Machine BB entry!!
//We are looking at the predecesor of our loop basic block and we want to change its ba instruction
-
+
//Find all llvm basic blocks that branch to the loop entry and change to our first prologue.
const BasicBlock *llvmBB = BB->getBasicBlock();
std::vector<const BasicBlock*>Preds (pred_begin(llvmBB), pred_end(llvmBB));
//for(pred_const_iterator P = pred_begin(llvmBB), PE = pred_end(llvmBB); P != PE; ++PE) {
- for(std::vector<const BasicBlock*>::iterator P = Preds.begin(), PE = Preds.end(); P != PE; ++P) {
+ for(std::vector<const BasicBlock*>::iterator P = Preds.begin(), PE = Preds.end(); P != PE; ++P) {
if(*P == llvmBB)
continue;
else {
}
}
}
- }
+ }
}
else {
term->setSuccessor(i, llvmKernelBB);
break;
}
}
-
+
//BB->getParent()->getBasicBlockList().erase(BB);
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-//
-//
+//
+//
//===----------------------------------------------------------------------===//
#ifndef LLVM_MODULOSCHEDULING_H
#include <set>
namespace llvm {
-
+
//Struct to contain ModuloScheduling Specific Information for each node
struct MSNodeAttributes {
int MOB;
int depth;
int height;
- MSNodeAttributes(int asap=-1, int alap=-1, int mob=-1,
- int d=-1, int h=-1) : ASAP(asap), ALAP(alap),
- MOB(mob), depth(d),
+ MSNodeAttributes(int asap=-1, int alap=-1, int mob=-1,
+ int d=-1, int h=-1) : ASAP(asap), ALAP(alap),
+ MOB(mob), depth(d),
height(h) {}
};
//Map that holds node to node attribute information
std::map<MSchedGraphNode*, MSNodeAttributes> nodeToAttributesMap;
-
+
//Map to hold all reccurrences
std::set<std::pair<int, std::vector<MSchedGraphNode*> > > recurrenceList;
-
+
//Set of edges to ignore, stored as src node and index into vector of successors
std::set<std::pair<MSchedGraphNode*, unsigned> > edgesToIgnore;
-
+
//Vector containing the partial order
std::vector<std::set<MSchedGraphNode*> > partialOrder;
-
+
//Vector containing the final node order
std::vector<MSchedGraphNode*> FinalNodeOrder;
-
+
//Schedule table, key is the cycle number and the vector is resource, node pairs
MSSchedule schedule;
//Internal functions
bool CreateDefMap(MachineBasicBlock *BI);
bool MachineBBisValid(const MachineBasicBlock *BI);
- bool assocIndVar(Instruction *I, std::set<Instruction*> &indVar,
+ bool assocIndVar(Instruction *I, std::set<Instruction*> &indVar,
std::vector<Instruction*> &stack, BasicBlock *BB);
int calculateResMII(const MachineBasicBlock *BI);
int calculateRecMII(MSchedGraph *graph, int MII);
int findMaxASAP();
void orderNodes();
- void findAllReccurrences(MSchedGraphNode *node,
+ void findAllReccurrences(MSchedGraphNode *node,
std::vector<MSchedGraphNode*> &visitedNodes, int II);
void addReccurrence(std::vector<MSchedGraphNode*> &recurrence, int II, MSchedGraphNode*, MSchedGraphNode*);
void findAllCircuits(MSchedGraph *MSG, int II);
- bool circuit(MSchedGraphNode *v, std::vector<MSchedGraphNode*> &stack,
- std::set<MSchedGraphNode*> &blocked,
+ bool circuit(MSchedGraphNode *v, std::vector<MSchedGraphNode*> &stack,
+ std::set<MSchedGraphNode*> &blocked,
std::vector<MSchedGraphNode*> &SCC, MSchedGraphNode *s,
std::map<MSchedGraphNode*, std::set<MSchedGraphNode*> > &B, int II,
std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes);
-
+
void unblock(MSchedGraphNode *u, std::set<MSchedGraphNode*> &blocked,
std::map<MSchedGraphNode*, std::set<MSchedGraphNode*> > &B);
- void searchPath(MSchedGraphNode *node,
+ void searchPath(MSchedGraphNode *node,
std::vector<MSchedGraphNode*> &path,
std::set<MSchedGraphNode*> &nodesToAdd);
- void pathToRecc(MSchedGraphNode *node,
+ void pathToRecc(MSchedGraphNode *node,
std::vector<MSchedGraphNode*> &path,
std::set<MSchedGraphNode*> &poSet, std::set<MSchedGraphNode*> &lastNodes);
-
+
void computePartialOrder();
bool computeSchedule(const MachineBasicBlock *BB);
- bool scheduleNode(MSchedGraphNode *node,
+ bool scheduleNode(MSchedGraphNode *node,
int start, int end);
void predIntersect(std::set<MSchedGraphNode*> &CurrentSet, std::set<MSchedGraphNode*> &IntersectResult);
void succIntersect(std::set<MSchedGraphNode*> &CurrentSet, std::set<MSchedGraphNode*> &IntersectResult);
-
+
void reconstructLoop(MachineBasicBlock*);
-
+
//void saveValue(const MachineInstr*, const std::set<Value*>&, std::vector<Value*>*);
- void fixBranches(std::vector<MachineBasicBlock *> &prologues, std::vector<BasicBlock*> &llvm_prologues, MachineBasicBlock *machineBB, BasicBlock *llvmBB, std::vector<MachineBasicBlock *> &epilogues, std::vector<BasicBlock*> &llvm_epilogues, MachineBasicBlock*);
+ void fixBranches(std::vector<MachineBasicBlock *> &prologues, std::vector<BasicBlock*> &llvm_prologues, MachineBasicBlock *machineBB, BasicBlock *llvmBB, std::vector<MachineBasicBlock *> &epilogues, std::vector<BasicBlock*> &llvm_epilogues, MachineBasicBlock*);
void writePrologues(std::vector<MachineBasicBlock *> &prologues, MachineBasicBlock *origBB, std::vector<BasicBlock*> &llvm_prologues, std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave, std::map<Value*, std::map<int, Value*> > &newValues, std::map<Value*, MachineBasicBlock*> &newValLocation);
void writeEpilogues(std::vector<MachineBasicBlock *> &epilogues, const MachineBasicBlock *origBB, std::vector<BasicBlock*> &llvm_epilogues, std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave,std::map<Value*, std::map<int, Value*> > &newValues, std::map<Value*, MachineBasicBlock*> &newValLocation, std::map<Value*, std::map<int, Value*> > &kernelPHIs);
-
-
+
+
void writeKernel(BasicBlock *llvmBB, MachineBasicBlock *machineBB, std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave, std::map<Value*, std::map<int, Value*> > &newValues, std::map<Value*, MachineBasicBlock*> &newValLocation, std::map<Value*, std::map<int, Value*> > &kernelPHIs);
void removePHIs(const MachineBasicBlock *origBB, std::vector<MachineBasicBlock *> &prologues, std::vector<MachineBasicBlock *> &epilogues, MachineBasicBlock *kernelBB, std::map<Value*, MachineBasicBlock*> &newValLocation);
-
+
void connectedComponentSet(MSchedGraphNode *node, std::set<MSchedGraphNode*> &ccSet, std::set<MSchedGraphNode*> &lastNodes);
public:
ModuloSchedulingPass(TargetMachine &targ) : target(targ) {}
virtual bool runOnFunction(Function &F);
virtual const char* getPassName() const { return "ModuloScheduling"; }
-
+
// getAnalysisUsage
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<DependenceAnalyzer>();
//===-- AllocInfo.h - Store info about regalloc decisions -------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This header file contains the data structure used to save the state
AllocInfo (int Inst_, int Op_, AllocStateTy State_, int Place_) :
Instruction(Inst_), Operand(Op_), AllocState(State_), Placement(Place_) { }
- /// AllocInfo constructor -- Default constructor creates an invalid AllocInfo
+ /// AllocInfo constructor -- Default constructor creates an invalid AllocInfo
/// (presumably to be replaced with something meaningful later).
///
AllocInfo () :
///
bool operator== (const AllocInfo &X) const {
return (X.AllocState == AllocState) && (X.Placement == Placement);
- }
- bool operator!= (const AllocInfo &X) const { return !(*this == X); }
+ }
+ bool operator!= (const AllocInfo &X) const { return !(*this == X); }
/// Returns a human-readable string representation of the AllocState member.
///
//===-- IGNode.cpp --------------------------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file implements an Interference graph node for coloring-based register
// allocation.
-//
+//
//===----------------------------------------------------------------------===//
#include "IGNode.h"
namespace llvm {
//-----------------------------------------------------------------------------
-// Sets this IGNode on stack and reduce the degree of neighbors
+// Sets this IGNode on stack and reduce the degree of neighbors
//-----------------------------------------------------------------------------
void IGNode::pushOnStack() {
- OnStack = true;
+ OnStack = true;
int neighs = AdjList.size();
if (neighs < 0) {
for (int i=0; i < neighs; i++)
AdjList[i]->decCurDegree();
}
-
+
//-----------------------------------------------------------------------------
// Deletes an adjacency node. IGNodes are deleted when coalescing merges
// two IGNodes together.
//===-- IGNode.h - Represent a node in an interference graph ----*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
-// This file represents a node in an interference graph.
+// This file represents a node in an interference graph.
//
// For efficiency, the AdjList is updated only once - ie. we can add but not
-// remove nodes from AdjList.
+// remove nodes from AdjList.
//
// The removal of nodes from IG is simulated by decrementing the CurDegree.
// If this node is put on stack (that is removed from IG), the CurDegree of all
//----------------------------------------------------------------------------
class IGNode {
- const unsigned Index; // index within IGNodeList
+ const unsigned Index; // index within IGNodeList
bool OnStack; // this has been pushed on to stack for coloring
std::vector<IGNode *> AdjList;// adjacency list for this live range
- int CurDegree;
+ int CurDegree;
//
// set by InterferenceGraph::setCurDegreeOfIGNodes() after calculating
// all adjacency lists.
- // Decremented when a neighbor is pushed on to the stack.
+ // Decremented when a neighbor is pushed on to the stack.
// After that, never incremented/set again nor used.
LiveRange *const ParentLR;
// adjLists must be updated only once. However, the CurDegree can be changed
//
- inline void addAdjIGNode(IGNode *AdjNode) { AdjList.push_back(AdjNode); }
+ inline void addAdjIGNode(IGNode *AdjNode) { AdjList.push_back(AdjNode); }
- inline IGNode *getAdjIGNode(unsigned ind) const
+ inline IGNode *getAdjIGNode(unsigned ind) const
{ assert ( ind < AdjList.size()); return AdjList[ind]; }
// delete a node in AdjList - node must be in the list
// should not be called often
//
- void delAdjIGNode(const IGNode *Node);
+ void delAdjIGNode(const IGNode *Node);
inline unsigned getNumOfNeighbors() const { return AdjList.size(); }
// remove form IG and pushes on to stack (reduce the degree of neighbors)
//
- void pushOnStack();
+ void pushOnStack();
// CurDegree is the effective number of neighbors when neighbors are
// pushed on to the stack during the coloring phase. Must be called
//===-- InterferenceGraph.cpp ---------------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// Interference graph for coloring-based register allocation for LLVM.
-//
+//
//===----------------------------------------------------------------------===//
#include "IGNode.h"
//-----------------------------------------------------------------------------
// Constructor: Records the RegClass and initalizes IGNodeList.
-// The matrix is NOT yet created by the constructor. Call createGraph()
+// The matrix is NOT yet created by the constructor. Call createGraph()
// to create it after adding all IGNodes to the IGNodeList.
//-----------------------------------------------------------------------------
InterferenceGraph::InterferenceGraph(RegClass *const RC) : RegCl(RC) {
- IG = NULL;
- Size = 0;
+ IG = NULL;
+ Size = 0;
if( DEBUG_RA >= RA_DEBUG_Interference)
std::cerr << "Interference graph created!\n";
}
// Creates (dynamically allocates) the bit matrix necessary to hold the
// interference graph.
//-----------------------------------------------------------------------------
-void InterferenceGraph::createGraph()
-{
+void InterferenceGraph::createGraph()
+{
Size = IGNodeList.size();
- IG = new char*[Size];
+ IG = new char*[Size];
for( unsigned int r=0; r < Size; ++r)
IG[r] = new char[Size];
// init IG matrix
- for(unsigned int i=0; i < Size; i++)
+ for(unsigned int i=0; i < Size; i++)
for(unsigned int j=0; j < Size; j++)
IG[i][j] = 0;
}
//-----------------------------------------------------------------------------
void InterferenceGraph::setInterference(const LiveRange *const LR1,
const LiveRange *const LR2 ) {
- assert(LR1 != LR2);
+ assert(LR1 != LR2);
IGNode *IGNode1 = LR1->getUserIGNode();
IGNode *IGNode2 = LR2->getUserIGNode();
- assertIGNode(this, IGNode1);
+ assertIGNode(this, IGNode1);
assertIGNode(this, IGNode2);
-
+
unsigned row = IGNode1->getIndex();
unsigned col = IGNode2->getIndex();
char *val;
- if( DEBUG_RA >= RA_DEBUG_Interference)
- std::cerr << "setting intf for: [" << row << "][" << col << "]\n";
+ if( DEBUG_RA >= RA_DEBUG_Interference)
+ std::cerr << "setting intf for: [" << row << "][" << col << "]\n";
- ( row > col) ? val = &IG[row][col]: val = &IG[col][row];
+ ( row > col) ? val = &IG[row][col]: val = &IG[col][row];
if( ! (*val) ) { // if this interf is not previously set
- *val = 1; // add edges between nodes
- IGNode1->addAdjIGNode( IGNode2 );
+ *val = 1; // add edges between nodes
+ IGNode1->addAdjIGNode( IGNode2 );
IGNode2->addAdjIGNode( IGNode1 );
}
unsigned InterferenceGraph::getInterference(const LiveRange *const LR1,
const LiveRange *const LR2) const {
assert(LR1 != LR2);
- assertIGNode(this, LR1->getUserIGNode());
+ assertIGNode(this, LR1->getUserIGNode());
assertIGNode(this, LR2->getUserIGNode());
const unsigned int row = LR1->getUserIGNode()->getIndex();
const unsigned int col = LR2->getUserIGNode()->getIndex();
- char ret;
+ char ret;
if (row > col)
ret = IG[row][col];
- else
- ret = IG[col][row];
+ else
+ ret = IG[col][row];
return ret;
}
//----------------------------------------------------------------------------
// Merge 2 IGNodes. The neighbors of the SrcNode will be added to the DestNode.
// Then the IGNode2L will be deleted. Necessary for coalescing.
-// IMPORTANT: The live ranges are NOT merged by this method. Use
+// IMPORTANT: The live ranges are NOT merged by this method. Use
// LiveRangeInfo::unionAndUpdateLRs for that purpose.
//----------------------------------------------------------------------------
-void InterferenceGraph::mergeIGNodesOfLRs(const LiveRange *LR1,
+void InterferenceGraph::mergeIGNodesOfLRs(const LiveRange *LR1,
LiveRange *LR2) {
assert( LR1 != LR2); // cannot merge the same live range
// for all neighs of SrcNode
- for(unsigned i=0; i < SrcDegree; i++) {
- IGNode *NeighNode = SrcNode->getAdjIGNode(i);
+ for(unsigned i=0; i < SrcDegree; i++) {
+ IGNode *NeighNode = SrcNode->getAdjIGNode(i);
LiveRange *const LROfNeigh = NeighNode->getParentLR();
// delete edge between src and neigh - even neigh == dest
- NeighNode->delAdjIGNode(SrcNode);
+ NeighNode->delAdjIGNode(SrcNode);
// set the matrix posn to 0 betn src and neigh - even neigh == dest
const unsigned NInd = NeighNode->getIndex();
- ( SrcInd > NInd) ? (IG[SrcInd][NInd]=0) : (IG[NInd][SrcInd]=0) ;
+ ( SrcInd > NInd) ? (IG[SrcInd][NInd]=0) : (IG[NInd][SrcInd]=0) ;
- if( LR1 != LROfNeigh) { // if the neigh != dest
-
+ if( LR1 != LROfNeigh) { // if the neigh != dest
+
// add edge betwn Dest and Neigh - if there is no current edge
- setInterference(LR1, LROfNeigh );
+ setInterference(LR1, LROfNeigh );
}
-
+
}
IGNodeList[ SrcInd ] = NULL;
// SrcNode is no longer necessary - LR2 must be deleted by the caller
- delete( SrcNode );
+ delete( SrcNode );
}
//--------------------- debugging (Printing) methods -----------------------
//----------------------------------------------------------------------------
-// Print the IGnodes
+// Print the IGnodes
//----------------------------------------------------------------------------
void InterferenceGraph::printIG() const {
- for(unsigned i=0; i < Size; i++) {
+ for(unsigned i=0; i < Size; i++) {
const IGNode *const Node = IGNodeList[i];
if(Node) {
std::cerr << " [" << i << "] ";
//===-- InterferenceGraph.h - Interference graph for register coloring -*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
/* Title: InterferenceGraph.h -*- C++ -*-
Date: July 20, 01
Purpose: Interference Graph used for register coloring.
- Notes:
- Adj Info is stored in the lower trangular matrix (i.e., row > col )
+ Notes:
+ Adj Info is stored in the lower trangular matrix (i.e., row > col )
This class must be used in the following way:
* Construct class
* call addLRToIG as many times to add ALL LRs to this IG
* call createGraph to create the actual matrix
- * Then setInterference, getInterference, mergeIGNodesOfLRs can be
+ * Then setInterference, getInterference, mergeIGNodesOfLRs can be
called as desired to modify the graph.
- * Once the modifications to the graph are over, call
+ * Once the modifications to the graph are over, call
setCurDegreeOfIGNodes() before pushing IGNodes on to stack for coloring.
*/
unsigned int Size; // size of a side of the IG
RegClass *const RegCl; // RegCl contains this IG
std::vector<IGNode *> IGNodeList; // a list of all IGNodes in a reg class
-
+
public:
- // the matrix is not yet created by the constructor. Call createGraph()
+ // the matrix is not yet created by the constructor. Call createGraph()
// to create it after adding all IGNodes to the IGNodeList
InterferenceGraph(RegClass *RC);
~InterferenceGraph();
void mergeIGNodesOfLRs(const LiveRange *LR1, LiveRange *LR2);
- std::vector<IGNode *> &getIGNodeList() { return IGNodeList; }
- const std::vector<IGNode *> &getIGNodeList() const { return IGNodeList; }
+ std::vector<IGNode *> &getIGNodeList() { return IGNodeList; }
+ const std::vector<IGNode *> &getIGNodeList() const { return IGNodeList; }
void setCurDegreeOfIGNodes();
//===-- LiveRange.h - Store info about a live range -------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Implements a live range using a SetVector of Value *s. We keep only
ValueContainerType MyValues; // Values in this LiveRange
RegClass *MyRegClass; // register class (e.g., int, FP) for this LR
- /// doesSpanAcrossCalls - Does this live range span across calls?
+ /// doesSpanAcrossCalls - Does this live range span across calls?
/// This information is used by graph coloring algo to avoid allocating
/// volatile colors to live ranges that span across calls (since they have to
/// be saved/restored)
/// this live range is not available before graph coloring (e.g., it
/// can be allocated to another live range which interferes with
/// this)
- ///
+ ///
bool CanUseSuggestedCol;
/// SpilledStackOffsetFromFP - If this LR is spilled, its stack
void insert(iterator b, iterator e) { MyValues.insert (b, e); }
LiveRange() {
- Color = SuggestedColor = -1; // not yet colored
+ Color = SuggestedColor = -1; // not yet colored
mustSpill = false;
MyRegClass = 0;
UserIGNode = 0;
unsigned getRegClassID() const;
bool hasColor() const { return Color != -1; }
-
+
unsigned getColor() const { assert(Color != -1); return (unsigned)Color; }
void setColor(unsigned Col) { Color = (int)Col; }
- inline void setCallInterference() {
+ inline void setCallInterference() {
doesSpanAcrossCalls = 1;
}
- inline void clearCallInterference() {
+ inline void clearCallInterference() {
doesSpanAcrossCalls = 0;
}
- inline bool isCallInterference() const {
- return doesSpanAcrossCalls == 1;
- }
+ inline bool isCallInterference() const {
+ return doesSpanAcrossCalls == 1;
+ }
inline void markForSpill() { mustSpill = true; }
inline const Type *getType() const {
return (*begin())->getType(); // set's don't have a front
}
-
+
inline void setSuggestedColor(int Col) {
if (SuggestedColor == -1)
SuggestedColor = Col;
//===-- LiveRangeInfo.cpp -------------------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// Live range construction for coloring-based register allocation for LLVM.
-//
+//
//===----------------------------------------------------------------------===//
#include "IGNode.h"
LiveRangeInfo::~LiveRangeInfo() {
- for (LiveRangeMapType::iterator MI = LiveRangeMap.begin();
- MI != LiveRangeMap.end(); ++MI) {
+ for (LiveRangeMapType::iterator MI = LiveRangeMap.begin();
+ MI != LiveRangeMap.end(); ++MI) {
if (MI->first && MI->second) {
LiveRange *LR = MI->second;
for (LiveRange::iterator LI = LR->begin(); LI != LR->end(); ++LI)
LiveRangeMap[*LI] = 0;
-
+
delete LR;
}
}
for(LiveRange::iterator L2It = L2->begin(); L2It != L2->end(); ++L2It) {
L1->insert(*L2It); // add the var in L2 to L1
- LiveRangeMap[*L2It] = L1; // now the elements in L2 should map
- //to L1
+ LiveRangeMap[*L2It] = L1; // now the elements in L2 should map
+ //to L1
}
-
+
// set call interference for L1 from L2
if (L2->isCallInterference())
L1->setCallInterference();
-
+
// add the spill costs
L1->addSpillCost(L2->getSpillCost());
// must have the same color.
if (L2->hasSuggestedColor())
L1->setSuggestedColor(L2->getSuggestedColor());
-
+
delete L2; // delete L2 as it is no longer needed
}
LiveRange*
LiveRangeInfo::createNewLiveRange(const Value* Def, bool isCC /* = false*/)
-{
+{
LiveRange* DefRange = new LiveRange(); // Create a new live range,
DefRange->insert(Def); // add Def to it,
LiveRangeMap[Def] = DefRange; // and update the map.
LiveRange*
LiveRangeInfo::createOrAddToLiveRange(const Value* Def, bool isCC /* = false*/)
-{
+{
LiveRange *DefRange = LiveRangeMap[Def];
// check if the LR is already there (because of multiple defs)
- if (!DefRange) {
+ if (!DefRange) {
DefRange = createNewLiveRange(Def, isCC);
} else { // live range already exists
DefRange->insert(Def); // add the operand to the range
//---------------------------------------------------------------------------
-// Method for constructing all live ranges in a function. It creates live
+// Method for constructing all live ranges in a function. It creates live
// ranges for all values defined in the instruction stream. Also, it
// creates live ranges for all incoming arguments of the function.
//---------------------------------------------------------------------------
-void LiveRangeInfo::constructLiveRanges() {
+void LiveRangeInfo::constructLiveRanges() {
- if (DEBUG_RA >= RA_DEBUG_LiveRanges)
+ if (DEBUG_RA >= RA_DEBUG_LiveRanges)
std::cerr << "Constructing Live Ranges ...\n";
// first find the live ranges for all incoming args of the function since
for (Function::const_arg_iterator AI = Meth->arg_begin(); AI != Meth->arg_end(); ++AI)
createNewLiveRange(AI, /*isCC*/ false);
- // Now suggest hardware registers for these function args
+ // Now suggest hardware registers for these function args
MRI.suggestRegs4MethodArgs(Meth, *this);
- // Now create LRs for machine instructions. A new LR will be created
+ // Now create LRs for machine instructions. A new LR will be created
// only for defs in the machine instr since, we assume that all Values are
// defined before they are used. However, there can be multiple defs for
// the same Value in machine instructions.
- //
+ //
// Also, find CALL and RETURN instructions, which need extra work.
//
MachineFunction &MF = MachineFunction::get(Meth);
// iterate over all the machine instructions in BB
for(MachineBasicBlock::iterator MInstIterator = MBB.begin();
- MInstIterator != MBB.end(); ++MInstIterator) {
- MachineInstr *MInst = MInstIterator;
+ MInstIterator != MBB.end(); ++MInstIterator) {
+ MachineInstr *MInst = MInstIterator;
// If the machine instruction is a call/return instruction, add it to
// CallRetInstrList for processing its args, ret value, and ret addr.
- //
+ //
if(TM.getInstrInfo()->isReturn(MInst->getOpcode()) ||
TM.getInstrInfo()->isCall(MInst->getOpcode()))
- CallRetInstrList.push_back(MInst);
-
+ CallRetInstrList.push_back(MInst);
+
// iterate over explicit MI operands and create a new LR
// for each operand that is defined by the instruction
for (MachineInstr::val_op_iterator OpI = MInst->begin(),
OpE = MInst->end(); OpI != OpE; ++OpI)
- if (OpI.isDef()) {
+ if (OpI.isDef()) {
const Value *Def = *OpI;
bool isCC = (OpI.getMachineOperand().getType()
== MachineOperand::MO_CCRegister);
// iterate over implicit MI operands and create a new LR
// for each operand that is defined by the instruction
- for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i)
+ for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i)
if (MInst->getImplicitOp(i).isDef()) {
const Value *Def = MInst->getImplicitRef(i);
LiveRange* LR = createOrAddToLiveRange(Def, /*isCC*/ false);
// Now we have to suggest clors for call and return arg live ranges.
// Also, if there are implicit defs (e.g., retun value of a call inst)
// they must be added to the live range list
- //
+ //
suggestRegs4CallRets();
- if( DEBUG_RA >= RA_DEBUG_LiveRanges)
+ if( DEBUG_RA >= RA_DEBUG_LiveRanges)
std::cerr << "Initial Live Ranges constructed!\n";
}
// (e.g., for outgoing call args), suggesting of colors for such live
// ranges is done using target specific function. Those functions are called
// from this function. The target specific methods must:
-// 1) suggest colors for call and return args.
+// 1) suggest colors for call and return args.
// 2) create new LRs for implicit defs in machine instructions
//---------------------------------------------------------------------------
void LiveRangeInfo::suggestRegs4CallRets() {
MRI.suggestReg4RetValue(MInst, *this);
else if (TM.getInstrInfo()->isCall(OpCode))
MRI.suggestRegs4CallArgs(MInst, *this);
- else
+ else
assert( 0 && "Non call/ret instr in CallRetInstrList" );
}
}
if the def and op do not interfere //i.e., not simultaneously live
if (degree(LR of def) + degree(LR of op)) <= # avail regs
if both LRs do not have suggested colors
- merge2IGNodes(def, op) // i.e., merge 2 LRs
+ merge2IGNodes(def, op) // i.e., merge 2 LRs
*/
//---------------------------------------------------------------------------
// Checks if live range LR interferes with any node assigned or suggested to
// be assigned the specified color
-//
+//
inline bool InterferesWithColor(const LiveRange& LR, unsigned color) {
IGNode* lrNode = LR.getUserIGNode();
for (unsigned n=0, NN = lrNode->getNumOfNeighbors(); n < NN; n++) {
// (but if the colors are the same, it is definitely safe to coalesce)
// (3) LR1 has color and LR2 interferes with any LR that has the same color
// (4) LR2 has color and LR1 interferes with any LR that has the same color
-//
+//
inline bool InterfsPreventCoalescing(const LiveRange& LROfDef,
const LiveRange& LROfUse) {
// (4) if they have different suggested colors, cannot coalesce
}
-void LiveRangeInfo::coalesceLRs()
+void LiveRangeInfo::coalesceLRs()
{
- if(DEBUG_RA >= RA_DEBUG_LiveRanges)
+ if(DEBUG_RA >= RA_DEBUG_LiveRanges)
std::cerr << "\nCoalescing LRs ...\n";
MachineFunction &MF = MachineFunction::get(Meth);
if (!RCOfDef->getInterference(LROfDef, LROfUse) ) {
unsigned CombinedDegree =
- LROfDef->getUserIGNode()->getNumOfNeighbors() +
+ LROfDef->getUserIGNode()->getNumOfNeighbors() +
LROfUse->getUserIGNode()->getNumOfNeighbors();
if (CombinedDegree > RCOfDef->getNumOfAvailRegs()) {
} // for all machine instructions
} // for all BBs
- if (DEBUG_RA >= RA_DEBUG_LiveRanges)
+ if (DEBUG_RA >= RA_DEBUG_LiveRanges)
std::cerr << "\nCoalescing Done!\n";
}
std::cerr << "\nPrinting Live Ranges from Hash Map:\n";
for( ; HMI != LiveRangeMap.end(); ++HMI) {
if (HMI->first && HMI->second) {
- std::cerr << " Value* " << RAV(HMI->first) << "\t: ";
+ std::cerr << " Value* " << RAV(HMI->first) << "\t: ";
if (IGNode* igNode = HMI->second->getUserIGNode())
std::cerr << "LR# " << igNode->getIndex();
else
//===-- LiveRangeInfo.h - Track all LiveRanges for a Function ----*- C++ -*-==//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
-// This file contains the class LiveRangeInfo which constructs and keeps
+// This file contains the class LiveRangeInfo which constructs and keeps
// the LiveRangeMap which contains all the live ranges used in a method.
//
-// Assumptions:
+// Assumptions:
//
-// All variables (llvm Values) are defined before they are used. However, a
+// All variables (llvm Values) are defined before they are used. However, a
// constant may not be defined in the machine instruction stream if it can be
// used as an immediate value within a machine instruction. However, register
// allocation does not have to worry about immediate constants since they
//----------------------------------------------------------------------------
// Class LiveRangeInfo
//
-// Constructs and keeps the LiveRangeMap which contains all the live
+// Constructs and keeps the LiveRangeMap which contains all the live
// ranges used in a method. Also contain methods to coalesce live ranges.
//----------------------------------------------------------------------------
class LiveRangeInfo {
const Function *const Meth; // Func for which live range info is held
- LiveRangeMapType LiveRangeMap; // A map from Value * to LiveRange * to
+ LiveRangeMapType LiveRangeMap; // A map from Value * to LiveRange * to
// record all live ranges in a method
// created by constructLiveRanges
-
+
const TargetMachine& TM; // target machine description
std::vector<RegClass *> & RegClassList;// vector containing register classess
void suggestRegs4CallRets ();
public:
-
- LiveRangeInfo(const Function *F,
+
+ LiveRangeInfo(const Function *F,
const TargetMachine& tm,
std::vector<RegClass *> & RCList);
// Main entry point for live range construction
//
void constructLiveRanges();
-
+
/// return the common live range map for this method
///
- inline const LiveRangeMapType *getLiveRangeMap() const
+ inline const LiveRangeMapType *getLiveRangeMap() const
{ return &LiveRangeMap; }
/// Method used to get the live range containing a Value.
/// Method for coalescing live ranges. Called only after interference info
/// is calculated.
///
- void coalesceLRs();
+ void coalesceLRs();
/// debugging method to print the live ranges
///
} // End llvm namespace
-#endif
+#endif
//===-- PhyRegAlloc.cpp ---------------------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// Traditional graph-coloring global register allocator currently used
// by the SPARC back-end.
//
// NOTE 2: This register allocator can save its state in a global
// variable in the module it's working on. This feature is not
// thread-safe; if you have doubts, leave it turned off.
-//
+//
//===----------------------------------------------------------------------===//
#include "AllocInfo.h"
void PhyRegAlloc::createIGNodeListsAndIGs() {
if (DEBUG_RA >= RA_DEBUG_LiveRanges) std::cerr << "Creating LR lists ...\n";
- LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
- LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
+ LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
+ LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
for (; HMI != HMIEnd ; ++HMI ) {
- if (HMI->first) {
+ if (HMI->first) {
LiveRange *L = HMI->second; // get the LiveRange
- if (!L) {
+ if (!L) {
if (DEBUG_RA && !isa<ConstantIntegral> (HMI->first))
std::cerr << "\n**** ?!?WARNING: NULL LIVE RANGE FOUND FOR: "
<< RAV(HMI->first) << "****\n";
}
// if the Value * is not null, and LR is not yet written to the IGNodeList
- if (!(L->getUserIGNode()) ) {
+ if (!(L->getUserIGNode()) ) {
RegClass *const RC = // RegClass of first value in the LR
RegClassList[ L->getRegClassID() ];
RC->addLRToIG(L); // add this LR to an IG
}
}
}
-
+
// init RegClassList
- for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
+ for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
RegClassList[rc]->createInterferenceGraph();
if (DEBUG_RA >= RA_DEBUG_LiveRanges) std::cerr << "LRLists Created!\n";
ValueSet::const_iterator LIt = LVSet->begin();
// get the live range of instruction
- const LiveRange *const LROfDef = LRI->getLiveRangeForValue( Def );
+ const LiveRange *const LROfDef = LRI->getLiveRangeForValue( Def );
IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
assert( IGNodeOfDef );
- RegClass *const RCOfDef = LROfDef->getRegClass();
+ RegClass *const RCOfDef = LROfDef->getRegClass();
// for each live var in live variable set
for ( ; LIt != LVSet->end(); ++LIt) {
// get the live range corresponding to live var
LiveRange *LROfVar = LRI->getLiveRangeForValue(*LIt);
- // LROfVar can be null if it is a const since a const
+ // LROfVar can be null if it is a const since a const
// doesn't have a dominating def - see Assumptions above
if (LROfVar)
if (LROfDef != LROfVar) // do not set interf for same LR
if (RCOfDef == LROfVar->getRegClass()) // 2 reg classes are the same
- RCOfDef->setInterference( LROfDef, LROfVar);
+ RCOfDef->setInterference( LROfDef, LROfVar);
}
}
-/// For a call instruction, this method sets the CallInterference flag in
+/// For a call instruction, this method sets the CallInterference flag in
/// the LR of each variable live in the Live Variable Set live after the
/// call instruction (except the return value of the call instruction - since
/// the return value does not interfere with that call itself).
///
-void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
+void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
const ValueSet *LVSetAft) {
if (DEBUG_RA >= RA_DEBUG_Interference)
std::cerr << "\n For call inst: " << *MInst;
LIt != LEnd; ++LIt) {
// get the live range corresponding to live var
- LiveRange *const LR = LRI->getLiveRangeForValue(*LIt);
+ LiveRange *const LR = LRI->getLiveRangeForValue(*LIt);
- // LR can be null if it is a const since a const
+ // LR can be null if it is a const since a const
// doesn't have a dominating def - see Assumptions above
- if (LR) {
+ if (LR) {
if (DEBUG_RA >= RA_DEBUG_Interference)
std::cerr << "\n\tLR after Call: " << *LR << "\n";
LR->setCallInterference();
// of the call is live in this set - but it does not interfere with call
// (i.e., we can allocate a volatile register to the return value)
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(MInst);
-
+
if (const Value *RetVal = argDesc->getReturnValue()) {
LiveRange *RetValLR = LRI->getLiveRangeForValue( RetVal );
assert( RetValLR && "No LR for RetValue of call");
if (const Value *AddrVal = argDesc->getIndirectFuncPtr()) {
LiveRange *AddrValLR = LRI->getLiveRangeForValue( AddrVal );
// LR can be null if the function pointer is a constant.
- if (AddrValLR)
+ if (AddrValLR)
AddrValLR->setCallInterference();
}
}
const MachineBasicBlock &MBB = *BBI;
const BasicBlock *BB = MBB.getBasicBlock();
- // find the 10^(loop_depth) of this BB
+ // find the 10^(loop_depth) of this BB
BBLoopDepthCost = (unsigned)pow(10.0, LoopDepthCalc->getLoopDepth(BB));
// get the iterator for machine instructions
// Calculate the spill cost of each live range
LiveRange *LR = LRI->getLiveRangeForValue(*OpI);
if (LR) LR->addSpillCost(BBLoopDepthCost);
- }
+ }
// Also add interference for any implicit definitions in a machine
// instr (currently, only calls have this).
unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
- for (unsigned z=0; z < NumOfImpRefs; z++)
+ for (unsigned z=0; z < NumOfImpRefs; z++)
if (MInst->getImplicitOp(z).isDef())
addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
} // for all machine instructions in BB
} // for all BBs in function
- // add interferences for function arguments. Since there are no explicit
+ // add interferences for function arguments. Since there are no explicit
// defs in the function for args, we have to add them manually
- addInterferencesForArgs();
+ addInterferencesForArgs();
if (DEBUG_RA >= RA_DEBUG_Interference)
std::cerr << "Interference graphs calculated!\n";
// iterate over MI operands to find defs
for (MachineInstr::const_val_op_iterator It1 = MInst->begin(),
ItE = MInst->end(); It1 != ItE; ++It1) {
- const LiveRange *LROfOp1 = LRI->getLiveRangeForValue(*It1);
+ const LiveRange *LROfOp1 = LRI->getLiveRangeForValue(*It1);
assert((LROfOp1 || It1.isDef()) && "No LR for Def in PSEUDO insruction");
MachineInstr::const_val_op_iterator It2 = It1;
for (++It2; It2 != ItE; ++It2) {
- const LiveRange *LROfOp2 = LRI->getLiveRangeForValue(*It2);
+ const LiveRange *LROfOp2 = LRI->getLiveRangeForValue(*It2);
if (LROfOp2) {
- RegClass *RCOfOp1 = LROfOp1->getRegClass();
- RegClass *RCOfOp2 = LROfOp2->getRegClass();
-
- if (RCOfOp1 == RCOfOp2 ){
- RCOfOp1->setInterference( LROfOp1, LROfOp2 );
+ RegClass *RCOfOp1 = LROfOp1->getRegClass();
+ RegClass *RCOfOp2 = LROfOp2->getRegClass();
+
+ if (RCOfOp1 == RCOfOp2 ){
+ RCOfOp1->setInterference( LROfOp1, LROfOp2 );
setInterf = true;
}
} // if Op2 has a LR
std::cerr << *MInst;
assert(0 && "Interf not set for pseudo instr with > 2 operands" );
}
-}
+}
/// Add interferences for incoming arguments to a function.
///
void PhyRegAlloc::addInterferencesForArgs() {
// get the InSet of root BB
- const ValueSet &InSet = LVI->getInSetOfBB(&Fn->front());
+ const ValueSet &InSet = LVI->getInSetOfBB(&Fn->front());
for (Function::const_arg_iterator AI = Fn->arg_begin(); AI != Fn->arg_end(); ++AI) {
- // add interferences between args and LVars at start
+ // add interferences between args and LVars at start
addInterference(AI, &InSet, false);
-
+
if (DEBUG_RA >= RA_DEBUG_Interference)
std::cerr << " - %% adding interference for argument " << RAV(AI) << "\n";
}
const std::string& msg) {
if (!IBef.empty()) {
MachineInstr* OrigMI = MII;
- std::vector<MachineInstr *>::iterator AdIt;
+ std::vector<MachineInstr *>::iterator AdIt;
for (AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt) {
if (DEBUG_RA) {
if (OrigMI) std::cerr << "For MInst:\n " << *OrigMI;
const std::string& msg) {
if (!IAft.empty()) {
MachineInstr* OrigMI = MII;
- std::vector<MachineInstr *>::iterator AdIt;
+ std::vector<MachineInstr *>::iterator AdIt;
for ( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
if (DEBUG_RA) {
if (OrigMI) std::cerr << "For MInst:\n " << *OrigMI;
// will need to know which registers are already used by this instr'n.
for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
MachineOperand& Op = MInst->getOperand(OpNum);
- if (Op.getType() == MachineOperand::MO_VirtualRegister ||
+ if (Op.getType() == MachineOperand::MO_VirtualRegister ||
Op.getType() == MachineOperand::MO_CCRegister) {
const Value *const Val = Op.getVRegValue();
if (const LiveRange* LR = LRI->getLiveRangeForValue(Val)) {
unsigned Opcode = MInst->getOpcode();
// Reset tmp stack positions so they can be reused for each machine instr.
- MF->getInfo<SparcV9FunctionInfo>()->popAllTempValues();
+ MF->getInfo<SparcV9FunctionInfo>()->popAllTempValues();
// Mark the operands for which regs have been allocated.
bool instrNeedsSpills = markAllocatedRegs(MII);
if (instrNeedsSpills)
for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
MachineOperand& Op = MInst->getOperand(OpNum);
- if (Op.getType() == MachineOperand::MO_VirtualRegister ||
+ if (Op.getType() == MachineOperand::MO_VirtualRegister ||
Op.getType() == MachineOperand::MO_CCRegister) {
const Value* Val = Op.getVRegValue();
if (const LiveRange *LR = LRI->getLiveRangeForValue(Val))
assert(AddedInstrAtEntry.InstrnsAfter.empty() &&
"InstrsAfter should be unnecessary since we are just inserting at "
"the function entry point here.");
-
+
for (MachineFunction::iterator BBI = MF->begin(), BBE = MF->end();
BBI != BBE; ++BBI) {
MachineBasicBlock &MBB = *BBI;
// Iterate over all machine instructions in BB and mark operands with
- // their assigned registers or insert spill code, as appropriate.
+ // their assigned registers or insert spill code, as appropriate.
// Also, fix operands of call/return instructions.
for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
if (MII->getOpcode() != V9::PHI)
// move any existing instructions out of the delay slot so that the
// instructions can go into the delay slot. This only supports the
// case that #instrsAfter <= #delay slots.
- //
+ //
// (2) If any instruction in the delay slot needs
// instructions inserted, move it out of the delay slot and before the
// branch because putting code before or after it would be VERY BAD!
- //
+ //
// If the annul bit of the branch is set, neither of these is legal!
// If so, we need to handle spill differently but annulling is not yet used.
for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
if (unsigned delaySlots =
- TM.getInstrInfo()->getNumDelaySlots(MII->getOpcode())) {
+ TM.getInstrInfo()->getNumDelaySlots(MII->getOpcode())) {
MachineBasicBlock::iterator DelaySlotMI = next(MII);
assert(DelaySlotMI != MBB.end() && "no instruction for delay slot");
-
+
// Check the 2 conditions above:
// (1) Does a branch need instructions added after it?
// (2) O/w does delay slot instr. need instrns before or after?
// Finally iterate over all instructions in BB and insert before/after
for (MachineBasicBlock::iterator MII=MBB.begin(); MII != MBB.end(); ++MII) {
- MachineInstr *MInst = MII;
+ MachineInstr *MInst = MII;
// do not process Phis
if (MInst->getOpcode() == V9::PHI)
assert(instrsSeen.count(CallAI.InstrnsBefore[i]) == 0 &&
"Duplicate machine instruction in InstrnsBefore!");
instrsSeen.insert(CallAI.InstrnsBefore[i]);
- }
+ }
for (int i = 0, N = CallAI.InstrnsAfter.size(); i < N; ++i) {
assert(instrsSeen.count(CallAI.InstrnsAfter[i]) == 0 &&
"Duplicate machine instruction in InstrnsBefore/After!");
instrsSeen.insert(CallAI.InstrnsAfter[i]);
- }
+ }
#endif
// Now add the instructions before/after this MI.
// as close as possible to an instruction (see above insertCode4Spill)
if (! CallAI.InstrnsBefore.empty())
PrependInstructions(CallAI.InstrnsBefore, MBB, MII,"");
-
+
if (! CallAI.InstrnsAfter.empty())
AppendInstructions(CallAI.InstrnsAfter, MBB, MII,"");
/// instruction. Then it uses this register temporarily to accommodate the
/// spilled value.
///
-void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
+void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
MachineBasicBlock::iterator& MII,
MachineBasicBlock &MBB,
const unsigned OpNum) {
#endif
MF->getInfo<SparcV9FunctionInfo>()->pushTempValue(MRI.getSpilledRegSize(RegType));
-
+
std::vector<MachineInstr*> MIBef, MIAft;
std::vector<MachineInstr*> AdIMid;
-
+
// Choose a register to hold the spilled value, if one was not preallocated.
// This may insert code before and after MInst to free up the value. If so,
// this code should be first/last in the spill sequence before/after MInst.
int TmpRegU=(LR->hasColor()
? MRI.getUnifiedRegNum(LR->getRegClassID(),LR->getColor())
: getUsableUniRegAtMI(RegType, &LVSetBef, MInst, MIBef,MIAft));
-
+
// Set the operand first so that it this register does not get used
// as a scratch register for later calls to getUsableUniRegAtMI below
MInst->SetRegForOperand(OpNum, TmpRegU);
-
+
// get the added instructions for this instruction
AddedInstrns &AI = AddedInstrMap[MInst];
// We may need a scratch register to copy the spilled value to/from memory.
- // This may itself have to insert code to free up a scratch register.
+ // This may itself have to insert code to free up a scratch register.
// Any such code should go before (after) the spill code for a load (store).
// The scratch reg is not marked as used because it is only used
// for the copy and not used across MInst.
MInst, MIBef, MIAft);
assert(scratchReg != MRI.getInvalidRegNum());
}
-
+
if (isUse) {
// for a USE, we have to load the value of LR from stack to a TmpReg
// and use the TmpReg as one operand of instruction
-
+
// actual loading instruction(s)
MRI.cpMem2RegMI(AdIMid, MRI.getFramePointer(), SpillOff, TmpRegU,
RegType, scratchReg);
-
+
// the actual load should be after the instructions to free up TmpRegU
MIBef.insert(MIBef.end(), AdIMid.begin(), AdIMid.end());
AdIMid.clear();
}
-
+
if (isDef) { // if this is a Def
// for a DEF, we have to store the value produced by this instruction
// on the stack position allocated for this LR
-
+
// actual storing instruction(s)
MRI.cpReg2MemMI(AdIMid, TmpRegU, MRI.getFramePointer(), SpillOff,
RegType, scratchReg);
-
+
MIAft.insert(MIAft.begin(), AdIMid.begin(), AdIMid.end());
} // if !DEF
-
+
// Finally, insert the entire spill code sequences before/after MInst
AI.InstrnsBefore.insert(AI.InstrnsBefore.end(), MIBef.begin(), MIBef.end());
AI.InstrnsAfter.insert(AI.InstrnsAfter.begin(), MIAft.begin(), MIAft.end());
-
+
if (DEBUG_RA) {
std::cerr << "\nFor Inst:\n " << *MInst;
std::cerr << "SPILLED LR# " << LR->getUserIGNode()->getIndex();
void
PhyRegAlloc::insertCallerSavingCode(std::vector<MachineInstr*> &instrnsBefore,
std::vector<MachineInstr*> &instrnsAfter,
- MachineInstr *CallMI,
+ MachineInstr *CallMI,
const BasicBlock *BB) {
assert(TM.getInstrInfo()->isCall(CallMI->getOpcode()));
-
+
// hash set to record which registers were saved/restored
hash_set<unsigned> PushedRegSet;
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
-
+
// if the call is to a instrumentation function, do not insert save and
// restore instructions the instrumentation function takes care of save
// restore for volatile regs.
// get the live range corresponding to live var
LiveRange *const LR = LRI->getLiveRangeForValue(*LIt);
- // LR can be null if it is a const since a const
+ // LR can be null if it is a const since a const
// doesn't have a dominating def - see Assumptions above
- if (LR) {
+ if (LR) {
if (! LR->isMarkedForSpill()) {
assert(LR->hasColor() && "LR is neither spilled nor colored?");
unsigned RCID = LR->getRegClassID();
if (isLLVMFirstTrigger && !MRI.modifiedByCall(RCID, Color))
continue;
- // if the value is in both LV sets (i.e., live before and after
+ // if the value is in both LV sets (i.e., live before and after
// the call machine instruction)
unsigned Reg = MRI.getUnifiedRegNum(RCID, Color);
-
+
// if we haven't already pushed this register...
if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
unsigned RegType = MRI.getRegTypeForLR(LR);
// call instruction
int StackOff =
MF->getInfo<SparcV9FunctionInfo>()->pushTempValue(MRI.getSpilledRegSize(RegType));
-
+
//---- Insert code for pushing the reg on stack ----------
-
+
std::vector<MachineInstr*> AdIBef, AdIAft;
-
+
// We may need a scratch register to copy the saved value
// to/from memory. This may itself have to insert code to
// free up a scratch register. Any such code should go before
CallMI, AdIBef, AdIAft);
assert(scratchReg != MRI.getInvalidRegNum());
}
-
+
if (AdIBef.size() > 0)
instrnsBefore.insert(instrnsBefore.end(),
AdIBef.begin(), AdIBef.end());
-
+
MRI.cpReg2MemMI(instrnsBefore, Reg, MRI.getFramePointer(),
StackOff, RegType, scratchReg);
-
+
if (AdIAft.size() > 0)
instrnsBefore.insert(instrnsBefore.end(),
AdIAft.begin(), AdIAft.end());
-
+
//---- Insert code for popping the reg from the stack ----------
AdIBef.clear();
AdIAft.clear();
-
+
// We may need a scratch register to copy the saved value
// from memory. This may itself have to insert code to
// free up a scratch register. Any such code should go
CallMI, AdIBef, AdIAft);
assert(scratchReg != MRI.getInvalidRegNum());
}
-
+
if (AdIBef.size() > 0)
instrnsAfter.insert(instrnsAfter.end(),
AdIBef.begin(), AdIBef.end());
-
+
MRI.cpMem2RegMI(instrnsAfter, MRI.getFramePointer(), StackOff,
Reg, RegType, scratchReg);
-
+
if (AdIAft.size() > 0)
instrnsAfter.insert(instrnsAfter.end(),
AdIAft.begin(), AdIAft.end());
-
+
PushedRegSet.insert(Reg);
-
+
if(DEBUG_RA) {
std::cerr << "\nFor call inst:" << *CallMI;
std::cerr << " -inserted caller saving instrs: Before:\n\t ";
std::cerr << " -and After:\n\t ";
for_each(instrnsAfter.begin(), instrnsAfter.end(),
std::mem_fun(&MachineInstr::dump));
- }
+ }
} // if not already pushed
} // if LR has a volatile color
} // if LR has color
///
int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
const ValueSet *LVSetBef,
- MachineInstr *MInst,
+ MachineInstr *MInst,
std::vector<MachineInstr*>& MIBef,
std::vector<MachineInstr*>& MIAft) {
RegClass* RC = getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
-
+
int RegU = getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
-
+
if (RegU == -1) {
// we couldn't find an unused register. Generate code to free up a reg by
// saving it on stack and restoring after the instruction
-
+
int TmpOff = MF->getInfo<SparcV9FunctionInfo>()->pushTempValue(MRI.getSpilledRegSize(RegType));
-
+
RegU = getUniRegNotUsedByThisInst(RC, RegType, MInst);
-
+
// Check if we need a scratch register to copy this register to memory.
int scratchRegType = -1;
if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType)) {
int scratchReg = getUsableUniRegAtMI(scratchRegType, LVSetBef,
MInst, MIBef, MIAft);
assert(scratchReg != MRI.getInvalidRegNum());
-
+
// We may as well hold the value in the scratch register instead
// of copying it to memory and back. But we have to mark the
// register as used by this instruction, so it does not get used
MRI.cpMem2RegMI(MIAft, MRI.getFramePointer(), TmpOff, RegU, RegType);
}
}
-
+
return RegU;
}
// for each live var in live variable set after machine inst
for ( ; LIt != LVSetBef->end(); ++LIt) {
// Get the live range corresponding to live var, and its RegClass
- LiveRange *const LRofLV = LRI->getLiveRangeForValue(*LIt );
+ LiveRange *const LRofLV = LRI->getLiveRangeForValue(*LIt );
- // LR can be null if it is a const since a const
+ // LR can be null if it is a const since a const
// doesn't have a dominating def - see Assumptions above
if (LRofLV && LRofLV->getRegClass() == RC && LRofLV->hasColor())
RC->markColorsUsed(LRofLV->getColor(),
/// Return the unified register number of a register in class RC which is not
/// used by any operands of MInst.
///
-int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
+int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
const int RegType,
const MachineInstr *MInst) {
RC->clearColorsUsed();
// If there are implicit references, mark their allocated regs as well
for (unsigned z=0; z < MI->getNumImplicitRefs(); z++)
if (const LiveRange*
- LRofImpRef = LRI->getLiveRangeForValue(MI->getImplicitRef(z)))
+ LRofImpRef = LRI->getLiveRangeForValue(MI->getImplicitRef(z)))
if (LRofImpRef->hasColor())
// this implicit reference is in a LR that received a color
RC->markColorsUsed(LRofImpRef->getColor(),
///
void PhyRegAlloc::markUnusableSugColors()
{
- LiveRangeMapType::const_iterator HMI = (LRI->getLiveRangeMap())->begin();
- LiveRangeMapType::const_iterator HMIEnd = (LRI->getLiveRangeMap())->end();
+ LiveRangeMapType::const_iterator HMI = (LRI->getLiveRangeMap())->begin();
+ LiveRangeMapType::const_iterator HMIEnd = (LRI->getLiveRangeMap())->end();
for (; HMI != HMIEnd ; ++HMI ) {
- if (HMI->first) {
+ if (HMI->first) {
LiveRange *L = HMI->second; // get the LiveRange
if (L && L->hasSuggestedColor ())
L->setSuggestedColorUsable
void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
if (DEBUG_RA) std::cerr << "\nSetting LR stack offsets for spills...\n";
- LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
- LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
+ LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
+ LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
for ( ; HMI != HMIEnd ; ++HMI) {
if (HMI->first && HMI->second) {
void PhyRegAlloc::saveStateForValue (std::vector<AllocInfo> &state,
const Value *V, int Insn, int Opnd) {
- LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap ()->find (V);
- LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap ()->end ();
- AllocInfo::AllocStateTy AllocState = AllocInfo::NotAllocated;
- int Placement = -1;
- if ((HMI != HMIEnd) && HMI->second) {
- LiveRange *L = HMI->second;
- assert ((L->hasColor () || L->isMarkedForSpill ())
- && "Live range exists but not colored or spilled");
- if (L->hasColor ()) {
- AllocState = AllocInfo::Allocated;
- Placement = MRI.getUnifiedRegNum (L->getRegClassID (),
- L->getColor ());
- } else if (L->isMarkedForSpill ()) {
- AllocState = AllocInfo::Spilled;
- assert (L->hasSpillOffset ()
- && "Live range marked for spill but has no spill offset");
- Placement = L->getSpillOffFromFP ();
- }
- }
- state.push_back (AllocInfo (Insn, Opnd, AllocState, Placement));
+ LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap ()->find (V);
+ LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap ()->end ();
+ AllocInfo::AllocStateTy AllocState = AllocInfo::NotAllocated;
+ int Placement = -1;
+ if ((HMI != HMIEnd) && HMI->second) {
+ LiveRange *L = HMI->second;
+ assert ((L->hasColor () || L->isMarkedForSpill ())
+ && "Live range exists but not colored or spilled");
+ if (L->hasColor ()) {
+ AllocState = AllocInfo::Allocated;
+ Placement = MRI.getUnifiedRegNum (L->getRegClassID (),
+ L->getColor ());
+ } else if (L->isMarkedForSpill ()) {
+ AllocState = AllocInfo::Spilled;
+ assert (L->hasSpillOffset ()
+ && "Live range marked for spill but has no spill offset");
+ Placement = L->getSpillOffFromFP ();
+ }
+ }
+ state.push_back (AllocInfo (Insn, Opnd, AllocState, Placement));
}
}
-bool PhyRegAlloc::doFinalization (Module &M) {
+bool PhyRegAlloc::doFinalization (Module &M) {
if (SaveRegAllocState) finishSavingState (M);
return false;
}
/// Allocate registers for the machine code previously generated for F using
/// the graph-coloring algorithm.
///
-bool PhyRegAlloc::runOnFunction (Function &F) {
- if (DEBUG_RA)
- std::cerr << "\n********* Function "<< F.getName () << " ***********\n";
-
- Fn = &F;
- MF = &MachineFunction::get (Fn);
- LVI = &getAnalysis<FunctionLiveVarInfo> ();
- LRI = new LiveRangeInfo (Fn, TM, RegClassList);
- LoopDepthCalc = &getAnalysis<LoopInfo> ();
-
- // Create each RegClass for the target machine and add it to the
+bool PhyRegAlloc::runOnFunction (Function &F) {
+ if (DEBUG_RA)
+ std::cerr << "\n********* Function "<< F.getName () << " ***********\n";
+
+ Fn = &F;
+ MF = &MachineFunction::get (Fn);
+ LVI = &getAnalysis<FunctionLiveVarInfo> ();
+ LRI = new LiveRangeInfo (Fn, TM, RegClassList);
+ LoopDepthCalc = &getAnalysis<LoopInfo> ();
+
+ // Create each RegClass for the target machine and add it to the
// RegClassList. This must be done before calling constructLiveRanges().
- for (unsigned rc = 0; rc != NumOfRegClasses; ++rc)
- RegClassList.push_back (new RegClass (Fn, TM.getRegInfo(),
- MRI.getMachineRegClass(rc)));
-
+ for (unsigned rc = 0; rc != NumOfRegClasses; ++rc)
+ RegClassList.push_back (new RegClass (Fn, TM.getRegInfo(),
+ MRI.getMachineRegClass(rc)));
+
LRI->constructLiveRanges(); // create LR info
if (DEBUG_RA >= RA_DEBUG_LiveRanges)
LRI->printLiveRanges();
-
+
createIGNodeListsAndIGs(); // create IGNode list and IGs
buildInterferenceGraphs(); // build IGs in all reg classes
-
+
if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
// print all LRs in all reg classes
- for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
- RegClassList[rc]->printIGNodeList();
-
+ for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
+ RegClassList[rc]->printIGNodeList();
+
// print IGs in all register classes
- for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
- RegClassList[rc]->printIG();
+ for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
+ RegClassList[rc]->printIG();
}
LRI->coalesceLRs(); // coalesce all live ranges
// print all LRs in all reg classes
for (unsigned rc=0; rc < NumOfRegClasses; rc++)
RegClassList[rc]->printIGNodeList();
-
+
// print IGs in all register classes
for (unsigned rc=0; rc < NumOfRegClasses; rc++)
RegClassList[rc]->printIG();
// mark un-usable suggested color before graph coloring algorithm.
// When this is done, the graph coloring algo will not reserve
// suggested color unnecessarily - they can be used by another LR
- markUnusableSugColors();
+ markUnusableSugColors();
// color all register classes using the graph coloring algo
- for (unsigned rc=0; rc < NumOfRegClasses ; rc++)
- RegClassList[rc]->colorAllRegs();
+ for (unsigned rc=0; rc < NumOfRegClasses ; rc++)
+ RegClassList[rc]->colorAllRegs();
// After graph coloring, if some LRs did not receive a color (i.e, spilled)
// a position for such spilled LRs
// Now update the machine code with register names and add any additional
// code inserted by the register allocator to the instruction stream.
- updateMachineCode();
+ updateMachineCode();
if (SaveRegAllocState && !SaveStateToModule)
finishSavingState (const_cast<Module&> (*Fn->getParent ()));
std::cerr << "\n**** Machine Code After Register Allocation:\n\n";
MF->dump();
}
-
- // Tear down temporary data structures
- for (unsigned rc = 0; rc < NumOfRegClasses; ++rc)
- delete RegClassList[rc];
- RegClassList.clear ();
- AddedInstrMap.clear ();
- OperandsColoredMap.clear ();
- ScratchRegsUsed.clear ();
- AddedInstrAtEntry.clear ();
+
+ // Tear down temporary data structures
+ for (unsigned rc = 0; rc < NumOfRegClasses; ++rc)
+ delete RegClassList[rc];
+ RegClassList.clear ();
+ AddedInstrMap.clear ();
+ OperandsColoredMap.clear ();
+ ScratchRegsUsed.clear ();
+ AddedInstrAtEntry.clear ();
delete LRI;
- if (DEBUG_RA) std::cerr << "\nRegister allocation complete!\n";
+ if (DEBUG_RA) std::cerr << "\nRegister allocation complete!\n";
return false; // Function was not modified
-}
+}
} // End llvm namespace
//===-- PhyRegAlloc.h - Graph Coloring Register Allocator -------*- c++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This is the main entry point for register allocation.
//
// Notes:
-// * RegisterClasses: Each RegClass accepts a
+// * RegisterClasses: Each RegClass accepts a
// TargetRegClass which contains machine specific info about that register
// class. The code in the RegClass is machine independent and they use
// access functions in the TargetRegClass object passed into it to get
#include "LiveRangeInfo.h"
#include "llvm/Pass.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
-#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetMachine.h"
#include "../SparcV9RegInfo.h"
#include <map>
//----------------------------------------------------------------------------
// Class AddedInstrns:
-// When register allocator inserts new instructions in to the existing
+// When register allocator inserts new instructions in to the existing
// instruction stream, it does NOT directly modify the instruction stream.
-// Rather, it creates an object of AddedInstrns and stick it in the
+// Rather, it creates an object of AddedInstrns and stick it in the
// AddedInstrMap for an existing instruction. This class contains two vectors
// to store such instructions added before and after an existing instruction.
//----------------------------------------------------------------------------
const TargetMachine &TM; // target machine
const Function *Fn; // name of the function we work on
MachineFunction *MF; // descriptor for method's native code
- FunctionLiveVarInfo *LVI; // LV information for this method
- // (already computed for BBs)
+ FunctionLiveVarInfo *LVI; // LV information for this method
+ // (already computed for BBs)
LiveRangeInfo *LRI; // LR info (will be computed)
const SparcV9RegInfo &MRI; // Machine Register information
const unsigned NumOfRegClasses; // recorded here for efficiency
// updated according to their assigned colors. This is only used in
// assertion checking (debug builds).
std::map<const MachineInstr *, bool> OperandsColoredMap;
-
+
// AddedInstrMap - Used to store instrns added in this phase
std::map<const MachineInstr *, AddedInstrns> AddedInstrMap;
ScratchRegsUsedTy ScratchRegsUsed;
AddedInstrns AddedInstrAtEntry; // to store instrns added at entry
- const LoopInfo *LoopDepthCalc; // to calculate loop depths
+ const LoopInfo *LoopDepthCalc; // to calculate loop depths
PhyRegAlloc(const PhyRegAlloc&); // DO NOT IMPLEMENT
void operator=(const PhyRegAlloc&); // DO NOT IMPLEMENT
private:
SavedStateMapTy FnAllocState;
- void addInterference(const Value *Def, const ValueSet *LVSet,
+ void addInterference(const Value *Def, const ValueSet *LVSet,
bool isCallInst);
bool markAllocatedRegs(MachineInstr* MInst);
void saveState();
void finishSavingState(Module &M);
- void setCallInterferences(const MachineInstr *MI,
+ void setCallInterferences(const MachineInstr *MI,
const ValueSet *LVSetAft);
- void move2DelayedInstr(const MachineInstr *OrigMI,
+ void move2DelayedInstr(const MachineInstr *OrigMI,
const MachineInstr *DelayedMI);
void markUnusableSugColors();
void allocateStackSpace4SpilledLRs();
- void insertCode4SpilledLR(const LiveRange *LR,
+ void insertCode4SpilledLR(const LiveRange *LR,
MachineBasicBlock::iterator& MII,
MachineBasicBlock &MBB, unsigned OpNum);
MachineInstr *MI,
std::vector<MachineInstr*>& MIBef,
std::vector<MachineInstr*>& MIAft);
-
- /// Callback method used to find unused registers.
+
+ /// Callback method used to find unused registers.
/// LVSetBef is the live variable set to search for an unused register.
/// If it is not specified, the LV set before the current MI is used.
/// This is sufficient as long as no new copy instructions are generated
/// to copy the free register to memory.
- ///
+ ///
int getUnusedUniRegAtMI(RegClass *RC, int RegType,
const MachineInstr *MI,
const ValueSet *LVSetBef = 0);
-
+
void setRelRegsUsedByThisInst(RegClass *RC, int RegType,
const MachineInstr *MI);
//===-- RegAllocCommon.h --------------------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// Shared declarations for register allocation.
-//
+//
//===----------------------------------------------------------------------===//
#ifndef REGALLOCCOMMON_H
//===-- RegClass.cpp -----------------------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// class RegClass for coloring-based register allocation for LLVM.
-//
+//
//===----------------------------------------------------------------------===//
#include "IGNode.h"
namespace llvm {
//----------------------------------------------------------------------------
-// This constructor inits IG. The actual matrix is created by a call to
+// This constructor inits IG. The actual matrix is created by a call to
// createInterferenceGraph() above.
//----------------------------------------------------------------------------
-RegClass::RegClass(const Function *M,
+RegClass::RegClass(const Function *M,
const SparcV9RegInfo *_MRI_,
const TargetRegClassInfo *_MRC_)
: Meth(M), MRI(_MRI_), MRC(_MRC_),
// pre-color IGNodes
pushAllIGNodes(); // push all IG Nodes
- unsigned int StackSize = IGNodeStack.size();
+ unsigned int StackSize = IGNodeStack.size();
IGNode *CurIGNode;
// for all LRs on stack
- for (unsigned int IGN=0; IGN < StackSize; IGN++) {
+ for (unsigned int IGN=0; IGN < StackSize; IGN++) {
CurIGNode = IGNodeStack.top(); // pop the IGNode on top of stack
IGNodeStack.pop();
colorIGNode (CurIGNode); // color it
//----------------------------------------------------------------------------
void RegClass::pushAllIGNodes()
{
- bool NeedMoreSpills;
+ bool NeedMoreSpills;
IG.setCurDegreeOfIGNodes(); // calculate degree of IGNodes
// push non-constrained IGNodes
- bool PushedAll = pushUnconstrainedIGNodes();
+ bool PushedAll = pushUnconstrainedIGNodes();
if (DEBUG_RA >= RA_DEBUG_Coloring) {
std::cerr << " Puhsed all-unconstrained IGNodes. ";
return;
- // now, we have constrained nodes. So, push one of them (the one with min
- // spill cost) and try to push the others as unConstrained nodes.
+ // now, we have constrained nodes. So, push one of them (the one with min
+ // spill cost) and try to push the others as unConstrained nodes.
// Repeat this.
do {
//get node with min spill cost
- IGNode *IGNodeSpill = getIGNodeWithMinSpillCost();
+ IGNode *IGNodeSpill = getIGNodeWithMinSpillCost();
// push that node on to stack
IGNodeStack.push(IGNodeSpill);
- // set its OnStack flag and decrement degree of neighs
- IGNodeSpill->pushOnStack();
+ // set its OnStack flag and decrement degree of neighs
+ IGNodeSpill->pushOnStack();
// now push NON-constrained ones, if any
- NeedMoreSpills = !pushUnconstrainedIGNodes();
+ NeedMoreSpills = !pushUnconstrainedIGNodes();
if (DEBUG_RA >= RA_DEBUG_Coloring)
std::cerr << "\nConstrained IG Node found !@!" << IGNodeSpill->getIndex();
- } while(NeedMoreSpills); // repeat until we have pushed all
+ } while(NeedMoreSpills); // repeat until we have pushed all
}
//--------------------------------------------------------------------------
-// This method goes thru all IG nodes in the IGNodeList of an IG of a
+// This method goes thru all IG nodes in the IGNodeList of an IG of a
// register class and push any unconstrained IG node left (that is not
// already pushed)
//--------------------------------------------------------------------------
-bool RegClass::pushUnconstrainedIGNodes()
+bool RegClass::pushUnconstrainedIGNodes()
{
- // # of LRs for this reg class
- unsigned int IGNodeListSize = IG.getIGNodeList().size();
+ // # of LRs for this reg class
+ unsigned int IGNodeListSize = IG.getIGNodeList().size();
bool pushedall = true;
// a pass over IGNodeList
for (unsigned i =0; i < IGNodeListSize; i++) {
// get IGNode i from IGNodeList
- IGNode *IGNode = IG.getIGNodeList()[i];
+ IGNode *IGNode = IG.getIGNodeList()[i];
- if (!IGNode ) // can be null due to merging
+ if (!IGNode ) // can be null due to merging
continue;
-
+
// if already pushed on stack, continue. This can happen since this
// method can be called repeatedly until all constrained nodes are
// pushed
}
}
else pushedall = false; // we didn't push all live ranges
-
+
} // for
-
+
// returns true if we pushed all live ranges - else false
- return pushedall;
+ return pushedall;
}
// Get the IGNode with the minimum spill cost
//----------------------------------------------------------------------------
IGNode * RegClass::getIGNodeWithMinSpillCost() {
- unsigned int IGNodeListSize = IG.getIGNodeList().size();
+ unsigned int IGNodeListSize = IG.getIGNodeList().size();
double MinSpillCost = 0;
IGNode *MinCostIGNode = NULL;
bool isFirstNode = true;
// among all IGNodes that are not yet pushed on to the stack
for (unsigned int i =0; i < IGNodeListSize; i++) {
IGNode *IGNode = IG.getIGNodeList()[i];
-
+
if (!IGNode) // can be null due to merging
continue;
if (!IGNode->isOnStack()) {
double SpillCost = (double) IGNode->getParentLR()->getSpillCost() /
(double) (IGNode->getCurDegree() + 1);
-
+
if (isFirstNode) { // for the first IG node
MinSpillCost = SpillCost;
MinCostIGNode = IGNode;
}
}
}
-
+
assert (MinCostIGNode && "No IGNode to spill");
return MinCostIGNode;
}
//----------------------------------------------------------------------------
void RegClass::colorIGNode(IGNode *const Node) {
if (! Node->hasColor()) { // not colored as an arg etc.
-
+
// init all elements of to IsColorUsedAr false;
clearColorsUsed();
for (unsigned n=0; n < NumNeighbors; n++) {
IGNode *NeighIGNode = Node->getAdjIGNode(n);
LiveRange *NeighLR = NeighIGNode->getParentLR();
-
+
// Don't use a color if it is in use by the neighbor,
// or is suggested for use by the neighbor,
// markColorsUsed() should be given the color and the reg type for
void RegClass::printIGNodeList() const {
std::cerr << "IG Nodes for Register Class " << RegClassID << ":" << "\n";
- IG.printIGNodeList();
+ IG.printIGNodeList();
}
-void RegClass::printIG() {
+void RegClass::printIG() {
std::cerr << "IG for Register Class " << RegClassID << ":" << "\n";
- IG.printIG();
+ IG.printIG();
}
} // End llvm namespace
//===-- RegClass.h - Machine Independent register coloring ------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
/* Title: RegClass.h -*- C++ -*-
//-----------------------------------------------------------------------------
// Class RegClass
//
-// Implements a machine independent register class.
+// Implements a machine independent register class.
//
// This is the class that contains all data structures and common algos
-// for coloring a particular register class (e.g., int class, fp class).
-// This class is hardware independent. This class accepts a hardware
-// dependent description of machine registers (TargetRegInfo class) to
+// for coloring a particular register class (e.g., int class, fp class).
+// This class is hardware independent. This class accepts a hardware
+// dependent description of machine registers (TargetRegInfo class) to
// get hardware specific info and to color an individual IG node.
//
// This class contains the InterferenceGraph (IG).
-// Also it contains an IGNode stack that can be used for coloring.
+// Also it contains an IGNode stack that can be used for coloring.
// The class provides some easy access methods to the IG methods, since these
// methods are called thru a register class.
//
//-----------------------------------------------------------------------------
class RegClass {
const Function *const Meth; // Function we are working on
- const SparcV9RegInfo *MRI; // Machine register information
+ const SparcV9RegInfo *MRI; // Machine register information
const TargetRegClassInfo *const MRC; // Machine reg. class for this RegClass
const unsigned RegClassID; // my int ID
// main method called for coloring regs
//
- void colorAllRegs();
+ void colorAllRegs();
- inline unsigned getNumOfAvailRegs() const
+ inline unsigned getNumOfAvailRegs() const
{ return MRC->getNumOfAvailRegs(); }
// --- following methods are provided to access the IG contained within this
// ---- RegClass easilly.
- inline void addLRToIG(LiveRange *const LR)
+ inline void addLRToIG(LiveRange *const LR)
{ IG.addLRToIG(LR); }
inline void setInterference(const LiveRange *const LR1,
- const LiveRange *const LR2)
+ const LiveRange *const LR2)
{ IG.setInterference(LR1, LR2); }
inline unsigned getInterference(const LiveRange *const LR1,
- const LiveRange *const LR2) const
+ const LiveRange *const LR2) const
{ return IG.getInterference(LR1, LR2); }
inline void mergeIGNodesOfLRs(const LiveRange *const LR1,
- LiveRange *const LR2)
+ LiveRange *const LR2)
{ IG.mergeIGNodesOfLRs(LR1, LR2); }
//===-- SparcV9AsmPrinter.cpp - Emit SparcV9 Specific .s File --------------==//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file implements all of the stuff necessary to output a .s file from
/// Get the size of the constant for the given target.
/// If this is an unsized array, return 0.
- ///
+ ///
inline unsigned int
ConstantToSize(const Constant* CV, const TargetMachine& target) {
if (const ConstantArray* CVA = dyn_cast<ConstantArray>(CV)) {
if (ArrayTypeIsString(aty))
return 1 + CVA->getNumOperands();
}
-
+
return findOptimalStorageSize(target, CV->getType());
}
/// Align data larger than one L1 cache line on L1 cache line boundaries.
/// Align all smaller data on the next higher 2^x boundary (4, 8, ...).
- ///
+ ///
inline unsigned int
SizeToAlignment(unsigned int size, const TargetMachine& target) {
const unsigned short cacheLineSize = 16;
}
/// Get the size of the type and then use SizeToAlignment.
- ///
+ ///
inline unsigned int
TypeToAlignment(const Type* type, const TargetMachine& target) {
return SizeToAlignment(findOptimalStorageSize(target, type), target);
if (const ConstantArray* CVA = dyn_cast<ConstantArray>(CV))
if (ArrayTypeIsString(cast<ArrayType>(CVA->getType())))
return SizeToAlignment(1 + CVA->getNumOperands(), target);
-
+
return TypeToAlignment(CV->getType(), target);
}
AsmPrinter(std::ostream &os, const TargetMachine &T)
: /* idTable(0), */ O(os), TM(T), CurSection(Unknown) {}
-
+
~AsmPrinter() {
delete Mang;
}
void printConstant(const Constant* CV, std::string valID = "") {
if (valID.length() == 0)
valID = getID(CV);
-
+
O << "\t.align\t" << ConstantToAlignment(CV, TM) << "\n";
-
+
// Print .size and .type only if it is not a string.
if (const ConstantArray *CVA = dyn_cast<ConstantArray>(CV))
if (CVA->isString()) {
O << "\t" << ".ascii" << "\t" << getAsCString(CVA) << "\n";
return;
}
-
+
O << "\t.type" << "\t" << valID << ",#object\n";
unsigned int constSize = ConstantToSize(CV, TM);
if (constSize)
O << "\t.size" << "\t" << valID << "," << constSize << "\n";
-
+
O << valID << ":\n";
-
+
printConstantValueOnly(CV);
}
return "";
}
- // Combines expressions
+ // Combines expressions
inline std::string ConstantArithExprToString(const ConstantExpr* CE,
const TargetMachine &TM,
const std::string &op) {
/// valToExprString - Helper function for ConstantExprToString().
/// Appends result to argument string S.
- ///
+ ///
std::string valToExprString(const Value* V, const TargetMachine& target);
};
} // End anonymous namespace
assert(CV->getType() != Type::VoidTy &&
CV->getType() != Type::LabelTy &&
"Unexpected type for Constant");
-
+
assert((!isa<ConstantArray>(CV) && ! isa<ConstantStruct>(CV))
&& "Aggregate types should be handled outside this function");
-
+
O << "\t" << TypeToDataDirective(CV->getType()) << "\t";
-
+
if (const GlobalValue* GV = dyn_cast<GlobalValue>(CV)) {
O << getID(GV) << "\n";
} else if (isa<ConstantPointerNull>(CV) || isa<UndefValue>(CV)) {
// Null pointer value
O << "0\n";
- } else if (const ConstantExpr* CE = dyn_cast<ConstantExpr>(CV)) {
+ } else if (const ConstantExpr* CE = dyn_cast<ConstantExpr>(CV)) {
// Constant expression built from operators, constants, and symbolic addrs
O << ConstantExprToString(CE, TM) << "\n";
} else if (CV->getType()->isPrimitiveType()) {
if (CV->getType() == Type::FloatTy) {
float FVal = (float)Val;
char *ProxyPtr = (char*)&FVal; // Abide by C TBAA rules
- O << *(unsigned int*)ProxyPtr;
+ O << *(unsigned int*)ProxyPtr;
} else if (CV->getType() == Type::DoubleTy) {
char *ProxyPtr = (char*)&Val; // Abide by C TBAA rules
- O << *(uint64_t*)ProxyPtr;
+ O << *(uint64_t*)ProxyPtr;
} else {
assert(0 && "Unknown floating point type!");
}
-
+
O << "\t! " << CV->getType()->getDescription()
<< " value: " << Val << "\n";
} else if (const ConstantBool *CB = dyn_cast<ConstantBool>(CV)) {
/// valToExprString - Helper function for ConstantExprToString().
/// Appends result to argument string S.
-///
+///
std::string AsmPrinter::valToExprString(const Value* V,
const TargetMachine& target) {
std::string S;
private :
void emitBasicBlock(const MachineBasicBlock &MBB);
void emitMachineInst(const MachineInstr *MI);
-
+
unsigned int printOperands(const MachineInstr *MI, unsigned int opNum);
void printOneOperand(const MachineOperand &Op, MachineOpCode opCode);
bool OpIsBranchTargetLabel(const MachineInstr *MI, unsigned int opNum);
bool OpIsMemoryAddressBase(const MachineInstr *MI, unsigned int opNum);
-
+
unsigned getOperandMask(unsigned Opcode) {
switch (Opcode) {
case V9::SUBccr:
MachineOpCode opCode)
{
bool needBitsFlag = true;
-
+
if (mop.isHiBits32())
O << "%lm(";
else if (mop.isLoBits32())
O << "%hm(";
else
needBitsFlag = false;
-
+
switch (mop.getType())
{
case MachineOperand::MO_VirtualRegister:
case MachineOperand::MO_MachineRegister:
{
int regNum = (int)mop.getReg();
-
+
if (regNum == TM.getRegInfo()->getInvalidRegNum()) {
// better to print code with NULL registers than to die
O << "<NULL VALUE>";
}
break;
}
-
+
case MachineOperand::MO_ConstantPoolIndex:
{
O << ".CPI_" << getID(currFunction)
{
const Value *Val = mop.getVRegValue();
assert(Val && "\tNULL Value in SparcV9AsmPrinter");
-
+
if (const BasicBlock *BB = dyn_cast<BasicBlock>(Val))
O << getID(BB);
else if (const Function *F = dyn_cast<Function>(Val))
assert(0 && "Unrecognized value in SparcV9AsmPrinter");
break;
}
-
+
case MachineOperand::MO_SignExtendedImmed:
O << mop.getImmedValue();
break;
case MachineOperand::MO_UnextendedImmed:
O << (uint64_t) mop.getImmedValue();
break;
-
+
default:
O << mop; // use dump field
break;
}
-
+
if (needBitsFlag)
O << ")";
}
O << "\t" << TM.getInstrInfo()->getName(Opcode) << "\t";
unsigned Mask = getOperandMask(Opcode);
-
+
bool NeedComma = false;
unsigned N = 1;
for (unsigned OpNum = 0; OpNum < MI->getNumOperands(); OpNum += N)
N = printOperands(MI, OpNum);
} else
N = 1;
-
+
O << "\n";
++EmittedInsts;
}
void SparcV9AsmPrinter::printGlobalVariable(const GlobalVariable* GV) {
if (GV->hasExternalLinkage())
O << "\t.global\t" << getID(GV) << "\n";
-
+
if (GV->hasInitializer() &&
!(GV->getInitializer()->isNullValue() ||
isa<UndefValue>(GV->getInitializer()))) {
//===- SparcV9BurgISel.cpp - SparcV9 BURG-based Instruction Selector ------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// SparcV9 BURG-based instruction selector. It uses the SSA graph to
class InstructionNode : public InstrTreeNode {
bool codeIsFoldedIntoParent;
-
+
public:
InstructionNode(Instruction *_instr);
static inline bool classof(const InstrTreeNode *N) {
return N->getNodeType() == InstrTreeNode::NTInstructionNode;
}
-
+
protected:
virtual void dumpNode(int indent) const;
};
class ConstantNode : public InstrTreeNode {
public:
- ConstantNode(Constant *constVal)
+ ConstantNode(Constant *constVal)
: InstrTreeNode(NTConstNode, (Value*)constVal) {
- opLabel = ConstantNodeOp;
+ opLabel = ConstantNodeOp;
}
Constant *getConstVal() const { return (Constant*) val;}
// Methods to support type inquiry through isa, cast, and dyn_cast:
/// instructions O and I if: (1) Instruction O computes an operand used
/// by instruction I, and (2) O and I are part of the same basic block,
/// and (3) O has only a single use, viz., I.
-///
+///
class InstrForest : private hash_map<const Instruction *, InstructionNode*> {
public:
// Use a vector for the root set to get a deterministic iterator
typedef std::vector<InstructionNode*> RootSet;
typedef RootSet:: iterator root_iterator;
typedef RootSet::const_iterator const_root_iterator;
-
+
private:
RootSet treeRoots;
-
+
public:
/*ctor*/ InstrForest (Function *F);
/*dtor*/ ~InstrForest ();
-
+
/// getTreeNodeForInstr - Returns the tree node for an Instruction.
///
inline InstructionNode *getTreeNodeForInstr(Instruction* instr) {
return (*this)[instr];
}
-
+
/// Iterators for the root nodes for all the trees.
///
const_root_iterator roots_begin() const { return treeRoots.begin(); }
root_iterator roots_begin() { return treeRoots.begin(); }
const_root_iterator roots_end () const { return treeRoots.end(); }
root_iterator roots_end () { return treeRoots.end(); }
-
+
void dump() const;
-
+
private:
// Methods used to build the instruction forest.
void eraseRoot (InstructionNode* node);
void InstrTreeNode::dump(int dumpChildren, int indent) const {
dumpNode(indent);
-
+
if (dumpChildren) {
if (LeftChild)
LeftChild->dump(dumpChildren, indent+1);
opLabel = I->getOpcode();
// Distinguish special cases of some instructions such as Ret and Br
- //
+ //
if (opLabel == Instruction::Ret && cast<ReturnInst>(I)->getReturnValue()) {
opLabel = RetValueOp; // ret(value) operation
}
void VRegListNode::dumpNode(int indent) const {
for (int i=0; i < indent; i++)
std::cerr << " ";
-
+
std::cerr << "List" << "\n";
}
void LabelNode::dumpNode(int indent) const {
for (int i=0; i < indent; i++)
std::cerr << " ";
-
+
std::cerr << "Label " << *getValue() << "\n";
}
assert(treeNode->getInstruction() == instr);
return treeNode;
}
-
+
// Otherwise, create a new tree node for this instruction.
treeNode = new InstructionNode(instr);
noteTreeNodeForInstr(instr, treeNode);
-
+
if (instr->getOpcode() == Instruction::Call) {
// Operands of call instruction
return treeNode;
}
-
+
// If the instruction has more than 2 instruction operands,
// then we need to create artificial list nodes to hold them.
// (Note that we only count operands that get tree nodes, and not
// if a fixed array is too small.
int numChildren = 0;
InstrTreeNode** childArray = new InstrTreeNode*[instr->getNumOperands()];
-
+
// Walk the operands of the instruction
for (Instruction::op_iterator O = instr->op_begin(); O!=instr->op_end();
++O) {
Value* operand = *O;
-
+
// Check if the operand is a data value, not an branch label, type,
// method or module. If the operand is an address type (i.e., label
// or method) that is used in an non-branching operation, e.g., `add'.
bool includeAddressOperand =
(isa<BasicBlock>(operand) || isa<Function>(operand))
&& !instr->isTerminator();
-
+
if (includeAddressOperand || isa<Instruction>(operand) ||
isa<Constant>(operand) || isa<Argument>(operand)) {
// This operand is a data value.
childArray[numChildren++] = opTreeNode;
}
}
-
+
// Add any selected operands as children in the tree.
// Certain instructions can have more than 2 in some instances (viz.,
// a CALL or a memory access -- LOAD, STORE, and GetElemPtr -- to an
// a right-leaning binary tree with the operand nodes at the leaves
// and VRegList nodes as internal nodes.
InstrTreeNode *parent = treeNode;
-
+
if (numChildren > 2) {
unsigned instrOpcode = treeNode->getInstruction()->getOpcode();
assert(instrOpcode == Instruction::PHI ||
instrOpcode == Instruction::Store ||
instrOpcode == Instruction::GetElementPtr);
}
-
+
// Insert the first child as a direct child
if (numChildren >= 1)
setLeftChild(parent, childArray[0]);
int n;
-
+
// Create a list node for children 2 .. N-1, if any
for (n = numChildren-1; n >= 2; n--) {
// We have more than two children
setLeftChild(listNode, childArray[numChildren - n]);
parent = listNode;
}
-
+
// Now insert the last remaining child (if any).
if (numChildren >= 2) {
assert(n == 1);
///
enum SelectDebugLevel_t {
Select_NoDebugInfo,
- Select_PrintMachineCode,
- Select_DebugInstTrees,
+ Select_PrintMachineCode,
+ Select_DebugInstTrees,
Select_DebugBurgTrees,
};
cl::opt<SelectDebugLevel_t>
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
}
-
+
bool runOnFunction(Function &F);
virtual const char *getPassName() const {
return "SparcV9 BURG Instruction Selector";
/// since the representation of int64_t and uint64_t are identical. The
/// argument can be any known const. isValidConstant is set to true if a valid
/// constant was found.
-///
+///
uint64_t ConvertConstantToIntType(const TargetMachine &target, const Value *V,
const Type *destType, bool &isValidConstant) {
isValidConstant = false;
unsigned destSize = target.getTargetData().getTypeSize(destType);
uint64_t maskHi = (destSize < 8)? (1U << 8*destSize) - 1 : ~0;
assert(opSize <= 8 && destSize <= 8 && ">8-byte int type unexpected");
-
+
if (destType->isSigned()) {
if (opSize > destSize) // operand is larger than dest:
C = C & maskHi; // mask high bits
miSETHI->getOperand(0).markHi32();
mvec.push_back(miSETHI);
}
-
+
// Set the low 10 or 12 bits in dest. This is necessary if no SETHI
// was generated, or if the low 10 bits are non-zero.
if (miSETHI==NULL || C & MAXLO) {
}
else
mvec.push_back(BuildMI(V9::ORr,3).addReg(tmpReg).addMReg(SparcV9::g0).addRegDef(dest));
-
+
assert((miSETHI || miOR) && "Oops, no code was generated!");
}
/// This function correctly emulates the SETSW pseudo-op for SPARC v9. It
/// optimizes the same cases as SETUWConst, plus:
/// (1) SRA is not needed for positive or small negative values.
-///
+///
static inline void
CreateSETSWConst(int32_t C,
- Instruction* dest, std::vector<MachineInstr*>& mvec,
+ Instruction* dest, std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi, Value* val) {
-
+
//TmpInstruction for intermediate values
TmpInstruction *tmpReg = new TmpInstruction(mcfi, (Instruction*) val);
/// left-shift-by-32 in between. This function correctly emulates the SETX
/// pseudo-op for SPARC v9. It optimizes the same cases as SETUWConst for each
/// 32 bit word.
-///
+///
static inline void
CreateSETXConst(uint64_t C,
Instruction* tmpReg, Instruction* dest,
- std::vector<MachineInstr*>& mvec,
+ std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi, Value* val) {
assert(C > (unsigned int) ~0 && "Use SETUW/SETSW for 32-bit values!");
-
+
MachineInstr* MI;
-
+
// Code to set the upper 32 bits of the value in register `tmpReg'
CreateSETUWConst((C >> 32), tmpReg, mvec, mcfi, val);
-
+
//TmpInstruction for intermediate values
TmpInstruction *tmpReg2 = new TmpInstruction(mcfi, (Instruction*) val);
// Shift tmpReg left by 32 bits
mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg).addZImm(32)
.addRegDef(tmpReg2));
-
+
//TmpInstruction for intermediate values
TmpInstruction *tmpReg3 = new TmpInstruction(mcfi, (Instruction*) val);
// Code to set the low 32 bits of the value in register `dest'
CreateSETUWConst(C, tmpReg3, mvec, mcfi, val);
-
+
// dest = OR(tmpReg, dest)
mvec.push_back(BuildMI(V9::ORr,3).addReg(tmpReg3).addReg(tmpReg2).addRegDef(dest));
}
/// CreateSETUWLabel - Set a 32-bit constant (given by a symbolic label) in
/// the register `dest'.
-///
+///
static inline void
CreateSETUWLabel(Value* val,
Instruction* dest, std::vector<MachineInstr*>& mvec) {
MachineInstr* MI;
-
+
MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get((Instruction*) val);
TmpInstruction* tmpReg = new TmpInstruction(mcfi, val);
MI = BuildMI(V9::SETHI, 2).addReg(val).addRegDef(tmpReg);
MI->getOperand(0).markHi32();
mvec.push_back(MI);
-
+
// Set the low 10 bits in dest
MI = BuildMI(V9::ORr, 3).addReg(tmpReg).addReg(val).addRegDef(dest);
MI->getOperand(1).markLo32();
/// CreateSETXLabel - Set a 64-bit constant (given by a symbolic label) in the
/// register `dest'.
-///
+///
static inline void
CreateSETXLabel(Value* val, Instruction* tmpReg,
- Instruction* dest, std::vector<MachineInstr*>& mvec,
+ Instruction* dest, std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi) {
- assert(isa<Constant>(val) &&
+ assert(isa<Constant>(val) &&
"I only know about constant values and global addresses");
-
+
MachineInstr* MI;
-
+
MI = BuildMI(V9::SETHI, 2).addPCDisp(val).addRegDef(tmpReg);
MI->getOperand(0).markHi64();
mvec.push_back(MI);
-
+
TmpInstruction* tmpReg2 =
new TmpInstruction(mcfi, PointerType::get(val->getType()), val);
MI = BuildMI(V9::ORi, 3).addReg(tmpReg).addPCDisp(val).addRegDef(tmpReg2);
MI->getOperand(1).markLo64();
mvec.push_back(MI);
-
+
TmpInstruction* tmpReg3 =
new TmpInstruction(mcfi, PointerType::get(val->getType()), val);
MI = BuildMI(V9::SETHI, 2).addPCDisp(val).addRegDef(tmpReg4);
MI->getOperand(0).markHi32();
mvec.push_back(MI);
-
+
TmpInstruction* tmpReg5 =
new TmpInstruction(mcfi, PointerType::get(val->getType()), val);
MI = BuildMI(V9::ORr, 3).addReg(tmpReg4).addReg(tmpReg3).addRegDef(tmpReg5);
mvec.push_back(MI);
-
+
MI = BuildMI(V9::ORi, 3).addReg(tmpReg5).addPCDisp(val).addRegDef(dest);
MI->getOperand(1).markLo32();
mvec.push_back(MI);
/// as needed. CreateSETSWConst is an optimization for the case that the
/// unsigned value has all ones in the 33 high bits (so that sign-extension sets
/// them all).
-///
+///
static inline void
CreateUIntSetInstruction(uint64_t C, Instruction* dest,
std::vector<MachineInstr*>& mvec,
/// CreateIntSetInstruction - Create code to Set a signed constant in the
/// register `dest'. Really the same as CreateUIntSetInstruction.
-///
+///
static inline void
CreateIntSetInstruction(int64_t C, Instruction* dest,
std::vector<MachineInstr*>& mvec,
/// MaxConstantsTableTy - Table mapping LLVM opcodes to the max. immediate
/// constant usable for that operation in the SparcV9 backend. Used by
/// ConstantMayNotFitInImmedField().
-///
+///
struct MaxConstantsTableTy {
// Entry == 0 ==> no immediate constant field exists at all.
// Entry > 0 ==> abs(immediate constant) <= Entry
switch(llvmOpCode) {
case Instruction::Ret: modelOpCode = V9::JMPLCALLi; break;
- case Instruction::Malloc:
- case Instruction::Alloca:
- case Instruction::GetElementPtr:
- case Instruction::PHI:
+ case Instruction::Malloc:
+ case Instruction::Alloca:
+ case Instruction::GetElementPtr:
+ case Instruction::PHI:
case Instruction::Cast:
case Instruction::Call: modelOpCode = V9::ADDi; break;
/// ChooseLoadInstruction - Return the appropriate load instruction opcode
/// based on the given LLVM value type.
-///
+///
static inline MachineOpCode ChooseLoadInstruction(const Type *DestTy) {
switch (DestTy->getTypeID()) {
case Type::BoolTyID:
/// ChooseStoreInstruction - Return the appropriate store instruction opcode
/// based on the given LLVM value type.
-///
+///
static inline MachineOpCode ChooseStoreInstruction(const Type *DestTy) {
switch (DestTy->getTypeID()) {
case Type::BoolTyID:
switch(resultType->getTypeID()) {
case Type::FloatTyID: opCode = V9::FADDS; break;
case Type::DoubleTyID: opCode = V9::FADDD; break;
- default: assert(0 && "Invalid type for ADD instruction"); break;
+ default: assert(0 && "Invalid type for ADD instruction"); break;
}
-
+
return opCode;
}
/// (virtual register) to a Constant* (making an immediate field), we need to
/// change the opcode from a register-based instruction to an immediate-based
/// instruction, hence this mapping.
-///
+///
static unsigned convertOpcodeFromRegToImm(unsigned Opcode) {
switch (Opcode) {
/* arithmetic */
// It's already in correct format
// Or, it's just not handled yet, but an assert() would break LLC
#if 0
- std::cerr << "Unhandled opcode in convertOpcodeFromRegToImm(): " << Opcode
+ std::cerr << "Unhandled opcode in convertOpcodeFromRegToImm(): " << Opcode
<< "\n";
#endif
return Opcode;
/// The generated instructions are returned in `mvec'. Any temp. registers
/// (TmpInstruction) created are recorded in mcfi. Any stack space required is
/// allocated via MachineFunction.
-///
+///
void CreateCodeToLoadConst(const TargetMachine& target, Function* F,
Value* val, Instruction* dest,
std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi) {
assert(isa<Constant>(val) &&
"I only know about constant values and global addresses");
-
+
// Use a "set" instruction for known constants or symbolic constants (labels)
// that can go in an integer reg.
// We have to use a "load" instruction for all other constants,
// in particular, floating point constants.
const Type* valType = val->getType();
-
+
if (isa<GlobalValue>(val)) {
TmpInstruction* tmpReg =
new TmpInstruction(mcfi, PointerType::get(val->getType()), val);
// First, create a tmp register to be used by the SETX sequence.
TmpInstruction* tmpReg =
new TmpInstruction(mcfi, PointerType::get(val->getType()));
-
+
// Create another TmpInstruction for the address register
TmpInstruction* addrReg =
new TmpInstruction(mcfi, PointerType::get(val->getType()));
-
+
// Get the constant pool index for this constant
MachineConstantPool *CP = MachineFunction::get(F).getConstantPool();
Constant *C = cast<Constant>(val);
// Put the address of the constant into a register
MachineInstr* MI;
-
+
MI = BuildMI(V9::SETHI, 2).addConstantPoolIndex(CPI).addRegDef(tmpReg);
MI->getOperand(0).markHi64();
mvec.push_back(MI);
-
+
//Create another tmp register for the SETX sequence to preserve SSA
TmpInstruction* tmpReg2 =
new TmpInstruction(mcfi, PointerType::get(val->getType()));
-
+
MI = BuildMI(V9::ORi, 3).addReg(tmpReg).addConstantPoolIndex(CPI)
.addRegDef(tmpReg2);
MI->getOperand(1).markLo64();
mvec.push_back(MI);
-
+
//Create another tmp register for the SETX sequence to preserve SSA
TmpInstruction* tmpReg3 =
new TmpInstruction(mcfi, PointerType::get(val->getType()));
MI = BuildMI(V9::SETHI, 2).addConstantPoolIndex(CPI).addRegDef(addrReg);
MI->getOperand(0).markHi32();
mvec.push_back(MI);
-
+
// Create another TmpInstruction for the address register
TmpInstruction* addrReg2 =
new TmpInstruction(mcfi, PointerType::get(val->getType()));
-
+
MI = BuildMI(V9::ORr, 3).addReg(addrReg).addReg(tmpReg3).addRegDef(addrReg2);
mvec.push_back(MI);
-
+
// Create another TmpInstruction for the address register
TmpInstruction* addrReg3 =
new TmpInstruction(mcfi, PointerType::get(val->getType()));
/// memory and back. The generated instructions are returned in `mvec'. Any
/// temp. virtual registers (TmpInstruction) created are recorded in mcfi.
/// Temporary stack space required is allocated via MachineFunction.
-///
+///
void CreateCodeToCopyFloatToInt(const TargetMachine& target, Function* F,
Value* val, Instruction* dest,
std::vector<MachineInstr*>& mvec,
// FIXME: For now, we allocate permanent space because the stack frame
// manager does not allow locals to be allocated (e.g., for alloca) after
// a temp is allocated!
- int offset = MachineFunction::get(F).getInfo<SparcV9FunctionInfo>()->allocateLocalVar(val);
+ int offset = MachineFunction::get(F).getInfo<SparcV9FunctionInfo>()->allocateLocalVar(val);
unsigned FPReg = target.getRegInfo()->getFramePointer();
// Store instruction stores `val' to [%fp+offset].
// The store opCode is based only the source value being copied.
unsigned StoreOpcode = ChooseStoreInstruction(opTy);
- StoreOpcode = convertOpcodeFromRegToImm(StoreOpcode);
+ StoreOpcode = convertOpcodeFromRegToImm(StoreOpcode);
mvec.push_back(BuildMI(StoreOpcode, 3)
.addReg(val).addMReg(FPReg).addSImm(offset));
/// CreateBitExtensionInstructions - Helper function for sign-extension and
/// zero-extension. For SPARC v9, we sign-extend the given operand using SLL;
/// SRA/SRL.
-///
+///
inline void
CreateBitExtensionInstructions(bool signExtend, const TargetMachine& target,
Function* F, Value* srcVal, Value* destVal,
/// in bits, not bytes). The generated instructions are returned in `mvec'. Any
/// temp. registers (TmpInstruction) created are recorded in mcfi. Any stack
/// space required is allocated via MachineFunction.
-///
+///
void CreateSignExtensionInstructions(const TargetMachine& target,
Function* F, Value* srcVal, Value* destVal,
unsigned int numLowBits,
/// SLL; SRL. The generated instructions are returned in `mvec'. Any temp.
/// registers (TmpInstruction) created are recorded in mcfi. Any stack space
/// required is allocated via MachineFunction.
-///
+///
void CreateZeroExtensionInstructions(const TargetMachine& target,
Function* F, Value* srcVal, Value* destVal,
unsigned int numLowBits,
// Get a stack slot to use for the copy
int offset = MachineFunction::get(F).getInfo<SparcV9FunctionInfo>()->allocateLocalVar(val);
- // Get the size of the source value being copied.
+ // Get the size of the source value being copied.
size_t srcSize = target.getTargetData().getTypeSize(val->getType());
// Store instruction stores `val' to [%fp+offset].
/// InsertCodeToLoadConstant - Generates code to load the constant
/// into a TmpInstruction (virtual reg) and returns the virtual register.
-///
+///
static TmpInstruction*
InsertCodeToLoadConstant(Function *F, Value* opValue, Instruction* vmInstr,
std::vector<MachineInstr*>& loadConstVec,
// Create a tmp virtual register to hold the constant.
MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(vmInstr);
TmpInstruction* tmpReg = new TmpInstruction(mcfi, opValue);
-
+
CreateCodeToLoadConst(target, F, opValue, tmpReg, loadConstVec, mcfi);
-
+
// Record the mapping from the tmp VM instruction to machine instruction.
// Do this for all machine instructions that were not mapped to any
- // other temp values created by
+ // other temp values created by
// tmpReg->addMachineInstruction(loadConstVec.back());
return tmpReg;
}
/// for arbitrary types. The generated instructions are returned in `mvec'. Any
/// temp. registers (TmpInstruction) created are recorded in mcfi. Any stack
/// space required is allocated via MachineFunction.
-///
+///
void CreateCopyInstructionsByType(const TargetMachine& target,
Function *F, Value* src, Instruction* dest,
std::vector<MachineInstr*>& mvec,
MachineOperand::MachineOperandType opType =
ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
machineRegNum, immedValue);
-
+
if (opType == MachineOperand::MO_VirtualRegister)
loadConstantToReg = true;
}
-
- if (loadConstantToReg) {
+
+ if (loadConstantToReg) {
// `src' is constant and cannot fit in immed field for the ADD.
// Insert instructions to "load" the constant into a register.
CreateCodeToLoadConst(target, F, src, dest, mvec, mcfi);
- } else {
+ } else {
// Create a reg-to-reg copy instruction for the given type:
// -- For FP values, create a FMOVS or FMOVD instruction
// -- For non-FP values, create an add-with-0 instruction (opCode as above)
/// pool. In the first 2 cases, the operand of `minstr' is modified in place.
/// Returns a vector of machine instructions generated for operands that fall
/// under case 3; these must be inserted before `minstr'.
-///
+///
std::vector<MachineInstr*>
FixConstantOperandsForInstr(Instruction* vmInstr, MachineInstr* minstr,
TargetMachine& target) {
std::vector<MachineInstr*> MVec;
-
+
MachineOpCode opCode = minstr->getOpcode();
const TargetInstrInfo& instrInfo = *target.getInstrInfo();
int resultPos = instrInfo.get(opCode).resultPos;
for (unsigned op=0; op < minstr->getNumOperands(); op++) {
const MachineOperand& mop = minstr->getOperand(op);
-
+
// Skip the result position, preallocated machine registers, or operands
// that cannot be constants (CC regs or PC-relative displacements)
if (resultPos == (int)op ||
if (mop.getType() == MachineOperand::MO_VirtualRegister) {
assert(mop.getVRegValue() != NULL);
opValue = mop.getVRegValue();
- if (Constant *opConst = dyn_cast<Constant>(opValue))
+ if (Constant *opConst = dyn_cast<Constant>(opValue))
if (!isa<GlobalValue>(opConst)) {
opType = ChooseRegOrImmed(opConst, opCode, target,
(immedPos == (int)op), machineRegNum,
continue;
opType = ChooseRegOrImmed(mop.getImmedValue(), isSigned,
- opCode, target, (immedPos == (int)op),
+ opCode, target, (immedPos == (int)op),
machineRegNum, immedValue);
if (opType == MachineOperand::MO_SignExtendedImmed ||
minstr->setOpcode(newOpcode);
}
- if (opType == mop.getType())
+ if (opType == mop.getType())
continue; // no change: this is the most common case
if (opType == MachineOperand::MO_VirtualRegister) {
tmpReg);
}
}
-
+
// Also, check for implicit operands used by the machine instruction
// (no need to check those defined since they cannot be constants).
// These include:
CallArgsDescriptor* argDesc = NULL; // unused if not a call
if (isCall)
argDesc = CallArgsDescriptor::get(minstr);
-
+
for (unsigned i=0, N=minstr->getNumImplicitRefs(); i < N; ++i)
if (isa<Constant>(minstr->getImplicitRef(i))) {
Value* oldVal = minstr->getImplicitRef(i);
TmpInstruction* tmpReg =
InsertCodeToLoadConstant(F, oldVal, vmInstr, MVec, target);
minstr->setImplicitRef(i, tmpReg);
-
+
if (isCall) {
// find and replace the argument in the CallArgsDescriptor
unsigned i=lastCallArgNum;
argDesc->getArgInfo(i).replaceArgVal(tmpReg);
}
}
-
+
return MVec;
}
// If the first getElementPtr instruction had a leading [0], add it back.
// Note that this instruction is the *last* one that was successfully
// folded *and* contributed any indices, in the loop above.
- if (ptrVal && ! lastInstHasLeadingNonZero)
+ if (ptrVal && ! lastInstHasLeadingNonZero)
chainIdxVec.insert(chainIdxVec.begin(), ConstantSInt::get(Type::LongTy,0));
return ptrVal;
// Default pointer is the one from the current instruction.
Value* ptrVal = gepI->getPointerOperand();
- InstrTreeNode* ptrChild = gepNode->leftChild();
+ InstrTreeNode* ptrChild = gepNode->leftChild();
// Extract the index vector of the GEP instruction.
// If all indices are constant and first index is zero, try to fold
/// no code is generated for them. Returns the pointer Value to use, and
/// returns the resulting IndexVector in idxVec. Sets allConstantIndices
/// to true/false if all indices are/aren't const.
-///
+///
static Value *GetMemInstArgs(InstructionNode *memInstrNode,
std::vector<Value*> &idxVec,
bool& allConstantIndices) {
// right child for Store instructions.
InstrTreeNode* ptrChild = (memInst->getOpcode() == Instruction::Store
? memInstrNode->rightChild()
- : memInstrNode->leftChild());
-
+ : memInstrNode->leftChild());
+
// Default pointer is the one from the current instruction.
- Value* ptrVal = ptrChild->getValue();
+ Value* ptrVal = ptrChild->getValue();
// Find the "last" GetElemPtr instruction: this one or the immediate child.
// There will be none if this is a load or a store from a scalar pointer.
: ptrVal;
}
-static inline MachineOpCode
+static inline MachineOpCode
ChooseBprInstruction(const InstructionNode* instrNode) {
MachineOpCode opCode;
-
+
Instruction* setCCInstr =
((InstructionNode*) instrNode->leftChild())->getInstruction();
-
+
switch(setCCInstr->getOpcode()) {
case Instruction::SetEQ: opCode = V9::BRZ; break;
case Instruction::SetNE: opCode = V9::BRNZ; break;
default:
assert(0 && "Unrecognized VM instruction!");
opCode = V9::INVALID_OPCODE;
- break;
+ break;
}
-
+
return opCode;
}
-static inline MachineOpCode
+static inline MachineOpCode
ChooseBpccInstruction(const InstructionNode* instrNode,
const BinaryOperator* setCCInstr) {
MachineOpCode opCode = V9::INVALID_OPCODE;
-
+
bool isSigned = setCCInstr->getOperand(0)->getType()->isSigned();
-
+
if (isSigned) {
switch(setCCInstr->getOpcode()) {
case Instruction::SetEQ: opCode = V9::BE; break;
case Instruction::SetGT: opCode = V9::BG; break;
default:
assert(0 && "Unrecognized VM instruction!");
- break;
+ break;
}
} else {
switch(setCCInstr->getOpcode()) {
case Instruction::SetGT: opCode = V9::BGU; break;
default:
assert(0 && "Unrecognized VM instruction!");
- break;
+ break;
}
}
-
+
return opCode;
}
-static inline MachineOpCode
+static inline MachineOpCode
ChooseBFpccInstruction(const InstructionNode* instrNode,
const BinaryOperator* setCCInstr) {
MachineOpCode opCode = V9::INVALID_OPCODE;
-
+
switch(setCCInstr->getOpcode()) {
case Instruction::SetEQ: opCode = V9::FBE; break;
case Instruction::SetNE: opCode = V9::FBNE; break;
case Instruction::SetGT: opCode = V9::FBG; break;
default:
assert(0 && "Unrecognized VM instruction!");
- break;
+ break;
}
-
+
return opCode;
}
// into a separate class that can hold such information.
// The static cache is not too bad because the memory for these
// TmpInstructions will be freed along with the rest of the Function anyway.
-//
+//
static TmpInstruction *GetTmpForCC (Value* boolVal, const Function *F,
const Type* ccType,
MachineCodeForInstruction& mcfi) {
typedef hash_map<const Value*, TmpInstruction*> BoolTmpCache;
static BoolTmpCache boolToTmpCache; // Map boolVal -> TmpInstruction*
static const Function *lastFunction = 0;// Use to flush cache between funcs
-
+
assert(boolVal->getType() == Type::BoolTy && "Weird but ok! Delete assert");
-
+
if (lastFunction != F) {
lastFunction = F;
boolToTmpCache.clear();
}
-
+
// Look for tmpI and create a new one otherwise. The new value is
// directly written to map using the ref returned by operator[].
TmpInstruction*& tmpI = boolToTmpCache[boolVal];
if (tmpI == NULL)
tmpI = new TmpInstruction(mcfi, ccType, boolVal);
-
+
return tmpI;
}
-static inline MachineOpCode
+static inline MachineOpCode
ChooseBccInstruction(const InstructionNode* instrNode, const Type*& setCCType) {
InstructionNode* setCCNode = (InstructionNode*) instrNode->leftChild();
assert(setCCNode->getOpLabel() == SetCCOp);
BinaryOperator* setCCInstr =cast<BinaryOperator>(setCCNode->getInstruction());
setCCType = setCCInstr->getOperand(0)->getType();
-
+
if (setCCType->isFloatingPoint())
return ChooseBFpccInstruction(instrNode, setCCInstr);
else
/// two registers is required, then modify this function and use
/// convertOpcodeFromRegToImm() where required. It will be necessary to expand
/// convertOpcodeFromRegToImm() to handle the new cases of opcodes.
-///
-static inline MachineOpCode
+///
+static inline MachineOpCode
ChooseMovFpcciInstruction(const InstructionNode* instrNode) {
MachineOpCode opCode = V9::INVALID_OPCODE;
-
+
switch(instrNode->getInstruction()->getOpcode()) {
case Instruction::SetEQ: opCode = V9::MOVFEi; break;
case Instruction::SetNE: opCode = V9::MOVFNEi; break;
case Instruction::SetGT: opCode = V9::MOVFGi; break;
default:
assert(0 && "Unrecognized VM instruction!");
- break;
+ break;
}
-
+
return opCode;
}
/// ChooseMovpcciForSetCC -- Choose a conditional-move instruction
/// based on the type of SetCC operation.
-///
+///
/// WARNING: like the previous function, this function always returns
/// the opcode that expects an immediate and a register. See above.
-///
+///
static MachineOpCode ChooseMovpcciForSetCC(const InstructionNode* instrNode) {
MachineOpCode opCode = V9::INVALID_OPCODE;
const Type* opType = instrNode->leftChild()->getValue()->getType();
assert(opType->isIntegral() || isa<PointerType>(opType));
bool noSign = opType->isUnsigned() || isa<PointerType>(opType);
-
+
switch(instrNode->getInstruction()->getOpcode()) {
case Instruction::SetEQ: opCode = V9::MOVEi; break;
case Instruction::SetLE: opCode = noSign? V9::MOVLEUi : V9::MOVLEi; break;
case Instruction::SetLT: opCode = noSign? V9::MOVCSi : V9::MOVLi; break;
case Instruction::SetGT: opCode = noSign? V9::MOVGUi : V9::MOVGi; break;
case Instruction::SetNE: opCode = V9::MOVNEi; break;
- default: assert(0 && "Unrecognized LLVM instr!"); break;
+ default: assert(0 && "Unrecognized LLVM instr!"); break;
}
-
+
return opCode;
}
/// ChooseMovpregiForSetCC -- Choose a conditional-move-on-register-value
/// instruction based on the type of SetCC operation. These instructions
/// compare a register with 0 and perform the move is the comparison is true.
-///
+///
/// WARNING: like the previous function, this function it always returns
/// the opcode that expects an immediate and a register. See above.
-///
+///
static MachineOpCode ChooseMovpregiForSetCC(const InstructionNode* instrNode) {
MachineOpCode opCode = V9::INVALID_OPCODE;
-
+
switch(instrNode->getInstruction()->getOpcode()) {
case Instruction::SetEQ: opCode = V9::MOVRZi; break;
case Instruction::SetLE: opCode = V9::MOVRLEZi; break;
case Instruction::SetLT: opCode = V9::MOVRLZi; break;
case Instruction::SetGT: opCode = V9::MOVRGZi; break;
case Instruction::SetNE: opCode = V9::MOVRNZi; break;
- default: assert(0 && "Unrecognized VM instr!"); break;
+ default: assert(0 && "Unrecognized VM instr!"); break;
}
-
+
return opCode;
}
assert(opSize == 8 && "Unrecognized type size > 4 and < 8!");
opCode = (vopCode == ToFloatTy? V9::FXTOS : V9::FXTOD);
}
-
+
return opCode;
}
-static inline MachineOpCode
+static inline MachineOpCode
ChooseConvertFPToIntInstr(const TargetMachine& target,
const Type* destType, const Type* opType) {
assert((opType == Type::FloatTy || opType == Type::DoubleTy)
/// MAXUNSIGNED (i.e., 2^31 <= V <= 2^32-1) would be converted incorrectly.
/// Therefore, for converting an FP value to uint32_t, we first need to convert
/// to uint64_t and then to uint32_t.
-///
+///
static void
CreateCodeToConvertFloatToInt(const TargetMachine& target,
Value* opVal, Instruction* destI,
/*numLowBits*/ 32, mvec, mcfi);
}
-static inline MachineOpCode
+static inline MachineOpCode
ChooseAddInstruction(const InstructionNode* instrNode) {
return ChooseAddInstructionByType(instrNode->getInstruction()->getType());
}
-static inline MachineInstr*
+static inline MachineInstr*
CreateMovFloatInstruction(const InstructionNode* instrNode,
const Type* resultType) {
return BuildMI((resultType == Type::FloatTy) ? V9::FMOVS : V9::FMOVD, 2)
.addRegDef(instrNode->getValue());
}
-static inline MachineInstr*
+static inline MachineInstr*
CreateAddConstInstruction(const InstructionNode* instrNode) {
MachineInstr* minstr = NULL;
-
+
Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
assert(isa<Constant>(constOp));
-
+
// Cases worth optimizing are:
// (1) Add with 0 for float or double: use an FMOV of appropriate type,
// instead of an FADD (1 vs 3 cycles). There is no integer MOV.
minstr = CreateMovFloatInstruction(instrNode,
instrNode->getInstruction()->getType());
}
-
+
return minstr;
}
static inline MachineOpCode ChooseSubInstructionByType(const Type* resultType) {
MachineOpCode opCode = V9::INVALID_OPCODE;
-
+
if (resultType->isInteger() || isa<PointerType>(resultType)) {
opCode = V9::SUBr;
} else {
switch(resultType->getTypeID()) {
case Type::FloatTyID: opCode = V9::FSUBS; break;
case Type::DoubleTyID: opCode = V9::FSUBD; break;
- default: assert(0 && "Invalid type for SUB instruction"); break;
+ default: assert(0 && "Invalid type for SUB instruction"); break;
}
}
return opCode;
}
-static inline MachineInstr*
+static inline MachineInstr*
CreateSubConstInstruction(const InstructionNode* instrNode) {
MachineInstr* minstr = NULL;
-
+
Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
assert(isa<Constant>(constOp));
-
+
// Cases worth optimizing are:
// (1) Sub with 0 for float or double: use an FMOV of appropriate type,
// instead of an FSUB (1 vs 3 cycles). There is no integer MOV.
minstr = CreateMovFloatInstruction(instrNode,
instrNode->getInstruction()->getType());
}
-
+
return minstr;
}
-static inline MachineOpCode
+static inline MachineOpCode
ChooseFcmpInstruction(const InstructionNode* instrNode) {
MachineOpCode opCode = V9::INVALID_OPCODE;
-
+
Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue();
switch(operand->getType()->getTypeID()) {
case Type::FloatTyID: opCode = V9::FCMPS; break;
case Type::DoubleTyID: opCode = V9::FCMPD; break;
- default: assert(0 && "Invalid type for FCMP instruction"); break;
+ default: assert(0 && "Invalid type for FCMP instruction"); break;
}
-
+
return opCode;
}
/// BothFloatToDouble - Assumes that leftArg and rightArg of instrNode are both
/// cast instructions. Returns true if both are floats cast to double.
-///
+///
static inline bool BothFloatToDouble(const InstructionNode* instrNode) {
InstrTreeNode* leftArg = instrNode->leftChild();
InstrTreeNode* rightArg = instrNode->rightChild();
static inline MachineOpCode ChooseMulInstructionByType(const Type* resultType) {
MachineOpCode opCode = V9::INVALID_OPCODE;
-
+
if (resultType->isInteger())
opCode = V9::MULXr;
else
switch(resultType->getTypeID()) {
case Type::FloatTyID: opCode = V9::FMULS; break;
case Type::DoubleTyID: opCode = V9::FMULD; break;
- default: assert(0 && "Invalid type for MUL instruction"); break;
+ default: assert(0 && "Invalid type for MUL instruction"); break;
}
-
+
return opCode;
}
/// significant bit of the operand after shifting (e.g., bit 32 of Int or bit 16
/// of Short), so we do not have to worry about results that are as large as a
/// normal integer register.
-///
+///
static inline void
CreateShiftInstructions(const TargetMachine& target, Function* F,
MachineOpCode shiftOpCode, Value* argVal1,
assert((optArgVal2 != NULL || optShiftNum <= 64) &&
"Large shift sizes unexpected, but can be handled below: "
"You need to check whether or not it fits in immed field below");
-
+
// If this is a logical left shift of a type smaller than the standard
// integer reg. size, we have to extend the sign-bit into upper bits
// of dest, so we need to put the result of the SLL into a temporary.
// put SLL result into a temporary
shiftDest = new TmpInstruction(mcfi, argVal1, optArgVal2, "sllTmp");
}
-
+
MachineInstr* M = (optArgVal2 != NULL)
? BuildMI(shiftOpCode, 3).addReg(argVal1).addReg(optArgVal2)
.addReg(shiftDest, MachineOperand::Def)
: BuildMI(shiftOpCode, 3).addReg(argVal1).addZImm(optShiftNum)
.addReg(shiftDest, MachineOperand::Def);
mvec.push_back(M);
-
+
if (shiftDest != destVal) {
// extend the sign-bit of the result into all upper bits of dest
assert(8*opSize <= 32 && "Unexpected type size > 4 and < IntRegSize?");
/// cannot exploit constant to create a cheaper instruction. This returns the
/// approximate cost of the instructions generated, which is used to pick the
/// cheapest when both operands are constant.
-///
+///
static unsigned
CreateMulConstInstruction(const TargetMachine &target, Function* F,
Value* lval, Value* rval, Instruction* destVal,
// Use max. multiply cost, viz., cost of MULX
unsigned cost = target.getInstrInfo()->minLatency(V9::MULXr);
unsigned firstNewInstr = mvec.size();
-
+
Value* constOp = rval;
if (! isa<Constant>(constOp))
return cost;
-
+
// Cases worth optimizing are:
// (1) Multiply by 0 or 1 for any type: replace with copy (ADD or FMOV)
// (2) Multiply by 2^x for integer types: replace with Shift
const Type* resultType = destVal->getType();
-
+
if (resultType->isInteger() || isa<PointerType>(resultType)) {
bool isValidConst;
int64_t C = (int64_t) ConvertConstantToIntType(target, constOp,
needNeg = true;
C = -C;
}
-
+
if (C == 0 || C == 1) {
cost = target.getInstrInfo()->minLatency(V9::ADDr);
unsigned Zero = target.getRegInfo()->getZeroRegNum();
CreateShiftInstructions(target, F, opCode, lval, NULL, pow,
destVal, mvec, mcfi);
}
-
+
if (mvec.size() > 0 && needNeg) {
// insert <reg = SUB 0, reg> after the instr to flip the sign
MachineInstr* M = CreateIntNegInstruction(target, destVal);
? (resultType == Type::FloatTy? V9::FNEGS : V9::FNEGD)
: (resultType == Type::FloatTy? V9::FMOVS : V9::FMOVD);
mvec.push_back(BuildMI(opCode,2).addReg(lval).addRegDef(destVal));
- }
+ }
}
}
-
+
if (firstNewInstr < mvec.size()) {
cost = 0;
for (unsigned i=firstNewInstr; i < mvec.size(); ++i)
cost += target.getInstrInfo()->minLatency(mvec[i]->getOpcode());
}
-
+
return cost;
}
CreateMulConstInstruction(target, F, lval, rval, destVal, mvec, mcfi);
else if (isa<Constant>(lval)) // lval is constant, but not rval
CreateMulConstInstruction(target, F, lval, rval, destVal, mvec, mcfi);
-
+
// else neither is constant
return;
}
/// CreateMulInstruction - Returns NULL if we cannot exploit constant
/// to create a cheaper instruction.
-///
+///
static inline void
CreateMulInstruction(const TargetMachine &target, Function* F,
Value* lval, Value* rval, Instruction* destVal,
// Use FSMULD if both operands are actually floats cast to doubles.
// Otherwise, use the default opcode for the appropriate type.
MachineOpCode mulOp = ((forceMulOp != -1)
- ? forceMulOp
+ ? forceMulOp
: ChooseMulInstructionByType(destVal->getType()));
mvec.push_back(BuildMI(mulOp, 3).addReg(lval).addReg(rval)
.addRegDef(destVal));
/// ChooseDivInstruction - Generate a divide instruction for Div or Rem.
/// For Rem, this assumes that the operand type will be signed if the result
/// type is signed. This is correct because they must have the same sign.
-///
-static inline MachineOpCode
+///
+static inline MachineOpCode
ChooseDivInstruction(TargetMachine &target, const InstructionNode* instrNode) {
MachineOpCode opCode = V9::INVALID_OPCODE;
-
+
const Type* resultType = instrNode->getInstruction()->getType();
-
+
if (resultType->isInteger())
opCode = resultType->isSigned()? V9::SDIVXr : V9::UDIVXr;
else
switch(resultType->getTypeID()) {
case Type::FloatTyID: opCode = V9::FDIVS; break;
case Type::DoubleTyID: opCode = V9::FDIVD; break;
- default: assert(0 && "Invalid type for DIV instruction"); break;
+ default: assert(0 && "Invalid type for DIV instruction"); break;
}
-
+
return opCode;
}
/// CreateDivConstInstruction - Return if we cannot exploit constant to create
/// a cheaper instruction.
-///
+///
static void CreateDivConstInstruction(TargetMachine &target,
const InstructionNode* instrNode,
std::vector<MachineInstr*>& mvec) {
Instruction* destVal = instrNode->getInstruction();
unsigned ZeroReg = target.getRegInfo()->getZeroRegNum();
-
+
// Cases worth optimizing are:
// (1) Divide by 1 for any type: replace with copy (ADD or FMOV)
// (2) Divide by 2^x for integer types: replace with SR[L or A]{X}
const Type* resultType = instrNode->getInstruction()->getType();
-
+
if (resultType->isInteger()) {
unsigned pow;
bool isValidConst;
needNeg = true;
C = -C;
}
-
+
if (C == 1) {
mvec.push_back(BuildMI(V9::ADDr, 3).addReg(LHS).addMReg(ZeroReg)
.addRegDef(destVal));
if (resultType->isSigned()) {
// For N / 2^k, if the operand N is negative,
// we need to add (2^k - 1) before right-shifting by k, i.e.,
- //
+ //
// (N / 2^k) = N >> k, if N >= 0;
// (N + 2^k - 1) >> k, if N < 0
- //
+ //
// If N is <= 32 bits, use:
// sra N, 31, t1 // t1 = ~0, if N < 0, 0 else
// srl t1, 32-k, t2 // t2 = 2^k - 1, if N < 0, 0 else
// add t2, N, t3 // t3 = N + 2^k -1, if N < 0, N else
// sra t3, k, result // result = N / 2^k
- //
+ //
// If N is 64 bits, use:
// srax N, k-1, t1 // t1 = sign bit in high k positions
// srlx t1, 64-k, t2 // t2 = 2^k - 1, if N < 0, 0 else
mvec.push_back(BuildMI(opCode, 3).addReg(shiftOperand).addZImm(pow)
.addRegDef(destVal));
}
-
+
if (needNeg && (C == 1 || isPowerOf2(C, pow))) {
// insert <reg = SUB 0, reg> after the instr to flip the sign
mvec.push_back(CreateIntNegInstruction(target, destVal));
if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp)) {
double dval = FPC->getValue();
if (fabs(dval) == 1) {
- unsigned opCode =
+ unsigned opCode =
(dval < 0) ? (resultType == Type::FloatTy? V9::FNEGS : V9::FNEGD)
: (resultType == Type::FloatTy? V9::FMOVS : V9::FMOVD);
-
+
mvec.push_back(BuildMI(opCode, 2).addReg(LHS).addRegDef(destVal));
- }
+ }
}
}
}
// Instruction 3: add %sp, frameSizeBelowDynamicArea -> result
getMvec.push_back(BuildMI(V9::ADDr,3).addMReg(SPReg).addReg(dynamicAreaOffset)
.addRegDef(result));
-}
+}
static void
CreateCodeForFixedSizeAlloca(const TargetMachine& target,
// spills, and temporaries to have large offsets.
// NOTE: We use LARGE = 8 * argSlotSize = 64 bytes.
// You've gotta love having only 13 bits for constant offset values :-|.
- //
+ //
unsigned paddedSize;
int offsetFromFP = mcInfo.getInfo<SparcV9FunctionInfo>()->computeOffsetforLocalVar(result,
paddedSize,
if (((int)paddedSize) > 8 * SparcV9FrameInfo::SizeOfEachArgOnStack ||
!target.getInstrInfo()->constantFitsInImmedField(V9::LDXi,offsetFromFP)) {
- CreateCodeForVariableSizeAlloca(target, result, tsize,
+ CreateCodeForVariableSizeAlloca(target, result, tsize,
ConstantSInt::get(Type::IntTy,numElements),
getMvec);
return;
}
-
+
// else offset fits in immediate field so go ahead and allocate it.
offsetFromFP = mcInfo.getInfo<SparcV9FunctionInfo>()->allocateLocalVar(result, tsize *numElements);
-
+
// Create a temporary Value to hold the constant offset.
// This is needed because it may not fit in the immediate field.
ConstantSInt* offsetVal = ConstantSInt::get(Type::IntTy, offsetFromFP);
-
+
// Instruction 1: add %fp, offsetFromFP -> result
unsigned FPReg = target.getRegInfo()->getFramePointer();
getMvec.push_back(BuildMI(V9::ADDr, 3).addMReg(FPReg).addReg(offsetVal)
MachineOperand::MO_VirtualRegister;
// Check if there is an index vector and if so, compute the
- // right offset for structures and for arrays
+ // right offset for structures and for arrays
if (!idxVec.empty()) {
const PointerType* ptrType = cast<PointerType>(ptrVal->getType());
-
+
// If all indices are constant, compute the combined offset directly.
if (allConstantIndices) {
// Compute the offset value using the index vector. Create a
// offset. (An extra leading zero offset, if any, can be ignored.)
// Generate code sequence to compute address from index.
bool firstIdxIsZero = IsZero(idxVec[0]);
- assert(idxVec.size() == 1U + firstIdxIsZero
+ assert(idxVec.size() == 1U + firstIdxIsZero
&& "Array refs must be lowered before Instruction Selection");
Value* idxVal = idxVec[firstIdxIsZero];
assert(mulVec.size() > 0 && "No multiply code created?");
mvec.insert(mvec.end(), mulVec.begin(), mulVec.end());
-
+
valueForRegOffset = addr;
}
} else {
/// Check both explicit and implicit operands! Also make sure to skip over a
/// parent who: (1) is a list node in the Burg tree, or (2) itself had its
/// results forwarded to its parent.
-///
+///
static void ForwardOperand (InstructionNode *treeNode, InstrTreeNode *parent,
int operandNum) {
assert(treeNode && parent && "Invalid invocation of ForwardOperand");
-
+
Instruction* unusedOp = treeNode->getInstruction();
Value* fwdOp = unusedOp->getOperand(operandNum);
assert(parent && "ERROR: Non-instruction node has no parent in tree.");
}
InstructionNode* parentInstrNode = (InstructionNode*) parent;
-
+
Instruction* userInstr = parentInstrNode->getInstruction();
MachineCodeForInstruction &mvec = MachineCodeForInstruction::get(userInstr);
fwdOp);
}
}
-
+
for (unsigned i=0,numOps=minstr->getNumImplicitRefs(); i<numOps; ++i)
if (minstr->getImplicitRef(i) == unusedOp)
minstr->setImplicitRef(i, fwdOp);
/// AllUsesAreBranches - Returns true if all the uses of I are
/// Branch instructions, false otherwise.
-///
+///
inline bool AllUsesAreBranches(const Instruction* I) {
for (Value::use_const_iterator UI=I->use_begin(), UE=I->use_end();
UI != UE; ++UI)
/// CodeGenIntrinsic - Generate code for any intrinsic that needs a special
/// code sequence instead of a regular call. If not that kind of intrinsic, do
/// nothing. Returns true if code was generated, otherwise false.
-///
+///
static bool CodeGenIntrinsic(Intrinsic::ID iid, CallInst &callInstr,
TargetMachine &target,
std::vector<MachineInstr*>& mvec) {
Function* func = cast<Function>(callInstr.getParent()->getParent());
int numFixedArgs = func->getFunctionType()->getNumParams();
int fpReg = SparcV9::i6;
- int firstVarArgOff = numFixedArgs * 8 +
+ int firstVarArgOff = numFixedArgs * 8 +
SparcV9FrameInfo::FirstIncomingArgOffsetFromFP;
mvec.push_back(BuildMI(V9::ADDi, 3).addMReg(fpReg).addSImm(firstVarArgOff).
addRegDef(&callInstr));
}
/// ThisIsAChainRule - returns true if the given BURG rule is a chain rule.
-///
+///
extern bool ThisIsAChainRule(int eruleno) {
switch(eruleno) {
case 111: // stmt: reg
/// GetInstructionsByRule - Choose machine instructions for the
/// SPARC V9 according to the patterns chosen by the BURG-generated parser.
/// This is where most of the work in the V9 instruction selector gets done.
-///
+///
void GetInstructionsByRule(InstructionNode* subtreeRoot, int ruleForNode,
short* nts, TargetMachine &target,
std::vector<MachineInstr*>& mvec) {
unsigned L;
bool foldCase = false;
- mvec.clear();
-
+ mvec.clear();
+
// If the code for this instruction was folded into the parent (user),
// then do nothing!
if (subtreeRoot->isFoldedIntoParent())
return;
-
+
// Let's check for chain rules outside the switch so that we don't have
// to duplicate the list of chain rule production numbers here again
if (ThisIsAChainRule(ruleForNode)) {
// used by the machine instruction but not represented in LLVM.
Instruction* returnAddrTmp = new TmpInstruction(mcfi, returnInstr);
- MachineInstr* retMI =
+ MachineInstr* retMI =
BuildMI(V9::JMPLRETi, 3).addReg(returnAddrTmp).addSImm(8)
.addMReg(target.getRegInfo()->getZeroRegNum(), MachineOperand::Def);
-
+
// If there is a value to return, we need to:
// (a) Sign-extend the value if it is smaller than 8 bytes (reg size)
// (b) Insert a copy to copy the return value to the appropriate reg.
// -- For non-FP values, create an add-with-0 instruction
// First, create a virtual register to represent the register and
// mark this vreg as being an implicit operand of the ret MI.
- TmpInstruction* retVReg =
+ TmpInstruction* retVReg =
new TmpInstruction(mcfi, retValToUse, NULL, "argReg");
-
+
retMI->addImplicitRef(retVReg);
-
+
if (retType->isFloatingPoint())
M = (BuildMI(retType==Type::FloatTy? V9::FMOVS : V9::FMOVD, 2)
.addReg(retValToUse).addReg(retVReg, MachineOperand::Def));
mvec.push_back(M);
}
-
+
// Now insert the RET instruction and a NOP for the delay slot
mvec.push_back(retMI);
mvec.push_back(BuildMI(V9::NOP, 0));
-
+
break;
- }
-
+ }
+
case 3: // stmt: Store(reg,reg)
case 4: // stmt: Store(reg,ptrreg)
SetOperandsForMemInstr(ChooseStoreInstruction(
{
BranchInst *BI = cast<BranchInst>(subtreeRoot->getInstruction());
mvec.push_back(BuildMI(V9::BA, 1).addPCDisp(BI->getSuccessor(0)));
-
+
// delay slot
mvec.push_back(BuildMI(V9::NOP, 0));
break;
// If the constant is ZERO, we can use the branch-on-integer-register
// instructions and avoid the SUBcc instruction entirely.
// Otherwise this is just the same as case 5, so just fall through.
- //
+ //
InstrTreeNode* constNode = subtreeRoot->leftChild()->rightChild();
assert(constNode &&
constNode->getNodeType() ==InstrTreeNode::NTConstNode);
Constant *constVal = cast<Constant>(constNode->getValue());
bool isValidConst;
-
+
if ((constVal->getType()->isInteger()
|| isa<PointerType>(constVal->getType()))
&& ConvertConstantToIntType(target,
subtreeRoot->leftChild();
assert(setCCNode->getOpLabel() == SetCCOp);
setCCNode->markFoldedIntoParent();
-
+
BranchInst* brInst=cast<BranchInst>(subtreeRoot->getInstruction());
-
+
M = BuildMI(ChooseBprInstruction(subtreeRoot), 2)
.addReg(setCCNode->leftChild()->getValue())
.addPCDisp(brInst->getSuccessor(0));
mvec.push_back(M);
-
+
// delay slot
mvec.push_back(BuildMI(V9::NOP, 0));
// false branch
mvec.push_back(BuildMI(V9::BA, 1)
.addPCDisp(brInst->getSuccessor(1)));
-
+
// delay slot
mvec.push_back(BuildMI(V9::NOP, 0));
break;
// The branch to use depends on whether it is FP, signed, or unsigned.
// If it is an integer CC, we also need to find the unique
// TmpInstruction representing that CC.
- //
+ //
BranchInst* brInst = cast<BranchInst>(subtreeRoot->getInstruction());
const Type* setCCType;
unsigned Opcode = ChooseBccInstruction(subtreeRoot, setCCType);
mvec.push_back(BuildMI(V9::NOP, 0));
break;
}
-
+
case 208: // stmt: BrCond(boolconst)
{
// boolconst => boolean is a constant; use BA to first or second label
- Constant* constVal =
+ Constant* constVal =
cast<Constant>(subtreeRoot->leftChild()->getValue());
unsigned dest = cast<ConstantBool>(constVal)->getValue()? 0 : 1;
-
+
M = BuildMI(V9::BA, 1).addPCDisp(
cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(dest));
mvec.push_back(M);
-
+
// delay slot
mvec.push_back(BuildMI(V9::NOP, 0));
break;
}
-
+
case 8: // stmt: BrCond(boolreg)
{ // boolreg => boolean is recorded in an integer register.
// Use branch-on-integer-register instruction.
- //
+ //
BranchInst *BI = cast<BranchInst>(subtreeRoot->getInstruction());
M = BuildMI(V9::BRNZ, 2).addReg(subtreeRoot->leftChild()->getValue())
.addPCDisp(BI->getSuccessor(0));
// false branch
mvec.push_back(BuildMI(V9::BA, 1).addPCDisp(BI->getSuccessor(1)));
-
+
// delay slot
mvec.push_back(BuildMI(V9::NOP, 0));
break;
- }
-
+ }
+
case 9: // stmt: Switch(reg)
assert(0 && "*** SWITCH instruction is not implemented yet.");
break;
MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(castI);
TmpInstruction* tempReg =
new TmpInstruction(mcfi, opVal);
-
+
assert(opVal->getType()->isIntegral() ||
break;
}
-
+
case 23: // reg: ToUByteTy(reg)
case 24: // reg: ToSByteTy(reg)
case 25: // reg: ToUShortTy(reg)
{
//======================================================================
// Rules for integer conversions:
- //
+ //
//--------
// From ISO 1998 C++ Standard, Sec. 4.7:
//
// unsigned type). [Note: In a two s complement representation,
// this conversion is conceptual and there is no change in the
// bit pattern (if there is no truncation). ]
- //
+ //
// 3. If the destination type is signed, the value is unchanged if
// it can be represented in the destination type (and bitfield width);
// otherwise, the value is implementation-defined.
//--------
- //
+ //
// Since we assume 2s complement representations, this implies:
- //
+ //
// -- If operand is smaller than destination, zero-extend or sign-extend
// according to the signedness of the *operand*: source decides:
// (1) If operand is signed, sign-extend it.
// If dest is unsigned, zero-ext the result!
// (2) If operand is unsigned, our current invariant is that
// it's high bits are correct, so zero-extension is not needed.
- //
+ //
// -- If operand is same size as or larger than destination,
// zero-extend or sign-extend according to the signedness of
// the *destination*: destination decides:
const Type* destType = destI->getType();
unsigned opSize = target.getTargetData().getTypeSize(opType);
unsigned destSize = target.getTargetData().getTypeSize(destType);
-
+
bool isIntegral = opType->isIntegral() || isa<PointerType>(opType);
if (opType == Type::BoolTy ||
break;
}
-
+
case 31: // reg: ToFloatTy(reg):
case 32: // reg: ToDoubleTy(reg):
case 232: // reg: ToDoubleTy(Constant):
-
- // If this instruction has a parent (a user) in the tree
+
+ // If this instruction has a parent (a user) in the tree
// and the user is translated as an FsMULd instruction,
// then the cast is unnecessary. So check that first.
// In the future, we'll want to do the same for the FdMULq instruction,
// so do the check here instead of only for ToFloatTy(reg).
- //
+ //
if (subtreeRoot->parent() != NULL) {
const MachineCodeForInstruction& mcfi =
MachineCodeForInstruction::get(
// The type of this temporary will determine the FP
// register used: single-prec for a 32-bit int or smaller,
// double-prec for a 64-bit int.
- //
+ //
uint64_t srcSize =
target.getTargetData().getTypeSize(leftVal->getType());
Type* tmpTypeToUse =
(srcSize <= 4)? Type::FloatTy : Type::DoubleTy;
- MachineCodeForInstruction &destMCFI =
+ MachineCodeForInstruction &destMCFI =
MachineCodeForInstruction::get(dest);
srcForCast = new TmpInstruction(destMCFI, tmpTypeToUse, dest);
break;
}
// ELSE FALL THROUGH
-
+
case 33: // reg: Add(reg, reg)
maskUnsignedResult = true;
Add3OperandInstr(ChooseAddInstruction(subtreeRoot), subtreeRoot, mvec);
break;
}
// ELSE FALL THROUGH
-
+
case 34: // reg: Sub(reg, reg)
maskUnsignedResult = true;
Add3OperandInstr(ChooseSubInstructionByType(
case 135: // reg: Mul(todouble, todouble)
checkCast = true;
- // FALL THROUGH
+ // FALL THROUGH
case 35: // reg: Mul(reg, reg)
{
}
case 335: // reg: Mul(todouble, todoubleConst)
checkCast = true;
- // FALL THROUGH
+ // FALL THROUGH
case 235: // reg: Mul(reg, Constant)
{
if (mvec.size() > L)
break;
// ELSE FALL THROUGH
-
+
case 36: // reg: Div(reg, reg)
{
maskUnsignedResult = true;
Value* divOp2 = subtreeRoot->rightChild()->getValue();
MachineCodeForInstruction& mcfi = MachineCodeForInstruction::get(remI);
-
+
// If second operand of divide is smaller than 64 bits, we have
// to make sure the unused top bits are correct because they affect
// the result. These bits are already correct for unsigned values.
// They may be incorrect for signed values, so sign extend to fill in.
- //
+ //
Value* divOpToUse = divOp2;
if (divOp2->getType()->isSigned()) {
unsigned opSize=target.getTargetData().getTypeSize(divOp2->getType());
// Now compute: result = rem V1, V2 as:
// result = V1 - (V1 / signExtend(V2)) * signExtend(V2)
- //
+ //
TmpInstruction* quot = new TmpInstruction(mcfi, divOp1, divOpToUse);
TmpInstruction* prod = new TmpInstruction(mcfi, quot, divOpToUse);
mvec.push_back(BuildMI(ChooseDivInstruction(target, subtreeRoot), 3)
.addReg(divOp1).addReg(divOpToUse).addRegDef(quot));
-
+
mvec.push_back(BuildMI(ChooseMulInstructionByType(remI->getType()), 3)
.addReg(quot).addReg(divOpToUse).addRegDef(prod));
-
+
mvec.push_back(BuildMI(ChooseSubInstructionByType(remI->getType()), 3)
.addReg(divOp1).addReg(prod).addRegDef(remI));
-
+
break;
}
-
+
case 38: // bool: And(bool, bool)
case 138: // bool: And(bool, not)
case 238: // bool: And(bool, boolconst)
case 41: // setCCconst: SetCC(reg, Constant)
{ // Comparison is with a constant:
- //
+ //
// If the bool result must be computed into a register (see below),
// and the constant is int ZERO, we can use the MOVR[op] instructions
// and avoid the SUBcc instruction entirely.
// Otherwise this is just the same as case 42, so just fall through.
- //
+ //
// The result of the SetCC must be computed and stored in a register if
// it is used outside the current basic block (so it must be computed
// as a boolreg) or it is used by anything other than a branch.
// We will use a conditional move to do this.
- //
+ //
Instruction* setCCInstr = subtreeRoot->getInstruction();
bool computeBoolVal = (subtreeRoot->parent() == NULL ||
! AllUsesAreBranches(setCCInstr));
constNode->getNodeType() ==InstrTreeNode::NTConstNode);
Constant *constVal = cast<Constant>(constNode->getValue());
bool isValidConst;
-
+
if ((constVal->getType()->isInteger()
|| isa<PointerType>(constVal->getType()))
&& ConvertConstantToIntType(target,
// Unconditionally set register to 0
mvec.push_back(BuildMI(V9::SETHI, 2).addZImm(0)
.addRegDef(setCCInstr));
-
+
// Now conditionally move 1 into the register.
// Mark the register as a use (as well as a def) because the old
// value will be retained if the condition is false.
.addReg(subtreeRoot->leftChild()->getValue())
.addZImm(1)
.addReg(setCCInstr, MachineOperand::UseAndDef));
-
+
break;
}
}
{
// This generates a SUBCC instruction, putting the difference in a
// result reg. if needed, and/or setting a condition code if needed.
- //
+ //
Instruction* setCCInstr = subtreeRoot->getInstruction();
Value* leftVal = subtreeRoot->leftChild()->getValue();
Value* rightVal = subtreeRoot->rightChild()->getValue();
const Type* opType = leftVal->getType();
bool isFPCompare = opType->isFloatingPoint();
-
+
// If the boolean result of the SetCC is used outside the current basic
// block (so it must be computed as a boolreg) or is used by anything
// other than a branch, the boolean must be computed and stored
// in a result register. We will use a conditional move to do this.
- //
+ //
bool computeBoolVal = (subtreeRoot->parent() == NULL ||
! AllUsesAreBranches(setCCInstr));
-
+
// A TmpInstruction is created to represent the CC "result".
// Unlike other instances of TmpInstruction, this one is used
// by machine code of multiple LLVM instructions, viz.,
// condition code. Think of this as casting the bool result to
// a FP condition code register.
// Later, we mark the 4th operand as being a CC register, and as a def.
- //
+ //
TmpInstruction* tmpForCC = GetTmpForCC(setCCInstr,
setCCInstr->getParent()->getParent(),
leftVal->getType(),
// If the operands are signed values smaller than 4 bytes, then they
// must be sign-extended in order to do a valid 32-bit comparison
// and get the right result in the 32-bit CC register (%icc).
- //
+ //
Value* leftOpToUse = leftVal;
Value* rightOpToUse = rightVal;
if (opType->isIntegral() && opType->isSigned()) {
unsigned opSize = target.getTargetData().getTypeSize(opType);
if (opSize < 4) {
MachineCodeForInstruction& mcfi =
- MachineCodeForInstruction::get(setCCInstr);
+ MachineCodeForInstruction::get(setCCInstr);
// create temporary virtual regs. to hold the sign-extensions
leftOpToUse = new TmpInstruction(mcfi, leftVal);
rightOpToUse = new TmpInstruction(mcfi, rightVal);
-
+
// sign-extend each operand and put the result in the temporary reg.
CreateSignExtensionInstructions
(target, setCCInstr->getParent()->getParent(),
.addReg(leftOpToUse)
.addReg(rightOpToUse));
}
-
+
if (computeBoolVal) {
MachineOpCode movOpCode = (isFPCompare
? ChooseMovFpcciInstruction(subtreeRoot)
// Unconditionally set register to 0
M = BuildMI(V9::SETHI, 2).addZImm(0).addRegDef(setCCInstr);
mvec.push_back(M);
-
+
// Now conditionally move 1 into the register.
// Mark the register as a use (as well as a def) because the old
// value will be retained if the condition is false.
mvec.push_back(M);
}
break;
- }
-
+ }
+
case 51: // reg: Load(reg)
case 52: // reg: Load(ptrreg)
SetOperandsForMemInstr(ChooseLoadInstruction(
AllocationInst* instr =
cast<AllocationInst>(subtreeRoot->getInstruction());
const Type* eltType = instr->getAllocatedType();
-
+
// If #elements is constant, use simpler code for fixed-size allocas
int tsize = (int) target.getTargetData().getTypeSize(eltType);
Value* numElementsVal = NULL;
bool isArray = instr->isArrayAllocation();
-
+
if (!isArray || isa<Constant>(numElementsVal = instr->getArraySize())) {
// total size is constant: generate code for fixed-size alloca
- unsigned numElements = isArray?
+ unsigned numElements = isArray?
cast<ConstantUInt>(numElementsVal)->getValue() : 1;
CreateCodeForFixedSizeAlloca(target, instr, tsize,
numElements, mvec);
// register (for indirect calls), the operands of the Call,
// and the return value (if any) as implicit operands
// of the machine instruction.
- //
+ //
// If this is a varargs function, floating point arguments
// have to passed in integer registers so insert
// copy-float-to-int instructions for each float operand.
- //
+ //
CallInst *callInstr = cast<CallInst>(subtreeRoot->getInstruction());
Value *callee = callInstr->getCalledValue();
Function* calledFunc = dyn_cast<Function>(callee);
// Check if this is an intrinsic function that needs a special code
// sequence (e.g., va_start). Indirect calls cannot be special.
- //
+ //
bool specialIntrinsic = false;
Intrinsic::ID iid;
if (calledFunc && (iid=(Intrinsic::ID)calledFunc->getIntrinsicID()))
// If not, generate the normal call sequence for the function.
// This can also handle any intrinsics that are just function calls.
- //
+ //
if (! specialIntrinsic) {
Function* currentFunc = callInstr->getParent()->getParent();
MachineFunction& MF = MachineFunction::get(currentFunc);
MachineCodeForInstruction& mcfi =
- MachineCodeForInstruction::get(callInstr);
+ MachineCodeForInstruction::get(callInstr);
const SparcV9RegInfo& regInfo =
(SparcV9RegInfo&) *target.getRegInfo();
const TargetFrameInfo& frameInfo = *target.getFrameInfo();
// the PC-relative address fits in the CALL address field (22 bits).
// Use JMPL for indirect calls.
// This will be added to mvec later, after operand copies.
- //
+ //
MachineInstr* callMI;
if (calledFunc) // direct function call
callMI = BuildMI(V9::CALL, 1).addPCDisp(callee);
->getElementType());
bool isVarArgs = funcType->isVarArg();
bool noPrototype = isVarArgs && funcType->getNumParams() == 0;
-
+
// Use a descriptor to pass information about call arguments
// to the register allocator. This descriptor will be "owned"
// and freed automatically when the MachineCodeForInstruction
// Insert sign-extension instructions for small signed values,
// if this is an unknown function (i.e., called via a funcptr)
// or an external one (i.e., which may not be compiled by llc).
- //
+ //
if (calledFunc == NULL || calledFunc->isExternal()) {
for (unsigned i=1, N=callInstr->getNumOperands(); i < N; ++i) {
Value* argVal = callInstr->getOperand(i);
// Insert copy instructions to get all the arguments into
// all the places that they need to be.
- //
+ //
for (unsigned i=1, N=callInstr->getNumOperands(); i < N; ++i) {
int argNo = i-1;
CallArgInfo& argInfo = argDesc->getArgInfo(argNo);
// may go in a register or on the stack. The copy instruction
// to the outgoing reg/stack is created by the normal argument
// handling code since this is the "normal" passing mode.
- //
+ //
regNumForArg = regInfo.regNumForFPArg(regType,
false, false, argNo,
regClassIDOfArgReg);
else
argInfo.setUseFPArgReg();
}
-
+
// If this arg. is in the first $K$ regs, add special copy-
// float-to-int instructions to pass the value as an int.
// To check if it is in the first $K$, get the register
// generated here because they are extra cases and not needed
// for the normal argument handling (some code reuse is
// possible though -- later).
- //
+ //
int copyRegNum = regInfo.regNumForIntArg(false, false, argNo,
regClassIDOfArgReg);
if (copyRegNum != regInfo.getInvalidRegNum()) {
argVal, NULL,
"argRegCopy");
callMI->addImplicitRef(argVReg);
-
+
// Get a temp stack location to use to copy
// float-to-int via the stack.
- //
+ //
// FIXME: For now, we allocate permanent space because
// the stack frame manager does not allow locals to be
// allocated (e.g., for alloca) after a temp is
// allocated!
- //
+ //
// int tmpOffset = MF.getInfo<SparcV9FunctionInfo>()->pushTempValue(argSize);
int tmpOffset = MF.getInfo<SparcV9FunctionInfo>()->allocateLocalVar(argVReg);
-
+
// Generate the store from FP reg to stack
unsigned StoreOpcode = ChooseStoreInstruction(argType);
M = BuildMI(convertOpcodeFromRegToImm(StoreOpcode), 3)
.addReg(argVal).addMReg(regInfo.getFramePointer())
.addSImm(tmpOffset);
mvec.push_back(M);
-
+
// Generate the load from stack to int arg reg
unsigned LoadOpcode = ChooseLoadInstruction(loadTy);
M = BuildMI(convertOpcodeFromRegToImm(LoadOpcode), 3)
regNumForArg =regInfo.getUnifiedRegNum(regClassIDOfArgReg,
regNumForArg);
}
- }
+ }
- //
+ //
// Now insert copy instructions to stack slot or arg. register
- //
+ //
if (argInfo.usesStackSlot()) {
// Get the stack offset for this argument slot.
// FP args on stack are right justified so adjust offset!
// Create a virtual register to represent the arg reg. Mark
// this vreg as being an implicit operand of the call MI.
- TmpInstruction* argVReg =
+ TmpInstruction* argVReg =
new TmpInstruction(mcfi, argVal, NULL, "argReg");
callMI->addImplicitRef(argVReg);
-
+
// Generate the reg-to-reg copy into the outgoing arg reg.
// -- For FP values, create a FMOVS or FMOVD instruction
// -- For non-FP values, create an add-with-0 instruction
M = (BuildMI(ChooseAddInstructionByType(argType), 3)
.addReg(argVal).addSImm((int64_t) 0)
.addReg(argVReg, MachineOperand::Def));
-
+
// Mark the operand with the register it should be assigned
M->SetRegForOperand(M->getNumOperands()-1, regNumForArg);
callMI->SetRegForImplicitRef(callMI->getNumImplicitRefs()-1,
// Add the return value as an implicit ref. The call operands
// were added above. Also, add code to copy out the return value.
// This is always register-to-register for int or FP return values.
- //
- if (callInstr->getType() != Type::VoidTy) {
+ //
+ if (callInstr->getType() != Type::VoidTy) {
// Get the return value reg.
const Type* retType = callInstr->getType();
int regNum = (retType->isFloatingPoint()
- ? (unsigned) SparcV9FloatRegClass::f0
+ ? (unsigned) SparcV9FloatRegClass::f0
: (unsigned) SparcV9IntRegClass::o0);
unsigned regClassID = regInfo.getRegClassIDOfType(retType);
regNum = regInfo.getUnifiedRegNum(regClassID, regNum);
// Create a virtual register to represent it and mark
// this vreg as being an implicit operand of the call MI
- TmpInstruction* retVReg =
+ TmpInstruction* retVReg =
new TmpInstruction(mcfi, callInstr, NULL, "argReg");
callMI->addImplicitRef(retVReg, /*isDef*/ true);
break;
}
-
+
case 62: // reg: Shl(reg, reg)
{
Value* argVal1 = subtreeRoot->leftChild()->getValue();
Value* argVal2 = subtreeRoot->rightChild()->getValue();
Instruction* shlInstr = subtreeRoot->getInstruction();
-
+
const Type* opType = argVal1->getType();
assert((opType->isInteger() || isa<PointerType>(opType)) &&
"Shl unsupported for other types");
unsigned opSize = target.getTargetData().getTypeSize(opType);
-
+
CreateShiftInstructions(target, shlInstr->getParent()->getParent(),
(opSize > 4)? V9::SLLXr6:V9::SLLr5,
argVal1, argVal2, 0, shlInstr, mvec,
MachineCodeForInstruction::get(shlInstr));
break;
}
-
+
case 63: // reg: Shr(reg, reg)
- {
+ {
const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
assert((opType->isInteger() || isa<PointerType>(opType)) &&
"Shr unsupported for other types");
subtreeRoot, mvec);
break;
}
-
+
case 64: // reg: Phi(reg,reg)
break; // don't forward the value
addSImm(0).addRegDef(vaArgI));
break;
}
-
+
case 71: // reg: VReg
case 72: // reg: Constant
break; // don't forward the value
unsigned destSize=target.getTargetData().getTypeSize(dest->getType());
if (destSize <= 4) {
// Mask high 64 - N bits, where N = 4*destSize.
-
+
// Use a TmpInstruction to represent the
// intermediate result before masking. Since those instructions
// have already been generated, go back and substitute tmpI
// for dest in the result position of each one of them.
- //
+ //
MachineCodeForInstruction& mcfi = MachineCodeForInstruction::get(dest);
TmpInstruction *tmpI = new TmpInstruction(mcfi, dest->getType(),
dest, NULL, "maskHi");
// introduce a use of `tmpI' with no preceding def. Therefore,
// substitute a use or def-and-use operand only if a previous def
// operand has already been substituted (i.e., numSubst > 0).
- //
+ //
numSubst += mvec[i]->substituteValue(dest, tmpI,
/*defsOnly*/ numSubst == 0,
/*notDefsAndUses*/ numSubst > 0,
<< F.getName() << "\n\n";
instrForest.dump();
}
-
+
// Invoke BURG instruction selection for each tree
for (InstrForest::const_root_iterator RI = instrForest.roots_begin();
RI != instrForest.roots_end(); ++RI) {
InstructionNode* basicNode = *RI;
- assert(basicNode->parent() == NULL && "A `root' node has a parent?");
-
+ assert(basicNode->parent() == NULL && "A `root' node has a parent?");
+
// Invoke BURM to label each tree node with a state
burm_label(basicNode);
if (SelectDebugLevel >= Select_DebugBurgTrees) {
std::cerr << "\nCover cost == " << treecost(basicNode, 1, 0) <<"\n\n";
printMatches(basicNode);
}
-
+
// Then recursively walk the tree to select instructions
SelectInstructionsForTree(basicNode, /*goalnt*/1);
}
-
+
// Create the MachineBasicBlocks and add all of the MachineInstrs
// defined in the MachineCodeForInstruction objects to the MachineBasicBlocks.
MachineFunction &MF = MachineFunction::get(&F);
// Insert phi elimination code
InsertCodeForPhis(F);
-
+
if (SelectDebugLevel >= Select_PrintMachineCode) {
std::cerr << "\n*** Machine instructions after INSTRUCTION SELECTION\n";
MachineFunction::get(&F).dump();
}
-
+
return true;
}
MachineCodeForInstruction &MCforPN = MachineCodeForInstruction::get (PN);
for (unsigned i = 0; i < PN->getNumIncomingValues(); ++i) {
std::vector<MachineInstr*> mvec, CpVec;
- Target.getRegInfo()->cpValue2Value(PN->getIncomingValue(i),
+ Target.getRegInfo()->cpValue2Value(PN->getIncomingValue(i),
PhiCpRes, mvec);
for (std::vector<MachineInstr*>::iterator MI=mvec.begin();
MI != mvec.end(); ++MI) {
CpVec2.push_back(*MI);
CpVec.insert(CpVec.end(), CpVec2.begin(), CpVec2.end());
}
- // Insert the copy instructions into the predecessor BB.
+ // Insert the copy instructions into the predecessor BB.
InsertPhiElimInstructions(PN->getIncomingBlock(i), CpVec);
MCforPN.insert (MCforPN.end (), CpVec.begin (), CpVec.end ());
}
///
void V9ISel::InsertPhiElimInstructions(BasicBlock *BB,
const std::vector<MachineInstr*>& CpVec)
-{
+{
Instruction *TermInst = (Instruction*)BB->getTerminator();
MachineCodeForInstruction &MC4Term = MachineCodeForInstruction::get(TermInst);
MachineInstr *FirstMIOfTerm = MC4Term.front();
assert(MBB && "Machine BB for predecessor's terminator not found");
MachineBasicBlock::iterator MCIt = FirstMIOfTerm;
assert(MCIt != MBB->end() && "Start inst of terminator not found");
-
+
// Insert the copy instructions just before the first machine instruction
// generated for the terminator.
MBB->insert(MCIt, CpVec.begin(), CpVec.end());
/// SelectInstructionsForTree - Recursively walk the tree to select
/// instructions. Do this top-down so that child instructions can exploit
/// decisions made at the child instructions.
-///
+///
/// E.g., if br(setle(reg,const)) decides the constant is 0 and uses
/// a branch-on-integer-register instruction, then the setle node
/// can use that information to avoid generating the SUBcc instruction.
void V9ISel::SelectInstructionsForTree(InstrTreeNode* treeRoot, int goalnt) {
// Get the rule that matches this node.
int ruleForNode = burm_rule(treeRoot->state, goalnt);
-
+
if (ruleForNode == 0) {
std::cerr << "Could not match instruction tree for instr selection\n";
abort();
}
-
+
// Get this rule's non-terminals and the corresponding child nodes (if any)
short *nts = burm_nts[ruleForNode];
-
+
// First, select instructions for the current node and rule.
// (If this is a list node, not an instruction, then skip this step).
// This function is specific to the target architecture.
InstructionNode* instrNode = (InstructionNode*)treeRoot;
assert(instrNode->getNodeType() == InstrTreeNode::NTInstructionNode);
GetInstructionsByRule(instrNode, ruleForNode, nts, Target, minstrVec);
- MachineCodeForInstruction &mvec =
+ MachineCodeForInstruction &mvec =
MachineCodeForInstruction::get(instrNode->getInstruction());
mvec.insert(mvec.end(), minstrVec.begin(), minstrVec.end());
}
-
+
// Then, recursively compile the child nodes, if any.
- //
+ //
if (nts[0]) {
// i.e., there is at least one kid
InstrTreeNode* kids[2];
int currentRule = ruleForNode;
burm_kids(treeRoot, currentRule, kids);
-
+
// First skip over any chain rules so that we don't visit
// the current node again.
while (ThisIsAChainRule(currentRule)) {
nts = burm_nts[currentRule];
burm_kids(treeRoot, currentRule, kids);
}
-
+
// Now we have the first non-chain rule so we have found
// the actual child nodes. Recursively compile them.
for (unsigned i = 0; nts[i]; i++) {
SelectInstructionsForTree(kids[i], nts[i]);
}
}
-
+
// Finally, do any post-processing on this node after its children
// have been translated.
if (treeRoot->opLabel != VRegListOp)
//===-- SparcV9BurgISel.h ---------------------------------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Global functions exposed by the BURG-based instruction selector
/// or a GlobalValue, viz., the constant address of a global variable or
/// function. The generated instructions are returned in `mvec'. Any temp.
/// registers (TmpInstruction) created are recorded in mcfi.
-///
+///
void CreateCodeToLoadConst (const TargetMachine &target, Function *F,
Value *val, Instruction *dest, std::vector<MachineInstr*> &mvec,
MachineCodeForInstruction &mcfi);
//===-- SparcV9CodeEmitter.cpp --------------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// SPARC-specific backend for emitting machine code to memory.
MCE.emitWord(Val);
}
-unsigned
+unsigned
SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
MachineInstr &MI) {
const SparcV9RegInfo &RI = *TM.getRegInfo();
16, 17, 18, 19, 20, 21, 22, 23,
// "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
24, 25, 26, 27, 28, 29, 30, 31,
- // "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
+ // "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
0, 1, 2, 3, 4, 5, 6, 7,
// "o6"
14
- };
-
+ };
+
return IntRegMap[fakeReg];
break;
}
// The bit layout becomes: b[4], b[3], b[2], b[1], b[5]
fakeReg |= (fakeReg >> 5) & 1;
fakeReg &= 0x1f;
- DEBUG(std::cerr << "FP double reg, returning: " << fakeReg << "\n");
+ DEBUG(std::cerr << "FP double reg, returning: " << fakeReg << "\n");
}
return fakeReg;
}
case SparcV9RegInfo::IntCCRegClassID: {
/* xcc, icc, ccr */
static const unsigned IntCCReg[] = { 6, 4, 2 };
-
+
assert(fakeReg < sizeof(IntCCReg)/sizeof(IntCCReg[0])
- && "CC register out of bounds for IntCCReg map");
+ && "CC register out of bounds for IntCCReg map");
DEBUG(std::cerr << "IntCC reg: " << IntCCReg[fakeReg] << "\n");
return IntCCReg[fakeReg];
}
// instructions and 0 in SparcV9SpecialRegClass.
static const unsigned SpecialReg[] = { 1 };
assert(fakeReg < sizeof(SpecialReg)/sizeof(SpecialReg[0])
- && "Special register out of bounds for SpecialReg map");
+ && "Special register out of bounds for SpecialReg map");
DEBUG(std::cerr << "Special reg: " << SpecialReg[fakeReg] << "\n");
return SpecialReg[fakeReg];
}
unsigned fakeReg = MO.getReg();
unsigned realRegByClass = getRealRegNum(fakeReg, MI);
DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] => "
- << realRegByClass << " (LLC: "
+ << realRegByClass << " (LLC: "
<< TM.getRegInfo()->getUnifiedRegName(fakeReg) << ")\n");
rv = realRegByClass;
} else if (MO.isImmediate()) {
rv = MO.getImmedValue();
DEBUG(std::cerr << "immed: " << rv << "\n");
} else if (MO.isMachineBasicBlock()) {
- // Duplicate code of the above case for VirtualRegister, BasicBlock...
+ // Duplicate code of the above case for VirtualRegister, BasicBlock...
// It should really hit this case, but SparcV9 backend uses VRegs instead
DEBUG(std::cerr << "Saving reference to MBB\n");
const BasicBlock *BB = MO.getMachineBasicBlock()->getBasicBlock();
bool SparcV9CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
MCE.startFunction(MF);
DEBUG(std::cerr << "Starting function " << MF.getFunction()->getName()
- << ", address: " << "0x" << std::hex
+ << ", address: " << "0x" << std::hex
<< (long)MCE.getCurrentPCValue() << "\n");
MCE.emitConstantPool(MF.getConstantPool());
// Ref is the location of the instruction, and hence the PC
int64_t branchTarget = (Location - (long)Ref) >> 2;
// Save the flags.
- bool loBits32=false, hiBits32=false, loBits64=false, hiBits64=false;
+ bool loBits32=false, hiBits32=false, loBits64=false, hiBits64=false;
if (op.isLoBits32()) { loBits32=true; }
if (op.isHiBits32()) { hiBits32=true; }
if (op.isLoBits64()) { loBits64=true; }
//===-- SparcV9CodeEmitter.h ------------------------------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// Target-specific portions of the machine code emitter for the SparcV9.
// This class interfaces with the JIT's Emitter in order to turn MachineInstrs
// into words of binary machine code. Its code is partially generated by
/// emitWord - writes out the given 32-bit value to memory at the current PC.
///
void emitWord(unsigned Val);
-
+
/// getBinaryCodeForInstr - This function, generated by the
/// CodeEmitterGenerator using TableGen, produces the binary encoding for
/// machine instructions.
///
unsigned getBinaryCodeForInstr(MachineInstr &MI);
-private:
- /// getMachineOpValue -
+private:
+ /// getMachineOpValue -
///
int64_t getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
- /// emitBasicBlock -
+ /// emitBasicBlock -
///
void emitBasicBlock(MachineBasicBlock &MBB);
- /// getValueBit -
+ /// getValueBit -
///
unsigned getValueBit(int64_t Val, unsigned bit);
- /// getGlobalAddress -
+ /// getGlobalAddress -
///
void* getGlobalAddress(GlobalValue *V, MachineInstr &MI,
bool isPCRelative);
- /// emitFarCall -
+ /// emitFarCall -
///
unsigned getRealRegNum(unsigned fakeReg, MachineInstr &MI);
//===-- SparcV9FrameInfo.cpp - Stack frame layout info for SparcV9 --------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// Interface to stack frame layout info for the UltraSPARC.
-//
+//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MachineFunction.h"
using namespace llvm;
int
-SparcV9FrameInfo::getRegSpillAreaOffset(MachineFunction& mcInfo, bool& pos) const
+SparcV9FrameInfo::getRegSpillAreaOffset(MachineFunction& mcInfo, bool& pos) const
{
// ensure no more auto vars are added
mcInfo.getInfo<SparcV9FunctionInfo>()->freezeAutomaticVarsArea();
-
+
pos = false; // static stack area grows downwards
unsigned autoVarsSize = mcInfo.getInfo<SparcV9FunctionInfo>()->getAutomaticVarsSize();
- return StaticAreaOffsetFromFP - autoVarsSize;
+ return StaticAreaOffsetFromFP - autoVarsSize;
}
int SparcV9FrameInfo::getTmpAreaOffset(MachineFunction& mcInfo, bool& pos) const {
SparcV9FunctionInfo *MFI = mcInfo.getInfo<SparcV9FunctionInfo>();
MFI->freezeAutomaticVarsArea(); // ensure no more auto vars are added
MFI->freezeSpillsArea(); // ensure no more spill slots are added
-
+
pos = false; // static stack area grows downwards
unsigned autoVarsSize = MFI->getAutomaticVarsSize();
unsigned spillAreaSize = MFI->getRegSpillsSize();
//===-- SparcV9FrameInfo.h - Define TargetFrameInfo for SparcV9 -*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Interface to stack frame layout info for the UltraSPARC.
public:
SparcV9FrameInfo(const TargetMachine &TM)
: TargetFrameInfo(StackGrowsDown, StackFrameSizeAlignment, 0), target(TM) {}
-
+
// This method adjusts a stack offset to meet alignment rules of target.
// The fixed OFFSET (0x7ff) must be subtracted and the result aligned.
virtual int adjustAlignment(int unalignedOffset, bool growUp,
// These methods compute offsets using the frame contents for a
// particular function. The frame contents are obtained from the
// MachineCodeInfoForMethod object for the given function.
- //
+ //
int getFirstAutomaticVarOffset(MachineFunction& mcInfo, bool& growUp) const {
growUp = false;
return StaticAreaOffsetFromFP;
int getTmpAreaOffset(MachineFunction& mcInfo, bool& growUp) const;
int getDynamicAreaOffset(MachineFunction& mcInfo, bool& growUp) const;
- virtual int getIncomingArgOffset(MachineFunction& mcInfo,
+ virtual int getIncomingArgOffset(MachineFunction& mcInfo,
unsigned argNum) const {
unsigned relativeOffset = argNum * SizeOfEachArgOnStack;
int firstArg = FirstIncomingArgOffsetFromFP;
unsigned argNum) const {
return FirstOutgoingArgOffsetFromSP + argNum * SizeOfEachArgOnStack;
}
-
+
/*----------------------------------------------------------------------
This diagram shows the stack frame layout used by llc on SparcV9 V9.
Note that only the location of automatic variables, spill area,
during a call to another function, so it is never needed when
the current function is active. This is why space can be allocated
dynamically by incrementing %sp any time within the function.
-
+
STACK FRAME LAYOUT:
...
//===- SparcV9InstrForest.h - SparcV9 BURG Instruction Selector Trees -----===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// A forest of BURG instruction trees (class InstrForest) which represents
/// Declarations of data and functions created by BURG
///
-namespace llvm {
+namespace llvm {
class InstrTreeNode;
};
extern short* burm_nts[];
protected:
InstrTreeNodeType treeNodeType;
Value* val;
-
+
public:
InstrTreeNode(InstrTreeNodeType nodeType, Value* _val)
: treeNodeType(nodeType), val(_val) {
inline OpLabel getOpLabel () const { return opLabel; }
inline InstrTreeNode *leftChild () const { return LeftChild; }
inline InstrTreeNode *parent () const { return Parent; }
-
+
// If right child is a list node, recursively get its *left* child
inline InstrTreeNode* rightChild() const {
- return (!RightChild ? 0 :
+ return (!RightChild ? 0 :
(RightChild->getOpLabel() == VRegListOp
? RightChild->LeftChild : RightChild));
}
//===-- SparcV9InstrInfo.h - Define TargetInstrInfo for SparcV9 -*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This class contains information about individual instructions.
// Also see the SparcV9MachineInstrDesc array, which can be found in
// SparcV9TargetMachine.cpp.
// Other information is computed on demand, and most such functions
-// default to member functions in base class TargetInstrInfo.
+// default to member functions in base class TargetInstrInfo.
//
//===----------------------------------------------------------------------===//
// All immediate constants are in position 1 except the
// store instructions and SETxx.
- //
+ //
virtual int getImmedConstantPos(MachineOpCode opCode) const {
bool ignore;
if (this->maxImmedConstant(opCode, ignore) != 0) {
//===-- SparcV9Internals.h --------------------------------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file defines stuff that is to be private to the SparcV9 backend, but is
// shared among different portions of the backend.
//
SPARC_LD, /* Load instructions */
SPARC_ST, /* Store instructions */
SPARC_SINGLE, /* Instructions that must issue by themselves */
-
+
SPARC_INV, /* This should stay at the end for the next value */
SPARC_NUM_SCHED_CLASSES = SPARC_INV
};
//---------------------------------------------------------------------------
-// enum SparcV9MachineOpCode.
+// enum SparcV9MachineOpCode.
// const TargetInstrDescriptor SparcV9MachineInstrDesc[]
-//
+//
// Purpose:
// Description of UltraSparcV9 machine instructions.
-//
+//
//---------------------------------------------------------------------------
namespace V9 {
//---------------------------------------------------------------------------
// class SparcV9SchedInfo
-//
+//
// Purpose:
// Interface to instruction scheduling information for UltraSPARC.
// The parameter values above are based on UltraSPARC IIi.
// This function decomposes a single instance of such a reference.
// Return value: true if the instruction was replaced; false otherwise.
-//
+//
bool DecomposeArrayRef(GetElementPtrInst* GEP);
/// Peephole optimization pass operating on machine code
//===-- SparcJITInfo.cpp - Implement the JIT interfaces for SparcV9 -------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file implements the JIT interfaces for the SparcV9 target.
Addr[4] = 0x82114001;
// or %g1, %lo(Target), %g1 ;; get lowest 10 bits of Target into %g1
Addr[5] = BUILD_ORI(G1, JumpTarget, G1);
-
+
// jmpl %g1, %g0, %g0 ;; indirect branch on %g1
Addr[6] = 0x81C00001;
// nop ;; delay slot
}
-static void SaveRegisters(uint64_t DoubleFP[], uint64_t CC[],
+static void SaveRegisters(uint64_t DoubleFP[], uint64_t CC[],
uint64_t Globals[]) {
#if defined(__sparcv9)
__asm__ __volatile__ (// Save condition-code registers
- "stx %%fsr, %0;\n\t"
- "rd %%fprs, %1;\n\t"
+ "stx %%fsr, %0;\n\t"
+ "rd %%fprs, %1;\n\t"
"rd %%ccr, %2;\n\t"
: "=m"(CC[0]), "=r"(CC[1]), "=r"(CC[2]));
"=m"(DoubleFP[10]), "=m"(DoubleFP[11]),
"=m"(DoubleFP[12]), "=m"(DoubleFP[13]),
"=m"(DoubleFP[14]), "=m"(DoubleFP[15]));
-
+
__asm__ __volatile__ (// Save Double FP registers, part 2
"std %%f32, %0;\n\t" "std %%f34, %1;\n\t"
"std %%f36, %2;\n\t" "std %%f38, %3;\n\t"
#endif
}
-static void RestoreRegisters(uint64_t DoubleFP[], uint64_t CC[],
+static void RestoreRegisters(uint64_t DoubleFP[], uint64_t CC[],
uint64_t Globals[]) {
#if defined(__sparcv9)
__asm__ __volatile__ (// Restore condition-code registers
- "ldx %0, %%fsr;\n\t"
+ "ldx %0, %%fsr;\n\t"
"wr %1, 0, %%fprs;\n\t"
- "wr %2, 0, %%ccr;\n\t"
+ "wr %2, 0, %%ccr;\n\t"
:: "m"(CC[0]), "r"(CC[1]), "r"(CC[2]));
__asm__ __volatile__ (// Restore globals g1 and g5
// GCC says: `asm' only allows up to thirty parameters!
__asm__ __volatile__ (// Restore Single/Double FP registers, part 1
- "ldd %0, %%f0;\n\t" "ldd %1, %%f2;\n\t"
- "ldd %2, %%f4;\n\t" "ldd %3, %%f6;\n\t"
- "ldd %4, %%f8;\n\t" "ldd %5, %%f10;\n\t"
- "ldd %6, %%f12;\n\t" "ldd %7, %%f14;\n\t"
- "ldd %8, %%f16;\n\t" "ldd %9, %%f18;\n\t"
+ "ldd %0, %%f0;\n\t" "ldd %1, %%f2;\n\t"
+ "ldd %2, %%f4;\n\t" "ldd %3, %%f6;\n\t"
+ "ldd %4, %%f8;\n\t" "ldd %5, %%f10;\n\t"
+ "ldd %6, %%f12;\n\t" "ldd %7, %%f14;\n\t"
+ "ldd %8, %%f16;\n\t" "ldd %9, %%f18;\n\t"
"ldd %10, %%f20;\n\t" "ldd %11, %%f22;\n\t"
"ldd %12, %%f24;\n\t" "ldd %13, %%f26;\n\t"
"ldd %14, %%f28;\n\t" "ldd %15, %%f30;\n\t"
// has been performed. Having a variable sized alloca disables frame pointer
// elimination currently, even if it's dead. This is a gross hack.
alloca(42+Offset);
-
+
// Make sure that what we're about to overwrite is indeed "save".
if (*CodeBegin != 0x9DE3BF40) {
std::cerr << "About to overwrite smthg not a save instr!";
///
void *SparcV9JITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
if (Fn != CompilationCallback) {
- // If this is just a call to an external function,
+ // If this is just a call to an external function,
MCE.startFunctionStub(4*8);
unsigned *Stub = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
for (unsigned i = 0; i != 8; ++i)
//===- SparcV9JITInfo.h - SparcV9 Target JIT interface ----------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV9 implementation of the TargetJITInfo class,
/// is not supported for this target.
///
virtual void addPassesToJITCompile(FunctionPassManager &PM);
-
+
/// replaceMachineCodeForFunction - Make it so that calling the function
/// whose machine code is at OLD turns into a call to NEW, perhaps by
/// overwriting OLD with a branch to NEW. This is used for self-modifying
//===-- SparcV9PeepholeOpts.cpp -------------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// Support for performing several peephole opts in one or a few passes over the
// machine code of a method.
//
// This instruction is in a delay slot of its predecessor, so
// replace it with a nop. By replacing in place, we save having
// to update the I-I maps.
- //
+ //
assert(ndelay == 1 && "Not yet handling multiple-delay-slot targets");
BBI->replace(V9::NOP, 0);
return;
}
}
-
+
// The instruction is not in a delay slot, so we can simply erase it.
mvec.erase(BBI);
BBI = mvec.end();
} else if (MI->getOpcode() == V9::ADDr || MI->getOpcode() == V9::ORr ||
MI->getOpcode() == V9::ADDi || MI->getOpcode() == V9::ORi) {
unsigned srcWithDestReg;
-
+
for (srcWithDestReg = 0; srcWithDestReg < 2; ++srcWithDestReg)
if (MI->getOperand(srcWithDestReg).hasAllocatedReg() &&
MI->getOperand(srcWithDestReg).getReg()
== MI->getOperand(2).getReg())
break;
-
+
if (srcWithDestReg == 2)
return false;
else {
(MI->getOperand(otherOp).hasAllocatedReg() &&
MI->getOperand(otherOp).getReg() ==
target.getRegInfo()->getZeroRegNum()) ||
-
+
// or operand otherOp == 0
(MI->getOperand(otherOp).getType()
== MachineOperand::MO_SignExtendedImmed &&
// Apply a list of peephole optimizations to this machine instruction
// within its local context. They are allowed to delete MI or any
-// instruction before MI, but not
+// instruction before MI, but not
//
bool PeepholeOpts::visit(MachineBasicBlock& mvec,
MachineBasicBlock::iterator BBI) const {
//===- SparcV9PreSelection.cpp - Specialize LLVM code for SparcV9 ---------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file defines the PreSelection pass which specializes LLVM code for
//===--------------------------------------------------------------------===//
// PreSelection Pass - Specialize LLVM code for the SparcV9 instr. selector.
- //
+ //
class PreSelection : public FunctionPass, public InstVisitor<PreSelection> {
const TargetInstrInfo &instrInfo;
const char *getPassName() const { return "SparcV9 Instr. Pre-selection"; }
// These methods do the actual work of specializing code
- void visitInstruction(Instruction &I); // common work for every instr.
+ void visitInstruction(Instruction &I); // common work for every instr.
void visitGetElementPtrInst(GetElementPtrInst &I);
void visitCallInst(CallInst &I);
void visitPHINode(PHINode &PN);
}
// Helper functions for visiting operands of every instruction
- //
+ //
// visitOperands() works on every operand in [firstOp, lastOp-1].
// If lastOp==0, lastOp defaults to #operands or #incoming Phi values.
- //
+ //
// visitOneOperand() does all the work for one operand.
- //
+ //
void visitOperands(Instruction &I, int firstOp=0);
void visitOneOperand(Instruction &I, Value* Op, unsigned opNum,
Instruction& insertBefore);
Instruction& insertBefore)
{
Value *getArg1, *getArg2;
-
+
switch(CE->getOpcode())
{
case Instruction::Cast:
return new GetElementPtrInst(getArg1,
std::vector<Value*>(CE->op_begin()+1, CE->op_end()),
"constantGEP:" + getArg1->getName(), &insertBefore);
-
+
case Instruction::Select: {
Value *C, *S1, *S2;
C = CE->getOperand (0);
S2 = DecomposeConstantExpr (CEarg, insertBefore);
return new SelectInst (C, S1, S2, "constantSelect", &insertBefore);
}
-
+
default: // must be a binary operator
assert(CE->getOpcode() >= Instruction::BinaryOpsBegin &&
CE->getOpcode() < Instruction::BinaryOpsEnd &&
/// depends on the type of instruction and on the target architecture.
/// -- For any constants that cannot be put in an immediate field,
/// load address into virtual register first, and then load the constant.
-///
+///
/// firstOp and lastOp can be used to skip leading and trailing operands.
/// If lastOp is 0, it defaults to #operands or #incoming Phi values.
-///
+///
inline void PreSelection::visitOperands(Instruction &I, int firstOp) {
// For any instruction other than PHI, copies go just before the instr.
for (unsigned i = firstOp, e = I.getNumOperands(); i != e; ++i)
// For a PHI, operand copies must be before the terminator of the
// appropriate predecessor basic block. Remaining logic is simple
// so just handle PHIs and other instructions separately.
- //
+ //
for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i)
visitOneOperand(PN, PN.getIncomingValue(i),
PN.getOperandNumForIncomingValue(i),
// Common work for *all* instructions. This needs to be called explicitly
// by other visit<InstructionType> functions.
-inline void PreSelection::visitInstruction(Instruction &I) {
+inline void PreSelection::visitInstruction(Instruction &I) {
visitOperands(I); // Perform operand transformations
}
// GetElementPtr instructions: check if pointer is a global
-void PreSelection::visitGetElementPtrInst(GetElementPtrInst &I) {
+void PreSelection::visitGetElementPtrInst(GetElementPtrInst &I) {
Instruction* curI = &I;
// The Sparc backend doesn't handle array indexes that are not long types, so
//===-- SparcV9PrologEpilogCodeInserter.cpp - Insert Fn Prolog & Epilog ---===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This is the SparcV9 target's own PrologEpilogInserter. It creates prolog and
namespace {
struct InsertPrologEpilogCode : public MachineFunctionPass {
const char *getPassName() const { return "SparcV9 Prolog/Epilog Inserter"; }
-
+
bool runOnMachineFunction(MachineFunction &F) {
if (!F.getInfo<SparcV9FunctionInfo>()->isCompiledAsLeafMethod()) {
InsertPrologCode(F);
}
return false;
}
-
+
void InsertPrologCode(MachineFunction &F);
void InsertEpilogCode(MachineFunction &F);
};
unsigned staticStackSize = MF.getInfo<SparcV9FunctionInfo>()->getStaticStackSize();
if (staticStackSize < (unsigned)SparcV9FrameInfo::MinStackFrameSize)
staticStackSize = SparcV9FrameInfo::MinStackFrameSize;
- if (unsigned padsz = staticStackSize %
+ if (unsigned padsz = staticStackSize %
SparcV9FrameInfo::StackFrameSizeAlignment)
staticStackSize += SparcV9FrameInfo::StackFrameSizeAlignment - padsz;
return staticStackSize;
std::vector<MachineInstr*> mvec;
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo& frameInfo = *TM.getFrameInfo();
-
+
// The second operand is the stack size. If it does not fit in the
// immediate field, we have to use a free register to hold the size.
// See the comments below for the choice of this register.
.addMReg(uregNum, MachineOperand::Def);
M->getOperand(0).markHi32();
mvec.push_back(M);
-
+
M = BuildMI(V9::ORi, 3).addMReg(uregNum).addSImm(C)
.addMReg(uregNum, MachineOperand::Def);
M->getOperand(1).markLo32();
mvec.push_back(M);
-
+
M = BuildMI(V9::SRAi5, 3).addMReg(uregNum).addZImm(0)
.addMReg(uregNum, MachineOperand::Def);
mvec.push_back(M);
-
+
// Now generate the SAVE using the value in register %g1
M = BuildMI(V9::SAVEr,3).addMReg(SP).addMReg(uregNum)
.addMReg(SP,MachineOperand::Def);
// The first K=6 arguments are always received via int arg regs
// (%i0 ... %i5 if K=6) .
// By copying the varargs arguments to the stack, va_arg() then can
- // simply assume that all vararg arguments are in an array on the stack.
+ // simply assume that all vararg arguments are in an array on the stack.
if (MF.getFunction()->getFunctionType()->isVarArg()) {
int numFixedArgs = MF.getFunction()->getFunctionType()->getNumParams();
int numArgRegs = TM.getRegInfo()->getNumOfIntArgRegs();
if (TermInst->getOpcode() == Instruction::Ret)
{
int ZR = TM.getRegInfo()->getZeroRegNum();
- MachineInstr *Restore =
+ MachineInstr *Restore =
BuildMI(V9::RESTOREi, 3).addMReg(ZR).addSImm(0)
.addMReg(ZR, MachineOperand::Def);
-
+
MachineCodeForInstruction &termMvec =
MachineCodeForInstruction::get(TermInst);
-
+
// Remove the NOPs in the delay slots of the return instruction
unsigned numNOPs = 0;
while (termMvec.back()->getOpcode() == V9::NOP)
++numNOPs;
}
assert(termMvec.back() == &MBB.back());
-
+
// Check that we found the right number of NOPs and have the right
// number of instructions to replace them.
unsigned ndelays = MII.getNumDelaySlots(termMvec.back()->getOpcode());
assert(numNOPs == ndelays && "Missing NOPs in delay slots?");
assert(ndelays == 1 && "Cannot use epilog code for delay slots?");
-
+
// Append the epilog code to the end of the basic block.
MBB.push_back(Restore);
}
//===-- SparcV9RegClassInfo.cpp - Register class def'ns for SparcV9 -------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file defines the methods used by the SparcV9 register allocator
// If there is call interf, try to allocate non-volatile. If that fails
// try to allocate a volatile and insert save across calls
// If both above fail, spill.
-//
+//
//-----------------------------------------------------------------------------
void SparcV9IntRegClass::colorIGNode(IGNode * Node,
const std::vector<bool> &IsColorUsedArr) const
if (DEBUG_RA)
std::cerr << "\nColoring LR [CallInt=" << LR->isCallInterference() <<"]:"
- << *LR << "\n";
+ << *LR << "\n";
if (LR->hasSuggestedColor()) {
unsigned SugCol = LR->getSuggestedColor();
bool ColorFound= false; // have we found a color yet?
//if this Node is between calls
- if (! LR->isCallInterference()) {
+ if (! LR->isCallInterference()) {
// start with volatiles (we can allocate volatiles safely)
- SearchStart = SparcV9IntRegClass::StartOfAllRegs;
- } else {
+ SearchStart = SparcV9IntRegClass::StartOfAllRegs;
+ } else {
// start with non volatiles (no non-volatiles)
- SearchStart = SparcV9IntRegClass::StartOfNonVolatileRegs;
+ SearchStart = SparcV9IntRegClass::StartOfNonVolatileRegs;
}
unsigned c=0; // color
-
+
// find first unused color
- for (c=SearchStart; c < SparcV9IntRegClass::NumOfAvailRegs; c++) {
+ for (c=SearchStart; c < SparcV9IntRegClass::NumOfAvailRegs; c++) {
if (!IsColorUsedArr[c]) {
ColorFound = true;
break;
//
else if (LR->isCallInterference()) {
// start from 0 - try to find even a volatile this time
- SearchStart = SparcV9IntRegClass::StartOfAllRegs;
+ SearchStart = SparcV9IntRegClass::StartOfAllRegs;
// find first unused volatile color
- for(c=SearchStart; c < SparcV9IntRegClass::StartOfNonVolatileRegs; c++) {
+ for(c=SearchStart; c < SparcV9IntRegClass::StartOfNonVolatileRegs; c++) {
if (! IsColorUsedArr[c]) {
ColorFound = true;
break;
}
}
- if (ColorFound) {
- LR->setColor(c);
+ if (ColorFound) {
+ LR->setColor(c);
// get the live range corresponding to live var
- // since LR span across calls, must save across calls
+ // since LR span across calls, must save across calls
//
if (DEBUG_RA)
std::cerr << "\n Colored after SECOND search with col " << c;
// If we couldn't find a color regardless of call interference - i.e., we
// don't have either a volatile or non-volatile color left
//
- if (!ColorFound)
+ if (!ColorFound)
LR->markForSpill(); // no color found - must spill
}
// if (the LR is a 64-bit comparison) use %xcc
// else /*32-bit or smaller*/ use %icc
// }
-//
+//
// Note: The third name (%ccr) is essentially an assembly mnemonic and
// depends solely on the opcode, so the name can be chosen in EmitAssembly.
//-----------------------------------------------------------------------------
// because there is only one possible register, but more importantly, the
// spill algorithm cannot find it. In particular, we have to choose
// whether to use %xcc or %icc based on type of value compared
- //
+ //
const LiveRange* ccLR = Node->getParentLR();
const Type* setCCType = (* ccLR->begin())->getType(); // any Value in LR
assert(setCCType->isIntegral() || isa<PointerType>(setCCType));
const std::vector<bool> &IsColorUsedArr) const {
for(unsigned c = 0; c != 4; ++c)
if (!IsColorUsedArr[c]) { // find unused color
- Node->setColor(c);
+ Node->setColor(c);
return;
}
-
+
Node->getParentLR()->markForSpill();
}
#ifndef NDEBUG
// Check that the correct colors have been are marked for fp-doubles.
- //
+ //
// FIXME: This is old code that is no longer needed. Temporarily converting
// it into a big assertion just to check that the replacement logic
// (invoking SparcV9FloatRegClass::markColorsUsed() directly from
// RegClass::colorIGNode) works correctly.
- //
+ //
// In fact, this entire function should be identical to
// SparcV9IntRegClass::colorIGNode(), and perhaps can be
- // made into a general case in CodeGen/RegAlloc/RegClass.cpp.
- //
+ // made into a general case in CodeGen/RegAlloc/RegClass.cpp.
+ //
unsigned NumNeighbors = Node->getNumOfNeighbors(); // total # of neighbors
- for(unsigned n=0; n < NumNeighbors; n++) { // for each neigh
+ for(unsigned n=0; n < NumNeighbors; n++) { // for each neigh
IGNode *NeighIGNode = Node->getAdjIGNode(n);
LiveRange *NeighLR = NeighIGNode->getParentLR();
-
+
if (NeighLR->hasColor()) {
assert(IsColorUsedArr[ NeighLR->getColor() ]);
if (NeighLR->getType() == Type::DoubleTy)
assert(IsColorUsedArr[ NeighLR->getColor()+1 ]);
-
+
} else if (NeighLR->hasSuggestedColor() &&
NeighLR-> isSuggestedColorUsable() ) {
- // if the neighbour can use the suggested color
+ // if the neighbour can use the suggested color
assert(IsColorUsedArr[ NeighLR->getSuggestedColor() ]);
if (NeighLR->getType() == Type::DoubleTy)
assert(IsColorUsedArr[ NeighLR->getSuggestedColor()+1 ]);
// **NOTE: We don't check for call interferences in allocating suggested
// color in this class since ALL registers are volatile. If this fact
- // changes, we should change the following part
+ // changes, we should change the following part
//- see SparcV9IntRegClass::colorIGNode()
- //
+ //
if( LR->hasSuggestedColor() ) {
if( ! IsColorUsedArr[ LR->getSuggestedColor() ] ) {
LR->setColor( LR->getSuggestedColor() );
// cannot go there. By doing that, we provide more space for singles
// in f0 - f31
//
- if (LR->getType() == Type::DoubleTy)
+ if (LR->getType() == Type::DoubleTy)
ColorFound = findFloatColor( LR, 32, 64, IsColorUsedArr );
if (ColorFound >= 0) { // if we could find a color
- LR->setColor(ColorFound);
+ LR->setColor(ColorFound);
return;
- } else {
+ } else {
// if we didn't find a color because the LR was single precision or
// all f32-f63 range is filled, we try to allocate a register from
- // the f0 - f31 region
+ // the f0 - f31 region
unsigned SearchStart; // start pos of color in pref-order
//if this Node is between calls (i.e., no call interferences )
if (! isCallInterf) {
// start with volatiles (we can allocate volatiles safely)
- SearchStart = SparcV9FloatRegClass::StartOfAllRegs;
+ SearchStart = SparcV9FloatRegClass::StartOfAllRegs;
} else {
// start with non volatiles (no non-volatiles)
- SearchStart = SparcV9FloatRegClass::StartOfNonVolatileRegs;
+ SearchStart = SparcV9FloatRegClass::StartOfNonVolatileRegs;
}
-
+
ColorFound = findFloatColor(LR, SearchStart, 32, IsColorUsedArr);
}
if (ColorFound >= 0) { // if we could find a color
- LR->setColor(ColorFound);
+ LR->setColor(ColorFound);
return;
- } else if (isCallInterf) {
+ } else if (isCallInterf) {
// We are here because there is a call interference and no non-volatile
// color could be found.
// Now try to allocate even a volatile color
- ColorFound = findFloatColor(LR, SparcV9FloatRegClass::StartOfAllRegs,
+ ColorFound = findFloatColor(LR, SparcV9FloatRegClass::StartOfAllRegs,
SparcV9FloatRegClass::StartOfNonVolatileRegs,
IsColorUsedArr);
}
// entry in the array directly for float regs, and checks the pair [R,R+1]
// for double-precision registers
// It returns -1 if no unused color is found.
-//
+//
int SparcV9FloatRegClass::findUnusedColor(int RegTypeWanted,
const std::vector<bool> &IsColorUsedArr) const
{
// type of the Node (i.e., float/double)
//-----------------------------------------------------------------------------
-int SparcV9FloatRegClass::findFloatColor(const LiveRange *LR,
+int SparcV9FloatRegClass::findFloatColor(const LiveRange *LR,
unsigned Start,
- unsigned End,
+ unsigned End,
const std::vector<bool> &IsColorUsedArr) const
{
- if (LR->getType() == Type::DoubleTy) {
- // find first unused color for a double
+ if (LR->getType() == Type::DoubleTy) {
+ // find first unused color for a double
assert(Start % 2 == 0 && "Odd register number could be used for double!");
for (unsigned c=Start; c < End ; c+= 2)
if (!IsColorUsedArr[c]) {
//===-- SparcV9RegClassInfo.h - Register class def'ns for SparcV9 -*- C++ -*-=//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file defines the register classes used by the SparcV9 target. It
//-----------------------------------------------------------------------------
struct SparcV9IntRegClass : public TargetRegClassInfo {
- SparcV9IntRegClass(unsigned ID)
+ SparcV9IntRegClass(unsigned ID)
: TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) { }
void colorIGNode(IGNode *Node,
const std::vector<bool> &IsColorUsedArr) const;
inline bool isRegVolatile(int Reg) const {
- return (Reg < (int)StartOfNonVolatileRegs);
+ return (Reg < (int)StartOfNonVolatileRegs);
}
inline bool modifiedByCall(int Reg) const {
enum { // colors possible for a LR (in preferred order)
// --- following colors are volatile across function calls
// %g0 can't be used for coloring - always 0
- o0, o1, o2, o3, o4, o5, o7, // %o0-%o5,
+ o0, o1, o2, o3, o4, o5, o7, // %o0-%o5,
- // %o6 is sp,
+ // %o6 is sp,
// all %0's can get modified by a call
// --- following colors are NON-volatile across function calls
l0, l1, l2, l3, l4, l5, l6, l7, // %l0-%l7
- i0, i1, i2, i3, i4, i5, // %i0-%i5: i's need not be preserved
-
+ i0, i1, i2, i3, i4, i5, // %i0-%i5: i's need not be preserved
+
// %i6 is the fp - so not allocated
// %i7 is the ret address by convention - can be used for others
// max # of colors reg coloring can allocate (NumOfAvailRegs)
// --- following colors are not available for allocation within this phase
- // --- but can appear for pre-colored ranges
+ // --- but can appear for pre-colored ranges
i6, i7, g0, g1, g2, g3, g4, g5, g6, g7, o6,
NumOfAllRegs, // Must be first AFTER registers...
-
+
//*** NOTE: If we decide to use some %g regs, they are volatile
// (see sparc64ABI)
// Move the %g regs from the end of the enumeration to just above the
StartOfNonVolatileRegs = l0,
StartOfAllRegs = o0,
-
+
ModifiedByCall = o7,
};
unsigned End,
const std::vector<bool> &IsColorUsedArr) const;
public:
- SparcV9FloatRegClass(unsigned ID)
+ SparcV9FloatRegClass(unsigned ID)
: TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {}
// This method marks the registers used for a given register number.
// This marks a single register for Float regs, but the R,R+1 pair
// for double-precision registers.
- //
+ //
virtual void markColorsUsed(unsigned RegInClass,
int UserRegType,
int RegTypeWanted,
std::vector<bool> &IsColorUsedArr) const;
-
+
// This method finds unused registers of the specified register type,
// using the given "used" flag array IsColorUsedArr. It checks a single
// entry in the array directly for float regs, and checks the pair [R,R+1]
// for double-precision registers
// It returns -1 if no unused color is found.
- //
+ //
virtual int findUnusedColor(int RegTypeWanted,
const std::vector<bool> &IsColorUsedArr) const;
inline bool isRegVolatile(int Reg) const { return true; }
enum {
- f0, f1, f2, f3, f4, f5, f6, f7, f8, f9,
+ f0, f1, f2, f3, f4, f5, f6, f7, f8, f9,
f10, f11, f12, f13, f14, f15, f16, f17, f18, f19,
f20, f21, f22, f23, f24, f25, f26, f27, f28, f29,
f30, f31, f32, f33, f34, f35, f36, f37, f38, f39,
//-----------------------------------------------------------------------------
// Int CC Register Class
// Only one integer cc register is available. However, this register is
-// referred to as %xcc or %icc when instructions like subcc are executed but
+// referred to as %xcc or %icc when instructions like subcc are executed but
// referred to as %ccr (i.e., %xcc . %icc") when this register is moved
// into an integer register using RD or WR instrcutions. So, three ids are
// allocated for the three names.
//-----------------------------------------------------------------------------
struct SparcV9IntCCRegClass : public TargetRegClassInfo {
- SparcV9IntCCRegClass(unsigned ID)
+ SparcV9IntCCRegClass(unsigned ID)
: TargetRegClassInfo(ID, 1, 3) { }
-
+
void colorIGNode(IGNode *Node,
const std::vector<bool> &IsColorUsedArr) const;
//-----------------------------------------------------------------------------
struct SparcV9FloatCCRegClass : public TargetRegClassInfo {
- SparcV9FloatCCRegClass(unsigned ID)
+ SparcV9FloatCCRegClass(unsigned ID)
: TargetRegClassInfo(ID, 4, 4) { }
void colorIGNode(IGNode *Node,
const std::vector<bool> &IsColorUsedArr) const;
-
+
// according to the 64-bit SparcV9 ABI, all floating-point CC regs are
// volatile.
inline bool isRegVolatile(int Reg) const { return true; }
enum {
fcc0, fcc1, fcc2, fcc3
};
-
+
const char * const getRegName(unsigned reg) const;
};
//-----------------------------------------------------------------------------
struct SparcV9SpecialRegClass : public TargetRegClassInfo {
- SparcV9SpecialRegClass(unsigned ID)
+ SparcV9SpecialRegClass(unsigned ID)
: TargetRegClassInfo(ID, 0, 1) { }
void colorIGNode(IGNode *Node,
const std::vector<bool> &IsColorUsedArr) const {
assert(0 && "SparcV9SpecialRegClass should never be used for allocation");
}
-
+
// all currently included special regs are volatile
inline bool isRegVolatile(int Reg) const { return true; }
//===-- SparcV9RegInfo.cpp - SparcV9 Target Register Information ----------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains implementations of SparcV9 specific helper methods
MachineRegClassArr.push_back(new SparcV9IntCCRegClass(IntCCRegClassID));
MachineRegClassArr.push_back(new SparcV9FloatCCRegClass(FloatCCRegClassID));
MachineRegClassArr.push_back(new SparcV9SpecialRegClass(SpecialRegClassID));
-
- assert(SparcV9FloatRegClass::StartOfNonVolatileRegs == 32 &&
+
+ assert(SparcV9FloatRegClass::StartOfNonVolatileRegs == 32 &&
"32 Float regs are used for float arg passing");
}
}
// Returns the register containing the return address.
-// It should be made sure that this register contains the return
+// It should be made sure that this register contains the return
// value when a return instruction is reached.
//
unsigned SparcV9RegInfo::getReturnAddressReg() const {
static const char * const IntRegNames[] = {
"o0", "o1", "o2", "o3", "o4", "o5", "o7",
"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
- "i0", "i1", "i2", "i3", "i4", "i5",
+ "i0", "i1", "i2", "i3", "i4", "i5",
"i6", "i7",
- "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
+ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
"o6"
-};
+};
const char * const SparcV9IntRegClass::getRegName(unsigned reg) const {
assert(reg < NumOfAllRegs);
return IntRegNames[reg];
}
-static const char * const FloatRegNames[] = {
- "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
+static const char * const FloatRegNames[] = {
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
"f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
"f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
"f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
return FloatRegNames[reg];
}
-static const char * const IntCCRegNames[] = {
+static const char * const IntCCRegNames[] = {
"xcc", "icc", "ccr"
};
return IntCCRegNames[reg];
}
-static const char * const FloatCCRegNames[] = {
+static const char * const FloatCCRegNames[] = {
"fcc0", "fcc1", "fcc2", "fcc3"
};
return FloatCCRegNames[reg];
}
-static const char * const SpecialRegNames[] = {
+static const char * const SpecialRegNames[] = {
"fsr"
};
// Get the register number for the specified argument #argNo,
-//
+//
// Return value:
-// getInvalidRegNum(), if there is no int register available for the arg.
+// getInvalidRegNum(), if there is no int register available for the arg.
// regNum, otherwise (this is NOT the unified reg. num).
// regClassId is set to the register class ID.
-//
+//
int
SparcV9RegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall,
unsigned argNo, unsigned& regClassId) const
// Get the register number for the specified FP argument #argNo,
// Use INT regs for FP args if this is a varargs call.
-//
+//
// Return value:
-// getInvalidRegNum(), if there is no int register available for the arg.
+// getInvalidRegNum(), if there is no int register available for the arg.
// regNum, otherwise (this is NOT the unified reg. num).
// regClassId is set to the register class ID.
-//
+//
int
SparcV9RegInfo::regNumForFPArg(unsigned regType,
bool inCallee, bool isVarArgsCall,
const Type* type) const
{
switch (regClassID) {
- case IntRegClassID: return IntRegType;
+ case IntRegClassID: return IntRegType;
case FloatRegClassID:
if (type == Type::FloatTy) return FPSingleRegType;
else if (type == Type::DoubleTy) return FPDoubleRegType;
assert(0 && "Unknown type in FloatRegClass"); return 0;
- case IntCCRegClassID: return IntCCRegType;
- case FloatCCRegClassID: return FloatCCRegType;
- case SpecialRegClassID: return SpecialRegType;
+ case IntCCRegClassID: return IntCCRegType;
+ case FloatCCRegClassID: return FloatCCRegType;
+ case SpecialRegClassID: return SpecialRegType;
default: assert( 0 && "Unknown reg class ID"); return 0;
}
}
int SparcV9RegInfo::getRegType(int unifiedRegNum) const
{
- if (unifiedRegNum < 32)
+ if (unifiedRegNum < 32)
return IntRegType;
else if (unifiedRegNum < (32 + 32))
return FPSingleRegType;
return FPDoubleRegType;
else if (unifiedRegNum < (64+32+3))
return IntCCRegType;
- else if (unifiedRegNum < (64+32+3+4))
- return FloatCCRegType;
- else if (unifiedRegNum < (64+32+3+4+1))
- return SpecialRegType;
- else
+ else if (unifiedRegNum < (64+32+3+4))
+ return FloatCCRegType;
+ else if (unifiedRegNum < (64+32+3+4+1))
+ return SpecialRegType;
+ else
assert(0 && "Invalid unified register number in getRegType");
return 0;
}
bool isCCReg) const {
Type::TypeID ty = type->getTypeID();
unsigned res;
-
+
// FIXME: Comparing types like this isn't very safe...
if ((ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
(ty == Type::FunctionTyID) || (ty == Type::PointerTyID) )
res = IntRegClassID; // sparc int reg (ty=0: void)
else if (ty <= Type::DoubleTyID)
res = FloatRegClassID; // sparc float reg class
- else {
+ else {
//std::cerr << "TypeID: " << ty << "\n";
assert(0 && "Cannot resolve register class for type");
return 0;
}
-
+
if (isCCReg)
- return res + 2; // corresponding condition code register
- else
+ return res + 2; // corresponding condition code register
+ else
return res;
}
// Suggests a register for the ret address in the RET machine instruction.
// We always suggest %i7 by convention.
//---------------------------------------------------------------------------
-void SparcV9RegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
+void SparcV9RegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
LiveRangeInfo& LRI) const {
assert(target.getInstrInfo()->isReturn(RetMI->getOpcode()));
-
+
// return address is always mapped to i7 so set it immediately
RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID,
SparcV9IntRegClass::i7));
-
- // Possible Optimization:
+
+ // Possible Optimization:
// Instead of setting the color, we can suggest one. In that case,
// we have to test later whether it received the suggested color.
// In that case, a LR has to be created at the start of method.
// MachineOperand & MO = RetMI->getOperand(0);
// const Value *RetAddrVal = MO.getVRegValue();
// assert( RetAddrVal && "LR for ret address must be created at start");
- // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
- // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
+ // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
+ // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
// SparcV9IntRegOrdr::i7) );
}
SparcV9RegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
LiveRangeInfo& LRI) const
{
- CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
+ CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
const Value *RetAddrVal = argDesc->getReturnAddrReg();
assert(RetAddrVal && "INTERNAL ERROR: Return address value is required");
//---------------------------------------------------------------------------
-// This method will suggest colors to incoming args to a method.
-// According to the SparcV9 ABI, the first 6 incoming args are in
+// This method will suggest colors to incoming args to a method.
+// According to the SparcV9 ABI, the first 6 incoming args are in
// %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float).
// If the arg is passed on stack due to the lack of regs, NOTHING will be
// done - it will be colored (or spilled) as a normal live range.
//---------------------------------------------------------------------------
-void SparcV9RegInfo::suggestRegs4MethodArgs(const Function *Meth,
- LiveRangeInfo& LRI) const
+void SparcV9RegInfo::suggestRegs4MethodArgs(const Function *Meth,
+ LiveRangeInfo& LRI) const
{
// Check if this is a varArgs function. needed for choosing regs.
bool isVarArgs = isVarArgsFunction(Meth->getType());
-
+
// Count the arguments, *ignoring* whether they are int or FP args.
// Use this common arg numbering to pick the right int or fp register.
unsigned argNo=0;
I != E; ++I, ++argNo) {
LiveRange *LR = LRI.getLiveRangeForValue(I);
assert(LR && "No live range found for method arg");
-
+
unsigned regType = getRegTypeForLR(LR);
unsigned regClassIDOfArgReg = BadRegClass; // for chosen reg (unused)
-
+
int regNum = (regType == IntRegType)
? regNumForIntArg(/*inCallee*/ true, isVarArgs, argNo, regClassIDOfArgReg)
: regNumForFPArg(regType, /*inCallee*/ true, isVarArgs, argNo,
- regClassIDOfArgReg);
-
+ regClassIDOfArgReg);
+
if (regNum != getInvalidRegNum())
LR->setSuggestedColor(regNum);
}
// the correct hardware registers if they did not receive the correct
// (suggested) color through graph coloring.
//---------------------------------------------------------------------------
-void SparcV9RegInfo::colorMethodArgs(const Function *Meth,
+void SparcV9RegInfo::colorMethodArgs(const Function *Meth,
LiveRangeInfo &LRI,
std::vector<MachineInstr*>& InstrnsBefore,
std::vector<MachineInstr*>& InstrnsAfter) const {
unsigned regType = getRegTypeForLR(LR);
unsigned RegClassID = LR->getRegClassID();
-
+
// Find whether this argument is coming in a register (if not, on stack)
// Also find the correct register the argument must use (UniArgReg)
//
bool isArgInReg = false;
unsigned UniArgReg = getInvalidRegNum(); // reg that LR MUST be colored with
unsigned regClassIDOfArgReg = BadRegClass; // reg class of chosen reg
-
+
int regNum = (regType == IntRegType)
? regNumForIntArg(/*inCallee*/ true, isVarArgs,
argNo, regClassIDOfArgReg)
: regNumForFPArg(regType, /*inCallee*/ true, isVarArgs,
argNo, regClassIDOfArgReg);
-
+
if(regNum != getInvalidRegNum()) {
isArgInReg = true;
UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum);
}
-
+
if( ! LR->isMarkedForSpill() ) { // if this arg received a register
unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
if( UniLRReg == UniArgReg )
continue;
- // We are here because the LR did not receive the suggested
+ // We are here because the LR did not receive the suggested
// but LR received another register.
- // Now we have to copy the %i reg (or stack pos of arg)
+ // Now we have to copy the %i reg (or stack pos of arg)
// to the register the LR was colored with.
-
+
// if the arg is coming in UniArgReg register, it MUST go into
// the UniLRReg register
//
if( isArgInReg ) {
if( regClassIDOfArgReg != RegClassID ) {
// NOTE: This code has not been well-tested.
-
+
// It is a variable argument call: the float reg must go in a %o reg.
// We have to move an int reg to a float reg via memory.
- //
+ //
assert(isVarArgs &&
- RegClassID == FloatRegClassID &&
+ RegClassID == FloatRegClassID &&
regClassIDOfArgReg == IntRegClassID &&
"This should only be an Int register for an FP argument");
-
+
int TmpOff = MachineFunction::get(Meth).getInfo<SparcV9FunctionInfo>()->pushTempValue(
getSpilledRegSize(regType));
cpReg2MemMI(InstrnsBefore,
UniArgReg, getFramePointer(), TmpOff, IntRegType);
-
+
cpMem2RegMI(InstrnsBefore,
getFramePointer(), TmpOff, UniLRReg, regType);
}
cpMem2RegMI(InstrnsBefore,
getFramePointer(), offsetFromFP, UniLRReg, regType);
}
-
+
} // if LR received a color
- else {
+ else {
// Now, the LR did not receive a color. But it has a stack offset for
// spilling.
// that on to the stack pos of LR
if( isArgInReg ) {
-
+
if( regClassIDOfArgReg != RegClassID ) {
assert(0 &&
"FP arguments to a varargs function should be explicitly "
"copied to/from int registers by instruction selection!");
-
+
// It must be a float arg for a variable argument call, which
// must come in a %o reg. Move the int reg to the stack.
- //
+ //
assert(isVarArgs && regClassIDOfArgReg == IntRegClassID &&
"This should only be an Int register for an FP argument");
-
+
cpReg2MemMI(InstrnsBefore, UniArgReg,
getFramePointer(), LR->getSpillOffFromFP(), IntRegType);
}
else {
- // Now the arg is coming on stack. Since the LR did NOT
+ // Now the arg is coming on stack. Since the LR did NOT
// received a register as well, it is allocated a stack position. We
// can simply change the stack position of the LR. We can do this,
// since this method is called before any other method that makes
// uses of the stack pos of the LR (e.g., updateMachineInstr)
- //
+ //
const TargetFrameInfo& frameInfo = *target.getFrameInfo();
int offsetFromFP =
frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
assert(argSize <= slotSize && "Insufficient slot size!");
offsetFromFP += slotSize - argSize;
}
-
+
LR->modifySpillOffFromFP( offsetFromFP );
}
// This method is called before graph coloring to suggest colors to the
// outgoing call args and the return value of the call.
//---------------------------------------------------------------------------
-void SparcV9RegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
+void SparcV9RegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
LiveRangeInfo& LRI) const {
assert ( (target.getInstrInfo())->isCall(CallMI->getOpcode()) );
- CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
-
+ CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
+
suggestReg4CallAddr(CallMI, LRI);
// First color the return value of the call instruction, if any.
// The return value will be in %o0 if the value is an integer type,
// or in %f0 if the value is a float type.
- //
+ //
if (const Value *RetVal = argDesc->getReturnValue()) {
LiveRange *RetValLR = LRI.getLiveRangeForValue(RetVal);
assert(RetValLR && "No LR for return Value of call!");
unsigned RegClassID = RetValLR->getRegClassID();
// now suggest a register depending on the register class of ret arg
- if( RegClassID == IntRegClassID )
+ if( RegClassID == IntRegClassID )
RetValLR->setSuggestedColor(SparcV9IntRegClass::o0);
- else if (RegClassID == FloatRegClassID )
+ else if (RegClassID == FloatRegClassID )
RetValLR->setSuggestedColor(SparcV9FloatRegClass::f0 );
else assert( 0 && "Unknown reg class for return value of call\n");
}
// Now, go thru call args - implicit operands of the call MI
unsigned NumOfCallArgs = argDesc->getNumArgs();
-
+
for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0;
- i < NumOfCallArgs; ++i, ++argNo) {
+ i < NumOfCallArgs; ++i, ++argNo) {
const Value *CallArg = argDesc->getArgInfo(i).getArgVal();
-
+
// get the LR of call operand (parameter)
- LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
+ LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
if (!LR)
continue; // no live ranges for constants and labels
? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false,
argNo, regClassIDOfArgReg)
: regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false,
- argNo, regClassIDOfArgReg);
-
+ argNo, regClassIDOfArgReg);
+
// If a register could be allocated, use it.
// If not, do NOTHING as this will be colored as a normal value.
if(regNum != getInvalidRegNum())
// this method is called for an LLVM return instruction to identify which
// values will be returned from this method and to suggest colors.
//---------------------------------------------------------------------------
-void SparcV9RegInfo::suggestReg4RetValue(MachineInstr *RetMI,
+void SparcV9RegInfo::suggestReg4RetValue(MachineInstr *RetMI,
LiveRangeInfo& LRI) const {
assert( target.getInstrInfo()->isReturn( RetMI->getOpcode() ) );
unsigned SrcReg,
unsigned DestReg,
int RegType) const {
- assert( ((int)SrcReg != getInvalidRegNum()) &&
+ assert( ((int)SrcReg != getInvalidRegNum()) &&
((int)DestReg != getInvalidRegNum()) &&
"Invalid Register");
-
+
MachineInstr * MI = NULL;
-
+
switch( RegType ) {
-
+
case IntCCRegType:
if (getRegType(DestReg) == IntRegType) {
// copy intCC reg to int reg
MachineOperand::Def));
}
break;
-
- case FloatCCRegType:
+
+ case FloatCCRegType:
assert(0 && "Cannot copy FPCC register to any other register");
break;
-
+
case IntRegType:
MI = BuildMI(V9::ADDr, 3).addMReg(SrcReg).addMReg(getZeroRegNum())
.addMReg(DestReg, MachineOperand::Def);
break;
-
+
case FPSingleRegType:
MI = BuildMI(V9::FMOVS, 2).addMReg(SrcReg)
.addMReg(DestReg, MachineOperand::Def);
assert(0 && "Unknown RegType");
break;
}
-
+
if (MI)
mvec.push_back(MI);
}
MI = BuildMI(V9::WRCCRr, 3).addMReg(scratchReg).addMReg(SparcV9::g0)
.addMReg(SparcV9::ccr, MachineOperand::Def);
break;
-
+
case SpecialRegType: // used only for %fsr itself
case FloatCCRegType: {
if (useImmediateOffset)
std::cerr << " - could not find a color\n";
return;
}
-
+
// if a color is found
std::cerr << " colored with color "<< LR->getColor();
unsigned uRegName = getUnifiedRegNum(RegClassID, LR->getColor());
-
+
std::cerr << "[";
std::cerr<< getUnifiedRegName(uRegName);
if (RegClassID == FloatRegClassID && LR->getType() == Type::DoubleTy)
//===-- SparcV9RegInfo.h - SparcV9 Target Register Info ---------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file is used to describe the register file of the SparcV9 target to
const unsigned RegClassID; // integer ID of a reg class
const unsigned NumOfAvailRegs; // # of avail for coloring -without SP etc.
const unsigned NumOfAllRegs; // # of all registers -including SP,g0 etc.
-
+
public:
inline unsigned getRegClassID() const { return RegClassID; }
inline unsigned getNumOfAvailRegs() const { return NumOfAvailRegs; }
// This method marks the registers used for a given register number.
// This defaults to marking a single register but may mark multiple
// registers when a single number denotes paired registers.
- //
+ //
virtual void markColorsUsed(unsigned RegInClass,
int UserRegType,
int RegTypeWanted,
// checking a single entry in the array directly, but that can be overridden
// for paired registers and other such silliness.
// It returns -1 if no unused color is found.
- //
+ //
virtual int findUnusedColor(int RegTypeWanted,
const std::vector<bool> &IsColorUsedArr) const {
// find first unused color in the IsColorUsedArr directly
}
// This method should find a color which is not used by neighbors
- // (i.e., a false position in IsColorUsedArr) and
+ // (i.e., a false position in IsColorUsedArr) and
virtual void colorIGNode(IGNode *Node,
const std::vector<bool> &IsColorUsedArr) const = 0;
protected:
// A vector of all machine register classes
//
- std::vector<const TargetRegClassInfo *> MachineRegClassArr;
-
+ std::vector<const TargetRegClassInfo *> MachineRegClassArr;
+
public:
const TargetMachine ⌖
// According the definition of a MachineOperand class, a Value in a
- // machine instruction can go into either a normal register or a
+ // machine instruction can go into either a normal register or a
// condition code register. If isCCReg is true below, the ID of the condition
// code register class will be returned. Otherwise, the normal register
// class (eg. int, float) must be returned.
return classId;
}
- unsigned int getNumOfRegClasses() const {
- return MachineRegClassArr.size();
- }
+ unsigned int getNumOfRegClasses() const {
+ return MachineRegClassArr.size();
+ }
- const TargetRegClassInfo *getMachineRegClass(unsigned i) const {
- return MachineRegClassArr[i];
+ const TargetRegClassInfo *getMachineRegClass(unsigned i) const {
+ return MachineRegClassArr[i];
}
// getZeroRegNum - returns the register that is hardwired to always contain
// method args and return values etc.) with specific hardware registers
// as required. See SparcRegInfo.cpp for the implementation for Sparc.
//
- void suggestRegs4MethodArgs(const Function *Func,
+ void suggestRegs4MethodArgs(const Function *Func,
LiveRangeInfo& LRI) const;
- void suggestRegs4CallArgs(MachineInstr *CallI,
+ void suggestRegs4CallArgs(MachineInstr *CallI,
LiveRangeInfo& LRI) const;
- void suggestReg4RetValue(MachineInstr *RetI,
+ void suggestReg4RetValue(MachineInstr *RetI,
LiveRangeInfo& LRI) const;
void colorMethodArgs(const Function *Func,
inline bool modifiedByCall(int RegClassID, int Reg) const {
return MachineRegClassArr[RegClassID]->modifiedByCall(Reg);
}
-
+
// getCallAddressReg - Returns the reg used for pushing the address
// when a method is called. This can be used for other purposes
// between calls
// and returns the class ID in regClassID.
int getClassRegNum(int uRegNum, unsigned& regClassID) const {
if (uRegNum == getInvalidRegNum()) { return getInvalidRegNum(); }
-
- int totalRegs = 0, rcid = 0, NC = getNumOfRegClasses();
+
+ int totalRegs = 0, rcid = 0, NC = getNumOfRegClasses();
while (rcid < NC &&
uRegNum>= totalRegs+(int)MachineRegClassArr[rcid]->getNumOfAllRegs())
{
regClassID = rcid;
return uRegNum - totalRegs;
}
-
+
// Returns the assembly-language name of the specified machine register.
- //
+ //
const char * const getUnifiedRegName(int UnifiedRegNum) const {
unsigned regClassID = getNumOfRegClasses(); // initialize to invalid value
int regNumInClass = getClassRegNum(UnifiedRegNum, regClassID);
return MachineRegClassArr[regClassID]->getRegName(regNumInClass);
}
- // This method gives the the number of bytes of stack space allocated
+ // This method gives the the number of bytes of stack space allocated
// to a register when it is spilled to the stack, according to its
// register type.
//
- // For SparcV9, currently we allocate 8 bytes on stack for all
+ // For SparcV9, currently we allocate 8 bytes on stack for all
// register types. We can optimize this later if necessary to save stack
// space (However, should make sure that stack alignment is correct)
//
// function args and return values etc.) with specific hardware registers
// as required. See SparcV9RegInfo.cpp for the implementation.
//
- void suggestReg4RetAddr(MachineInstr *RetMI,
+ void suggestReg4RetAddr(MachineInstr *RetMI,
LiveRangeInfo &LRI) const;
void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI) const;
-
+
// Helper used by the all the getRegType() functions.
int getRegTypeForClassAndType(unsigned regClassID, const Type* type) const;
// The actual register classes in the SparcV9
//
- // **** WARNING: If this enum order is changed, also modify
- // getRegisterClassOfValue method below since it assumes this particular
+ // **** WARNING: If this enum order is changed, also modify
+ // getRegisterClassOfValue method below since it assumes this particular
// order for efficiency.
- //
- enum RegClassIDs {
+ //
+ enum RegClassIDs {
IntRegClassID, // Integer
FloatRegClassID, // Float (both single/double)
IntCCRegClassID, // Int Condition Code
}
// Returns the register containing the return address.
- // It should be made sure that this register contains the return
+ // It should be made sure that this register contains the return
// value when a return instruction is reached.
//
unsigned getReturnAddressReg() const;
//
unsigned const getNumOfIntArgRegs() const { return NumOfIntArgRegs; }
unsigned const getNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
-
+
// Compute which register can be used for an argument, if any
- //
+ //
int regNumForIntArg(bool inCallee, bool isVarArgsCall,
unsigned argNo, unsigned& regClassId) const;
int regNumForFPArg(unsigned RegType, bool inCallee, bool isVarArgsCall,
unsigned argNo, unsigned& regClassId) const;
-
+
// method used for printing a register for debugging purposes
//
const Value * getCallInstIndirectAddrVal(const MachineInstr *CallMI) const;
// The following methods are used to generate "copy" machine instructions
- // for an architecture. Currently they are used in TargetRegClass
+ // for an architecture. Currently they are used in TargetRegClass
// interface. However, they can be moved to TargetInstrInfo interface if
// necessary.
//
// TableGen to generate the register file description automatically.
// It consists of register classes and register class instances
// for the SparcV9 target.
-//
+//
// FIXME: the alignments listed here are wild guesses.
//
//===----------------------------------------------------------------------===//
abort ();
}
-void SparcV9RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI)
+void SparcV9RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI)
const {
abort ();
}
//===- SparcV9RegisterInfo.h - SparcV9 Register Information Impl -*- C++ -*-==//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV9 implementation of the MRegisterInfo class.
/* 5 */ o5, o7, l0, l1, l2,
/* 10 */ l3, l4, l5, l6, l7,
/* 15 */ i0, i1, i2, i3, i4,
- /* 20 */ i5, i6, i7, g0, g1, // i6 is frame ptr, i7 is ret addr, g0 is zero
+ /* 20 */ i5, i6, i7, g0, g1, // i6 is frame ptr, i7 is ret addr, g0 is zero
/* 25 */ g2, g3, g4, g5, g6,
/* 30 */ g7, o6, // o6 is stack ptr
/* 90 */ f58, f59, f60, f61, f62,
/* 95 */ f63,
- // SparcV9IntCCRegClass(IntCCRegClassID)
+ // SparcV9IntCCRegClass(IntCCRegClassID)
// - unified register numbers 96 ... 98 (3 regs)
/* 96 */ xcc, icc, ccr,
//===- SparcV9Relocations.h - SparcV9 Code Relocations ----------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file defines the SparcV9 target-specific relocation types.
//===-- SparcV9SchedInfo.cpp ----------------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Describe the scheduling characteristics of the UltraSparc IIi.
(see pg. 327).
** Don't put a branch in a group that crosses a 32-byte boundary!
An artificial branch is inserted after every 32 bytes, and having
- another branch will force the group to be broken into 2 groups.
+ another branch will force the group to be broken into 2 groups.
iTLB rules:
-- Don't let a loop span two memory pages, if possible
-- Several instructions must be issued in a single-instruction group:
MOVcc or MOVr, MULs/x and DIVs/x, SAVE/RESTORE, many others
-- A CALL or JMPL breaks a group, ie, is not combined with subsequent instrs.
---
---
+--
+--
Branch delay slot scheduling rules:
-- A CTI couple (two back-to-back CTI instructions in the dynamic stream)
static const CPUResource FPMIssueSlots( "FP Instr Slot 2", 1);
// IEUN instructions can use either Alu and should use IAluN.
-// IEU0 instructions must use Alu 1 and should use both IAluN and IAlu0.
-// IEU1 instructions must use Alu 2 and should use both IAluN and IAlu1.
+// IEU0 instructions must use Alu 1 and should use both IAluN and IAlu0.
+// IEU1 instructions must use Alu 2 and should use both IAluN and IAlu1.
static const CPUResource IAluN("Int ALU 1or2", 2);
static const CPUResource IAlu0("Int ALU 1", 1);
static const CPUResource IAlu1("Int ALU 2", 1);
//---------------------------------------------------------------------------
// const InstrClassRUsage SparcV9RUsageDesc[]
-//
+//
// Purpose:
// Resource usage information for instruction in each scheduling class.
// The InstrRUsage Objects for individual classes are specified first.
static const InstrClassRUsage NoneClassRUsage = {
SPARC_NONE,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 4,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 4,
/* feasibleSlots[] */ { 0, 1, 2, 3 },
-
+
/*numEntries*/ 0,
/* V[] */ {
/*Cycle G */
static const InstrClassRUsage IEUNClassRUsage = {
SPARC_IEUN,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 3,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 3,
/* feasibleSlots[] */ { 0, 1, 2 },
-
+
/*numEntries*/ 4,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
static const InstrClassRUsage IEU0ClassRUsage = {
SPARC_IEU0,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 3,
/* feasibleSlots[] */ { 0, 1, 2 },
-
+
/*numEntries*/ 5,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
static const InstrClassRUsage IEU1ClassRUsage = {
SPARC_IEU1,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 3,
/* feasibleSlots[] */ { 0, 1, 2 },
-
+
/*numEntries*/ 5,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
static const InstrClassRUsage FPMClassRUsage = {
SPARC_FPM,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 4,
/* feasibleSlots[] */ { 0, 1, 2, 3 },
-
+
/*numEntries*/ 7,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
static const InstrClassRUsage FPAClassRUsage = {
SPARC_FPA,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 4,
/* feasibleSlots[] */ { 0, 1, 2, 3 },
-
+
/*numEntries*/ 7,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
static const InstrClassRUsage LDClassRUsage = {
SPARC_LD,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 3,
/* feasibleSlots[] */ { 0, 1, 2, },
-
+
/*numEntries*/ 6,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
static const InstrClassRUsage STClassRUsage = {
SPARC_ST,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 3,
/* feasibleSlots[] */ { 0, 1, 2 },
-
+
/*numEntries*/ 4,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
static const InstrClassRUsage CTIClassRUsage = {
SPARC_CTI,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 4,
/* feasibleSlots[] */ { 0, 1, 2, 3 },
-
+
/*numEntries*/ 4,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
{ CTIIssueSlots.rid, 0, 1 },
/*Cycle E */ { IAlu0.rid, 1, 1 },
/*Cycles E-C */ { CTIDelayCycle.rid, 1, 2 }
- /*Cycle C */
+ /*Cycle C */
/*Cycle N1*/
/*Cycle N1*/
/*Cycle N1*/
static const InstrClassRUsage SingleClassRUsage = {
SPARC_SINGLE,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ true,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 1,
/* feasibleSlots[] */ { 0 },
-
+
/*numEntries*/ 5,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
//---------------------------------------------------------------------------
// const InstrIssueDelta SparcV9InstrIssueDeltas[]
-//
+//
// Purpose:
// Changes to issue restrictions information in InstrClassRUsage for
// instructions that differ from other instructions in their class.
//{ V9::RETRY, true, true, 0 },
//{ V9::TCC, true, true, 0 },
//{ V9::SHUTDOWN, true, true, 0 },
-
+
// Special cases for breaking group *before*
// CURRENTLY NOT SUPPORTED!
{ V9::CALL, false, false, 0 },
{ V9::JMPLCALLi, false, false, 0 },
{ V9::JMPLRETr, false, false, 0 },
{ V9::JMPLRETi, false, false, 0 },
-
+
// Special cases for breaking the group *after*
{ V9::MULXr, true, true, (4+34)/2 },
{ V9::MULXi, true, true, (4+34)/2 },
{ V9::FSQRTD, false, true, 0 },
{ V9::FSQRTQ, false, true, 0 },
//{ V9::FCMP{LE,GT,NE,EQ}, false, true, 0 },
-
+
// Instructions that introduce bubbles
//{ V9::MULScc, true, true, 2 },
//{ V9::SMULcc, true, true, (4+18)/2 },
//---------------------------------------------------------------------------
// const InstrRUsageDelta SparcV9InstrUsageDeltas[]
-//
+//
// Purpose:
// Changes to resource usage information in InstrClassRUsage for
// instructions that differ from other instructions in their class.
// MachineOpCode, Resource, Start cycle, Num cycles
- //
+ //
// JMPL counts as a load/store instruction for issue!
//
{ V9::JMPLCALLr, LSIssueSlots.rid, 0, 1 },
{ V9::JMPLCALLi, LSIssueSlots.rid, 0, 1 },
{ V9::JMPLRETr, LSIssueSlots.rid, 0, 1 },
{ V9::JMPLRETi, LSIssueSlots.rid, 0, 1 },
-
- //
+
+ //
// Many instructions cannot issue for the next 2 cycles after an FCMP
// We model that with a fake resource FCMPDelayCycle.
- //
+ //
{ V9::FCMPS, FCMPDelayCycle.rid, 1, 3 },
{ V9::FCMPD, FCMPDelayCycle.rid, 1, 3 },
{ V9::FCMPQ, FCMPDelayCycle.rid, 1, 3 },
-
+
{ V9::MULXr, FCMPDelayCycle.rid, 1, 1 },
{ V9::MULXi, FCMPDelayCycle.rid, 1, 1 },
{ V9::SDIVXr, FCMPDelayCycle.rid, 1, 1 },
{ V9::FMOVRSNZ, FCMPDelayCycle.rid, 1, 1 },
{ V9::FMOVRSGZ, FCMPDelayCycle.rid, 1, 1 },
{ V9::FMOVRSGEZ,FCMPDelayCycle.rid, 1, 1 },
-
- //
+
+ //
// Some instructions are stalled in the GROUP stage if a CTI is in
// the E or C stage. We model that with a fake resource CTIDelayCycle.
- //
+ //
{ V9::LDDFr, CTIDelayCycle.rid, 1, 1 },
{ V9::LDDFi, CTIDelayCycle.rid, 1, 1 },
//{ V9::LDDA, CTIDelayCycle.rid, 1, 1 },
//{ V9::CASA, CTIDelayCycle.rid, 1, 1 },
//{ V9::CASX, CTIDelayCycle.rid, 1, 1 },
//{ V9::CASXA, CTIDelayCycle.rid, 1, 1 },
-
+
//
// Signed int loads of less than dword size return data in cycle N1 (not C)
// and put all loads in consecutive cycles into delayed load return mode.
{ V9::LDSBr, LdReturn.rid, 3, 1 },
{ V9::LDSBi, LdReturn.rid, 2, -1 },
{ V9::LDSBi, LdReturn.rid, 3, 1 },
-
+
{ V9::LDSHr, LdReturn.rid, 2, -1 },
{ V9::LDSHr, LdReturn.rid, 3, 1 },
{ V9::LDSHi, LdReturn.rid, 2, -1 },
{ V9::LDSHi, LdReturn.rid, 3, 1 },
-
+
{ V9::LDSWr, LdReturn.rid, 2, -1 },
{ V9::LDSWr, LdReturn.rid, 3, 1 },
{ V9::LDSWi, LdReturn.rid, 2, -1 },
// Together with their single-issue requirement, this means all four issue
// slots are effectively blocked for those cycles, plus the issue cycle.
// This does not increase the latency of the instruction itself.
- //
+ //
{ V9::RDCCR, AllIssueSlots.rid, 0, 5 },
{ V9::RDCCR, AllIssueSlots.rid, 0, 5 },
{ V9::RDCCR, AllIssueSlots.rid, 0, 5 },
#undef EXPLICIT_BUBBLES_NEEDED
#ifdef EXPLICIT_BUBBLES_NEEDED
- //
+ //
// MULScc inserts one bubble.
// This means it breaks the current group (captured in UltraSparcV9SchedInfo)
// *and occupies all issue slots for the next cycle
- //
+ //
//{ V9::MULScc, AllIssueSlots.rid, 2, 2-1 },
//{ V9::MULScc, AllIssueSlots.rid, 2, 2-1 },
//{ V9::MULScc, AllIssueSlots.rid, 2, 2-1 },
//{ V9::MULScc, AllIssueSlots.rid, 2, 2-1 },
-
- //
+
+ //
// SMULcc inserts between 4 and 18 bubbles, depending on #leading 0s in rs1.
// We just model this with a simple average.
- //
+ //
//{ V9::SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
//{ V9::SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
//{ V9::SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
//{ V9::SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
-
+
// SMULcc inserts between 4 and 19 bubbles, depending on #leading 0s in rs1.
//{ V9::UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
//{ V9::UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
//{ V9::UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
//{ V9::UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
-
- //
+
+ //
// MULX inserts between 4 and 34 bubbles, depending on #leading 0s in rs1.
- //
+ //
{ V9::MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
{ V9::MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
{ V9::MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
{ V9::MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
-
- //
+
+ //
// SDIVcc inserts 36 bubbles.
- //
+ //
//{ V9::SDIVcc, AllIssueSlots.rid, 2, 36-1 },
//{ V9::SDIVcc, AllIssueSlots.rid, 2, 36-1 },
//{ V9::SDIVcc, AllIssueSlots.rid, 2, 36-1 },
//{ V9::SDIVcc, AllIssueSlots.rid, 2, 36-1 },
-
+
// UDIVcc inserts 37 bubbles.
//{ V9::UDIVcc, AllIssueSlots.rid, 2, 37-1 },
//{ V9::UDIVcc, AllIssueSlots.rid, 2, 37-1 },
//{ V9::UDIVcc, AllIssueSlots.rid, 2, 37-1 },
//{ V9::UDIVcc, AllIssueSlots.rid, 2, 37-1 },
-
- //
+
+ //
// SDIVX inserts 68 bubbles.
- //
+ //
{ V9::SDIVX, AllIssueSlots.rid, 2, 68-1 },
{ V9::SDIVX, AllIssueSlots.rid, 2, 68-1 },
{ V9::SDIVX, AllIssueSlots.rid, 2, 68-1 },
{ V9::SDIVX, AllIssueSlots.rid, 2, 68-1 },
-
- //
+
+ //
// UDIVX inserts 68 bubbles.
- //
+ //
{ V9::UDIVX, AllIssueSlots.rid, 2, 68-1 },
{ V9::UDIVX, AllIssueSlots.rid, 2, 68-1 },
{ V9::UDIVX, AllIssueSlots.rid, 2, 68-1 },
{ V9::UDIVX, AllIssueSlots.rid, 2, 68-1 },
-
- //
+
+ //
// WR inserts 4 bubbles.
- //
+ //
//{ V9::WR, AllIssueSlots.rid, 2, 68-1 },
//{ V9::WR, AllIssueSlots.rid, 2, 68-1 },
//{ V9::WR, AllIssueSlots.rid, 2, 68-1 },
//{ V9::WR, AllIssueSlots.rid, 2, 68-1 },
-
- //
+
+ //
// WRPR inserts 4 bubbles.
- //
+ //
//{ V9::WRPR, AllIssueSlots.rid, 2, 68-1 },
//{ V9::WRPR, AllIssueSlots.rid, 2, 68-1 },
//{ V9::WRPR, AllIssueSlots.rid, 2, 68-1 },
//{ V9::WRPR, AllIssueSlots.rid, 2, 68-1 },
-
- //
+
+ //
// DONE inserts 9 bubbles.
- //
+ //
//{ V9::DONE, AllIssueSlots.rid, 2, 9-1 },
//{ V9::DONE, AllIssueSlots.rid, 2, 9-1 },
//{ V9::DONE, AllIssueSlots.rid, 2, 9-1 },
//{ V9::DONE, AllIssueSlots.rid, 2, 9-1 },
-
- //
+
+ //
// RETRY inserts 9 bubbles.
- //
+ //
//{ V9::RETRY, AllIssueSlots.rid, 2, 9-1 },
//{ V9::RETRY, AllIssueSlots.rid, 2, 9-1 },
//{ V9::RETRY, AllIssueSlots.rid, 2, 9-1 },
// branch. The group will stall until the load returns.
//11. Single-prec. FP loads lock 2 registers, for dependency checking.
//
-//
+//
// Additional delays we cannot or will not capture:
// 1. If DCTI is last word of cache line, it is delayed until next line can be
// fetched. Also, other DCTI alignment-related delays (pg 352)
//---------------------------------------------------------------------------
-// class SparcV9SchedInfo
-//
+// class SparcV9SchedInfo
+//
// Purpose:
// Scheduling information for the UltraSPARC.
// Primarily just initializes machine-dependent parameters in
{
maxNumIssueTotal = 4;
longestIssueConflict = 0; // computed from issuesGaps[]
-
+
// must be called after above parameters are initialized.
initializeResources();
}
{
// Compute TargetSchedInfo::instrRUsages and TargetSchedInfo::issueGaps
TargetSchedInfo::initializeResources();
-
+
// Machine-dependent fixups go here. None for now.
}
//===- SparcV9StackSlots.cpp - Add empty stack slots to functions ---------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This pass adds 2 empty slots at the top of function stack. These two slots
const TargetMachine &Target;
public:
StackSlots(const TargetMachine &T) : Target(T) {}
-
+
const char *getPassName() const {
return "Stack Slot Insertion for profiling code";
}
-
+
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
}
-
+
bool runOnMachineFunction(MachineFunction &MF) {
const Type *PtrInt = PointerType::get(Type::IntTy);
unsigned Size = Target.getTargetData().getTypeSize(PtrInt);
-
+
Value *V = Constant::getNullValue(Type::IntTy);
MF.getInfo<SparcV9FunctionInfo>()->allocateLocalVar(V, 2*Size);
return true;
//===-- SparcV9TargetMachine.cpp - SparcV9 Target Machine Implementation --===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// Primary interface to machine description for the UltraSPARC. Primarily just
// initializes machine-dependent parameters in class TargetMachine, and creates
// machine-dependent subclasses for classes such as TargetInstrInfo.
-//
+//
//===----------------------------------------------------------------------===//
#include "llvm/Function.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetMachineRegistry.h"
#include "llvm/Transforms/Scalar.h"
-#include "MappingInfo.h"
+#include "MappingInfo.h"
#include "MachineFunctionInfo.h"
#include "MachineCodeForInstruction.h"
#include "SparcV9Internals.h"
cl::init(false),
cl::desc("Emit LLVM-to-MachineCode mapping info to assembly"));
- cl::opt<bool> EnableModSched("enable-modsched",
+ cl::opt<bool> EnableModSched("enable-modsched",
cl::desc("Enable modulo scheduling pass instead of local scheduling"), cl::Hidden);
// Register the target.
TargetMachine &Target;
public:
ConstructMachineFunction(TargetMachine &T) : Target(T) {}
-
+
const char *getPassName() const {
return "ConstructMachineFunction";
}
-
+
bool runOnFunction(Function &F) {
MachineFunction::construct(&F, Target).getInfo<SparcV9FunctionInfo>()->CalculateArgSize();
return false;
struct DestroyMachineFunction : public FunctionPass {
const char *getPassName() const { return "DestroyMachineFunction"; }
-
+
static void freeMachineCode(Instruction &I) {
MachineCodeForInstruction::destroy(&I);
}
-
+
bool runOnFunction(Function &F) {
for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
for (BasicBlock::iterator I = FI->begin(), E = FI->end(); I != E; ++I)
MachineCodeForInstruction::get(I).dropAllReferences();
-
+
for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
for_each(FI->begin(), FI->end(), freeMachineCode);
-
+
MachineFunction::destruct(&F);
return false;
}
};
-
+
FunctionPass *createMachineCodeConstructionPass(TargetMachine &Target) {
return new ConstructMachineFunction(Target);
}
// Replace malloc and free instructions with library calls.
PM.add(createLowerAllocationsPass());
-
+
// FIXME: implement the switch instruction in the instruction selector.
PM.add(createLowerSwitchPass());
// FIXME: implement the invoke/unwind instructions!
PM.add(createLowerInvokePass());
-
+
// decompose multi-dimensional array references into single-dim refs
PM.add(createDecomposeMultiDimRefsPass());
// Insert empty stackslots in the stack frame of each function
// so %fp+offset-8 and %fp+offset-16 are empty slots now!
PM.add(createStackSlotsPass(*this));
-
+
PM.add(createSparcV9BurgInstSelector(*this));
if (!DisableSched)
//Use ModuloScheduling if enabled, otherwise use local scheduling if not disabled.
if(EnableModSched)
PM.add(createModuloSchedulingPass(*this));
-
+
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(&std::cerr, "Before reg alloc:\n"));
// Emit bytecode to the assembly file into its special section next
if (EmitMappingInfo)
PM.add(createBytecodeAsmPrinterPass(Out));
-
+
return false;
}
// Replace malloc and free instructions with library calls.
PM.add(createLowerAllocationsPass());
-
+
// FIXME: implement the switch instruction in the instruction selector.
PM.add(createLowerSwitchPass());
// FIXME: implement the invoke/unwind instructions!
PM.add(createLowerInvokePass());
-
+
// decompose multi-dimensional array references into single-dim refs
PM.add(createDecomposeMultiDimRefsPass());
//===-- SparcV9TargetMachine.h - Define TargetMachine for SparcV9 -*- C++ -*-=//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file declares the top-level SparcV9 target machine.
//
//===----------------------------------------------------------------------===//
SparcV9JITInfo jitInfo;
public:
SparcV9TargetMachine(const Module &M, IntrinsicLowering *IL);
-
+
virtual const TargetInstrInfo *getInstrInfo() const { return &instrInfo; }
virtual const TargetSchedInfo *getSchedInfo() const { return &schedInfo; }
virtual const SparcV9RegInfo *getRegInfo() const { return ®Info; }
//===- SparcV9TmpInstr.cpp - SparcV9 Intermediate Value class -------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Methods of class for temporary intermediate values used within the current
//===-- SparcV9TmpInstr.h ---------------------------------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Definition of class for temporary intermediate values used within the current
/// TmpInstruction - This class represents temporary intermediate
/// values used within the SparcV9 machine code for an LLVM instruction.
-///
+///
class TmpInstruction : public Instruction {
Use Ops[2];
TmpInstruction(const TmpInstruction &TI);
// s1 must be a valid value. s2 may be NULL.
TmpInstruction(MachineCodeForInstruction &mcfi,
Value *s1, Value *s2 = 0, const std::string &name = "");
-
+
// Constructor that uses the type of S1 as the type of the temporary,
// but does not require a MachineCodeForInstruction.
// s1 must be a valid value. s2 may be NULL.
TmpInstruction(MachineCodeForInstruction& mcfi,
const Type *Ty, Value *s1 = 0, Value* s2 = 0,
const std::string &name = "");
-
+
virtual Instruction *clone() const {
assert(0 && "Cannot clone TmpInstructions!");
return 0;
}
virtual const char *getOpcodeName() const { return "TmpInstruction"; }
-
+
// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const TmpInstruction *) { return true; }
static inline bool classof(const Instruction *I) {
projects / oota-llvm.git / commitdiff