Don't form PPC CTR loops for over-sized exit counts

Although you can't generate this from C on PPC64, if you have a loop using a
64-bit counter on PPC32 then you can't form a CTR-based loop for it. This had
been cauing the PPCCTRLoops pass to assert.

Thanks to Joerg Sonnenberger for providing a test case!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185361 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCCTRLoops.cpp b/lib/Target/PowerPC/PPCCTRLoops.cpp
index 08247c289f38bbe3bc2af26d3bcbea521759e25f..bfc949521be4c6d885f06b1f1ad12ed3c49e2b86 100644 (file)
--- a/lib/Target/PowerPC/PPCCTRLoops.cpp
+++ b/lib/Target/PowerPC/PPCCTRLoops.cpp
@@ -415,6 +415,9 @@ bool PPCCTRLoops::convertToCTRLoop(Loop *L) {
     } else if (!SE->isLoopInvariant(EC, L))
       continue;
 
+    if (SE->getTypeSizeInBits(EC->getType()) > (TT.isArch64Bit() ? 64 : 32))
+      continue;
+
     // We now have a loop-invariant count of loop iterations (which is not the
     // constant zero) for which we know that this loop will not exit via this
     // exisiting block.

diff --git a/test/CodeGen/PowerPC/ctrloop-large-ec.ll b/test/CodeGen/PowerPC/ctrloop-large-ec.ll
new file mode 100644 (file)
index 0000000..c18bdab
--- /dev/null
+++ b/test/CodeGen/PowerPC/ctrloop-large-ec.ll
@@ -0,0 +1,23 @@
+; RUN: llc -mcpu=ppc32 < %s
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"
+target triple = "powerpc-unknown-linux-gnu"
+
+define void @fn1() {
+entry:
+  br i1 undef, label %for.end, label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %inc3 = phi i64 [ %inc, %for.body ], [ undef, %entry ]
+  %inc = add nsw i64 %inc3, 1
+  %tobool = icmp eq i64 %inc, 0
+  br i1 %tobool, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+; On PPC32, CTR is also 32 bits, and so cannot hold a 64-bit count.
+; CHECK: @fn1
+; CHECK-NOT: mtctr
+; CHECK: blr
+