#endif
};
+/*****************************************************************************************
+ * extern gpio devices
+ *author: xxx
+ *****************************************************************************************/
+#if defined (CONFIG_GPIO_PCA9554)
+struct rk2818_gpio_expander_info extern_gpio_settinginfo[] = {
+ {
+ .gpio_num =RK2818_PIN_PI0,
+ .pin_type = GPIO_IN,
+ //.pin_value =GPIO_HIGH,
+ },
+
+ {
+ .gpio_num =RK2818_PIN_PI4,// tp3
+ .pin_type = GPIO_IN,
+ //.pin_value =GPIO_HIGH,
+ },
+
+ {
+ .gpio_num =RK2818_PIN_PI5,//tp4
+ .pin_type = GPIO_IN,
+ //.pin_value =GPIO_HIGH,
+ },
+ {
+ .gpio_num =RK2818_PIN_PI6,//tp2
+ .pin_type = GPIO_OUT,
+ //.pin_value =GPIO_HIGH,
+ },
+ {
+ .gpio_num =RK2818_PIN_PI7,//tp1
+ .pin_type = GPIO_OUT,
+ .pin_value =GPIO_HIGH,
+ },
+
+
+
+};
+
+struct pca9554_platform_data rk2818_pca9554_data={
+ .gpio_base=GPIOS_EXPANDER_BASE,
+ .gpio_pin_num=CONFIG_EXPANDED_GPIO_NUM,
+ .gpio_irq_start=NR_AIC_IRQS + 2*NUM_GROUP,
+ .irq_pin_num=CONFIG_EXPANDED_GPIO_IRQ_NUM,
+ .pca9954_irq_pin=RK2818_PIN_PE2,
+ .settinginfo=extern_gpio_settinginfo,
+ .settinginfolen=ARRAY_SIZE(extern_gpio_settinginfo),
+ .names="pca9554",
+};
+#endif
/*****************************************************************************************
* I2C devices
.addr = 0x2b,
.flags = 0,
},
+#endif
+#if defined (CONFIG_GPIO_PCA9554)
+ {
+ .type = "extend_gpio_pca9554",
+ .addr = 0x3c,
+ .flags = 0,
+ .platform_data=&rk2818_pca9554_data.gpio_base,
+ },
#endif
{}
};
#define PIN_BASE 0//¶¨ÒåRK2818ÄÚ²¿GPIOµÄµÚÒ»¸öPIN¿Ú(¼´GPIO0_A0)ÔÚgpio_descÊý×éµÄµØÖ·
#define NUM_GROUP 8// ¶¨ÒåRK2818ÄÚ²¿GPIOÿһ×é×î´óµÄPINÊýÄ¿£¬ÏÖÔÚ¶¨Îª8¸ö£¬¼´GPIOX_Y0~ GPIOX_Y7(ÆäÖÐX=0/1;Y=A/B/C/D)
#define MAX_GPIO_BANKS 8//¶¨ÒåRK2818ÄÚ²¿GPIO×ܹ²Óм¸×飬ÏÖÔÚ¶¨Îª8×飬¼´GPIO0_A~ GPIO0_D£¬GPIO1_A~ GPIO1_D¡£
+#define GPIOS_EXPANDER_BASE (PIN_BASE+NUM_GROUP*MAX_GPIO_BANKS)
//¶¨ÒåGPIOµÄPIN¿Ú×î´óÊýÄ¿¡£(NUM_GROUP*MAX_GPIO_BANKS)±íʾRK2818µÄÄÚ²¿GPIOµÄPIN¿Ú×î´óÊýÄ¿£»CONFIG_ARCH_EXTEND_GPIOS±íʾÀ©Õ¹IOµÄ×î´óÊýÄ¿¡£
-#define ARCH_NR_GPIOS (NUM_GROUP*MAX_GPIO_BANKS) + CONFIG_ARCH_EXTEND_GPIOS
+#define ARCH_NR_GPIOS (NUM_GROUP*MAX_GPIO_BANKS) + CONFIG_EXPANDED_GPIO_NUM
typedef enum eGPIOPinLevel
{
GPIO_LOW=0,
#define RK2818_PIN_PH5 (PIN_BASE + 7*NUM_GROUP + 5)
#define RK2818_PIN_PH6 (PIN_BASE + 7*NUM_GROUP + 6)
#define RK2818_PIN_PH7 (PIN_BASE + 7*NUM_GROUP + 7)
-
+/***********************define extern gpio pin num******************************/
+#define RK2818_PIN_PI0 (GPIOS_EXPANDER_BASE + 0)
+#define RK2818_PIN_PI1 (GPIOS_EXPANDER_BASE +1)
+#define RK2818_PIN_PI2 (GPIOS_EXPANDER_BASE +2)
+#define RK2818_PIN_PI3 (GPIOS_EXPANDER_BASE +3)
+#define RK2818_PIN_PI4 (GPIOS_EXPANDER_BASE +4)
+#define RK2818_PIN_PI5 (GPIOS_EXPANDER_BASE +5)
+#define RK2818_PIN_PI6 (GPIOS_EXPANDER_BASE +6)
+#define RK2818_PIN_PI7 (GPIOS_EXPANDER_BASE +7)
#ifndef __ASSEMBLY__
extern void __init rk2818_gpio_init(struct rk2818_gpio_bank *data, int nr_banks);
extern void __init rk2818_gpio_irq_setup(void);
static inline int irq_to_gpio(unsigned irq)
{
- if((irq - __gpio_to_irq(RK2818_PIN_PA0)) < NUM_GROUP)
+ if(irq<NR_AIC_IRQS)
+ return -ENXIO;
+
+ if((irq - __gpio_to_irq(RK2818_PIN_PA0)) < NUM_GROUP)
{
return (RK2818_PIN_PA0 + (irq - __gpio_to_irq(RK2818_PIN_PA0)));
}
{
return (RK2818_PIN_PE0 + (irq - __gpio_to_irq(RK2818_PIN_PE0)));
}
+ else if((irq - __gpio_to_irq(RK2818_PIN_PA0)) <3*NUM_GROUP)
+ {
+ return (RK2818_PIN_PI0 + (irq - __gpio_to_irq(RK2818_PIN_PI0)));
+ }
else
{
return -ENXIO;
CONFIG_RK28_GPIO_IRQ±íʾRK2818µÄGPIO¸´ÓõÄ×î´óÖжÏÊýÄ¿£¬CONFIG_EXTEND_GPIO_IRQ±íʾRK2818µÄ
À©Õ¹IO¸´ÓõÄ×î´óÖжÏÊýÄ¿¡£*/
#define NR_AIC_IRQS 48
-#define NR_IRQS (NR_AIC_IRQS + CONFIG_RK28_GPIO_IRQ + CONFIG_EXTEND_GPIO_IRQ)
+#define NR_IRQS (NR_AIC_IRQS + CONFIG_RK28_GPIO_IRQ + CONFIG_EXPANDED_GPIO_IRQ_NUM)
/*irq number*/