status = "disabled";
};
+ vpu: vpu_service@ff9a0000 {
+ compatible = "rockchip,vpu_service";
+ rockchip,grf = <&grf>;
+ iommu_enabled = <1>;
+ reg = <0x0 0xff9a0000 0x0 0x800>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_dec", "irq_enc";
+ clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
+ reset-names = "video_h", "video_a";
+ name = "vpu_service";
+ dev_mode = <0>;
+ status = "disabled";
+ };
+
+ rkvdec: rkvdec@ff9b0000 {
+ compatible = "rockchip,rkvdec";
+ rockchip,grf = <&grf>;
+ iommu_enabled = <1>;
+ reg = <0x0 0xff9b0000 0x0 0x400>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_dec";
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
+ resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
+ reset-names = "video_h", "video_a";
+ dev_mode = <2>;
+ name = "rkvdec";
+ status = "disabled";
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3366-pinctrl";
rockchip,grf = <&grf>;