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For VLDM/VSTM (Advanced SIMD), set encoding bits Inst{11-8} to 0b1011.
author
Johnny Chen
<johnny.chen@apple.com>
Tue, 1 Dec 2009 17:37:06 +0000
(17:37 +0000)
committer
Johnny Chen
<johnny.chen@apple.com>
Tue, 1 Dec 2009 17:37:06 +0000
(17:37 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90243
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/ARM/ARMInstrNEON.td
patch
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diff --git
a/lib/Target/ARM/ARMInstrNEON.td
b/lib/Target/ARM/ARMInstrNEON.td
index 3166931325d2d783534a3699aa8ab563d3801342..61b770560b3a84f09d580b7536535b705f442fd5 100644
(file)
--- a/
lib/Target/ARM/ARMInstrNEON.td
+++ b/
lib/Target/ARM/ARMInstrNEON.td
@@
-152,7
+152,7
@@
def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
let Inst{24} = 0; // P bit
let Inst{23} = 1; // U bit
let Inst{20} = 1;
- let Inst{11-
9} = 0b10
1;
+ let Inst{11-
8} = 0b101
1;
}
// Use vstmia to store a Q register as a D register pair.
@@
-164,7
+164,7
@@
def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
let Inst{24} = 0; // P bit
let Inst{23} = 1; // U bit
let Inst{20} = 0;
- let Inst{11-
9} = 0b10
1;
+ let Inst{11-
8} = 0b101
1;
}
// VLD1 : Vector Load (multiple single elements)