rk29: add dynamic DDR reconfiguration support, default disabled

diff --git a/arch/arm/mach-rk29/Kconfig b/arch/arm/mach-rk29/Kconfig
index f5c49882514addd5a2a83f7047896f0d70b44b0a..0892d4c42f0b2e9bfe01ac42878c6a76ba0c3c16 100755 (executable)
--- a/arch/arm/mach-rk29/Kconfig
+++ b/arch/arm/mach-rk29/Kconfig
@@ -150,6 +150,9 @@ config DDR_SDRAM_FREQ
        int "DDR SDRAM frequence (in MHz)"
        default 400
 
+config DDR_RECONFIG
+       bool "Enable dynamic DDR reconfiguration (EXPERIMENTAL)"
+
 config WIFI_CONTROL_FUNC
         bool "Enable WiFi control function abstraction"
         help

diff --git a/arch/arm/mach-rk29/clock.c b/arch/arm/mach-rk29/clock.c
index 105ad5d0761f79e2f874b2712743f5979b341338..2a8838a3f459f48bcb04ce8cd660a12ef42ddc7f 100755 (executable)
--- a/arch/arm/mach-rk29/clock.c
+++ b/arch/arm/mach-rk29/clock.c
@@ -209,6 +209,7 @@ volatile u32 cru_clkgate3_con_mirror;
 
 static int gate_mode(struct clk *clk, int on)
 {
+       unsigned long flags;
        u32 reg;
        int idx = clk->gate_idx;
        u32 v;
@@ -220,6 +221,9 @@ static int gate_mode(struct clk *clk, int on)
        reg += (idx >> 5) << 2;
        idx &= 0x1F;
 
+       /* ddr reconfig may change gate */
+       local_irq_save(flags);
+
        if (reg == CRU_CLKGATE3_CON)
                v = cru_clkgate3_con_mirror;
        else
@@ -234,6 +238,7 @@ static int gate_mode(struct clk *clk, int on)
                cru_clkgate3_con_mirror = v;
        cru_writel(v, reg);
 
+       local_irq_restore(flags);
        return 0;
 }
 

diff --git a/arch/arm/mach-rk29/ddr.c b/arch/arm/mach-rk29/ddr.c
index 3bd26953b9686900e8b6b44fb0894101562b74a9..d665fa909a68cbf12d6b9d9c3a062175a4d8b3ed 100755 (executable)
--- a/arch/arm/mach-rk29/ddr.c
+++ b/arch/arm/mach-rk29/ddr.c
@@ -1490,264 +1490,7 @@ int ddr_init(uint32_t dram_type, uint32_t freq)
 EXPORT_SYMBOL(ddr_init);
 
 //core_initcall_sync(ddr_probe);
-#if 0
-int test =0;
-extern void local_flush_tlb_all(void);
-void __sramlocalfunc ddrReg_Save(void)
-{
-    int i=0;
-//    pDDR_REG_T pDDR_Reg=((pDDR_REG_T)RK29_DDRC_BASE);
-    for(i =0; i<0x30; i++)
-        ddrreg[i] =*(unsigned long volatile *)(RK29_DDRC_BASE +i*4);
-    ddrreg[i++] =*(unsigned long volatile *)(RK29_DDRC_BASE +0x7c*4); //pDDR_Reg->MR;
-    ddrreg[i++] =*(unsigned long volatile *)(RK29_DDRC_BASE +0x7d*4);
-    ddrreg[i++] =*(unsigned long volatile *)(RK29_DDRC_BASE +0x7e*4);
-    ddrreg[i++] =*(unsigned long volatile *)(RK29_DDRC_BASE +0x7f*4);
-    //rest reg did not saved yet
-}
-void __sramlocalfunc ddrReg_Restore(void)
-{
-    int i=0;
-//    pDDR_REG_T pDDR_Reg=((pDDR_REG_T)RK29_DDRC_BASE);
-    for(i =0; i<0x30; i++)
-        *(unsigned long volatile *)(RK29_DDRC_BASE +i*4) =ddrreg[i];
-     *(unsigned long volatile *)(RK29_DDRC_BASE +0x7c*4) =ddrreg[i++];
-     *(unsigned long volatile *)(RK29_DDRC_BASE +0x7d*4) =ddrreg[i++];
-     *(unsigned long volatile *)(RK29_DDRC_BASE +0x7e*4) =ddrreg[i++];
-     *(unsigned long volatile *)(RK29_DDRC_BASE +0x7f*4) =ddrreg[i++];
-    //rest reg did not saved yet
-}
-void __sramlocalfunc Delay10cyc(int count)
-{
-    volatile int i;
-
-    while(count--)
-    {
-        for (i=0; i<8; i++);    //12*8+8=104cyc
-    }
-}
-
-void __sramlocalfunc __ddr_reconfig(int mode)
-{
-    int i, n, bakdatr;
-    volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
-
-        __cpuc_flush_kern_all();
-        __cpuc_flush_user_all();
-        local_flush_tlb_all();
-        n=temp[0];
-        barrier();
-        n=temp[1024];
-        barrier();
-        n=temp[1024*2];
-        barrier();
-        n=temp[1024*3];
-        barrier();
-        n= pSCU_Reg->CRU_SOFTRST_CON[0];
-        
-        dsb();
 
-        n= *(unsigned long volatile *)(0xf50080d8);
-        
-        
-        pDDR_Reg->DCR = (pDDR_Reg->DCR & (~((0x1<<24) | (0x1<<13) | (0xF<<27) | (0x1<<31)))) | ((0x1<<13) | (0x2<<27) | (0x1<<31));  //enter Self Refresh
-        
-#if 1
-        //DO_INT Must be cleared before ddrReg_Save
-        while(pDDR_Reg->DCR &(0x1<<31)); //may done soon
-        ddrReg_Save();
-
-        pSCU_Reg->CRU_SOFTRST_CON[2] |= ((0x3<<15) | (0x3<<11) | (0x3<<8));
-        pSCU_Reg->CRU_SOFTRST_CON[0] |= (0x7f<<18);
-        Delay10cyc(100);
-        pSCU_Reg->CRU_SOFTRST_CON[2] &= ~((0x3<<15) | (0x3<<11) | (0x3<<8));
-
-        if(mode &1)
-            *(unsigned long volatile *)(0xf50080ac) =0x298;
-        else
-            *(unsigned long volatile *)(0xf50080ac) =0x246;
-        pDDR_Reg->PQCR[0] =0x0e03f000;
-        pDDR_Reg->PQCR[1] =0x0e01f000;
-        pDDR_Reg->PQCR[2] =0x0e00f000;
-        ddrReg_Restore();
-        if(mode &2)
-            pDDR_Reg->MMGCR =2;
-        else
-            pDDR_Reg->MMGCR =0;
-        pSCU_Reg->CRU_SOFTRST_CON[0]  &=~(0x7F<<18);
-        dsb();
-        Delay10cyc(200); //need 1024 cycles, worst case assume ddr @200MHZ, cpu at @1GHZ, need 5120 cycles delay
-//        if((pDDR_Reg->DRR) &0x0f000000)
-//            while(1);
-        pDDR_Reg->DCR |= DO_INIT; 
-        while((*(volatile unsigned int  *)(0xf50080b8)) & 0x1)  //wait init ok
-            Delay10cyc(1);
-        pDDR_Reg->DRR |=(1<<31);
-        Delay10cyc(10);
-        pDDR_Reg->CCR = DTT;               //ddr3 400m 4us 4*6*rank+1;
-        Delay10cyc(100);
-        while((*(volatile unsigned int  *)(0xf50080b8)) & 0x1)  //wait dtt ok
-            Delay10cyc(1);
-        if((*(volatile unsigned int  *)(0xf50080b8)) & 0x2)
-            while(1);
-        pDDR_Reg->DRR &=~(1<<31);
-        pDDR_Reg->DCR &=~DO_INIT;
-        pDDR_Reg->CCR = DFTCMP |HOSTEN;  //enable host port
-        dsb();
-#endif
-
-}
-void ddr_reconfig(int mode)
-
-{
-    int baklcdctrl;
-    int count =0;
-//    *(int *)(0xf50080d4) =1;
-    int i;
-    int gpu_suspended,currcmdbufadr;
-    asm volatile ("cpsid       if");
-    {
-        __cpuc_flush_kern_all();
-        __cpuc_flush_user_all();
-        //some risk: if a common to lcdc is going, then a read form 0xf410c0000 may retrun an old val
-        pSCU_Reg->CRU_CLKGATE_CON[3] |=(1<<3);
-        if(0)
-        {
-            *(unsigned long volatile *)(0xf410c000) |= (1<<17);
-            *(unsigned long volatile *)(0xf410c0a0) |= (1<<0);
-            delayus(1);      //
-            dsb();
-//        for(i =0; i<32; i++)
-//            Barrier[i]++;
-            dmac_flush_range((0xf410c000),(0xf410c000));
-            while(!(*(unsigned long volatile *)(0xf410c000) & (0x1<<17)))
-                delayus(1);      //
-        
-/*            for(i =0; i<30; i++)
-            {
-                *(unsigned long volatile *)(0xf410c000) |= (1<<17);
-                *(unsigned long volatile *)(0xf410c0a0) |= (1<<0);
-                delayus(1000);      //
-            }
-*/
-        }
-        gpu_suspended =0;
-        if(((0xf<<14)!=(pSCU_Reg->CRU_CLKGATE_CON[3] &(0xf<<14))) 
-            &&(*(unsigned long volatile *)(0xf4120004) !=0x7fffffff))
-        {   //clock enable and not at idle
-            gpu_suspended =1;
-            {
-                int chktime =0;
-                for(chktime =0; chktime<30; chktime++ )
-                {
-                    if(*(unsigned long volatile *)(0xf4120004) !=0x7ffffffe)
-                        chktime =0;
-                    delayus(1);      //
-                }
-            }
-            currcmdbufadr =*(int *)(0xf4120664);
-            if(*(int *)(currcmdbufadr +0x60000000) ==0x380000c8) //0x60000000 assume VA =PA +0x60000000
-                *(int *)(currcmdbufadr +0x60000000) =0x10000000;
-            else
-            {
-                currcmdbufadr -=8;
-                if(*(int *)(currcmdbufadr +0x60000000) ==0x380000c8)
-                    *(int *)(currcmdbufadr +0x60000000) =0x10000000;
-                else
-                {
-                    currcmdbufadr -=8;
-                    if(*(int *)(currcmdbufadr +0x60000000) ==0x380000c8)
-                        *(int *)(currcmdbufadr +0x60000000) =0x10000000;
-                    else
-                        while(1);
-                }
-            }
-            dmac_flush_range((currcmdbufadr +0x60000000),(currcmdbufadr +0x60000000));
-            while(*(unsigned long volatile *)(0xf4120004) !=0x7fffffff) delayus(1);      //
-        }
-
-    //status check
-        //1 IPP clock_con3[5:4](0x20000068)  INT_ST[6](0x10110010) 1 ==working
-        if(((0)==(pSCU_Reg->CRU_CLKGATE_CON[3] &(0x3<<4))) &&
-            ((0)!=(*(unsigned long volatile *)(0xf4110010) &(1<<6))))
-            while(1);
-        //2 DMA0 clock con0[10](0x2000005c) DSR[3:0](0x20180000) 0 ==stop
-        while(((0)==(pSCU_Reg->CRU_CLKGATE_CON[0] &(0x1<<10))) 
-            &&(((0)!=(*(unsigned long volatile *)(0xf5018000) &(0xf<<0))) 
-                ||((0)!=(*(unsigned long volatile *)(0xf5018100) &(0xf<<0))) 
-                    ||((0)!=(*(unsigned long volatile *)(0xf5018108) &(0xf<<0))) 
-                        ||((0)!=(*(unsigned long volatile *)(0xf5018110) &(0xf<<0))) 
-                            ||((0)!=(*(unsigned long volatile *)(0xf5018118) &(0xf<<0)))))
-            /*while(1)*/;
-        //2 SDMA0 clock con0[9](0x2000005c) DSR[3:0](0x201C0000) 0 ==stop
-        while(((0)==(pSCU_Reg->CRU_CLKGATE_CON[0] &(0x1<<9))) 
-            &&(((0)!=(*(unsigned long volatile *)(0xf501c000) &(0xf<<0))) 
-                ||((0)!=(*(unsigned long volatile *)(0xf501c100) &(0xf<<0))) 
-                    ||((0)!=(*(unsigned long volatile *)(0xf501c108) &(0xf<<0))) 
-                        ||((0)!=(*(unsigned long volatile *)(0xf501c110) &(0xf<<0))) 
-                            ||((0)!=(*(unsigned long volatile *)(0xf501c118) &(0xf<<0)))))
-            /*while(1)*/;
-        //2 DMA2 clock con1[5](0x20000060) DSR[3:0](0x20078000) 0 ==stop
-        while(((0)==(pSCU_Reg->CRU_CLKGATE_CON[1] &(0x1<<5))) 
-            &&(((0)!=(*(unsigned long volatile *)(0xf5078000) &(0xf<<0))) 
-                ||((0)!=(*(unsigned long volatile *)(0xf5078100) &(0xf<<0))) 
-                    ||((0)!=(*(unsigned long volatile *)(0xf5078108) &(0xf<<0))) 
-                        ||((0)!=(*(unsigned long volatile *)(0xf5078110) &(0xf<<0))) 
-                            ||((0)!=(*(unsigned long volatile *)(0xf5078118) &(0xf<<0)))))
-            /*while(1)*/;
-        //3 VIP clock con2[22,18](0x20000064) VIPCTL[0](0x10108010) 0==stop 
-        while(((0)==(pSCU_Reg->CRU_CLKGATE_CON[2] &((0x1<<18)|(0x1<<22)))) 
-            &&((0)!=(*(unsigned long volatile *)(0xf4108010) &(1<<0))) &&((1)!=(*(unsigned long volatile *)(0xf410802c) &(1<<0))))
-                //print_Dec(1);/*while(1)*/;
-                ddr_print("1");
-/*
-        //4 USB
-        if(((0)==(*(unsigned long volatile *)(0xf5000068) &(0x3<<4))) &&
-            ((0)==(*(unsigned long volatile *)(0xf4110010) &(1<<6))))
-            while(1);
-*/
-        //5 VPU when select VDPU clk VDPU clock con2[19,13:12]else con2[18,11:10] (0x20000068) wreg[1](0x10104204)  0==stop
-        //wreg24[0] 0==stop
-        {
-            int clkgatemask;
-            clkgatemask =((0x1<<18)|(0x3<<10))<<(((*(unsigned long volatile *)(0xf50080bc))>>23) &1);
-            if((0)==(pSCU_Reg->CRU_CLKGATE_CON[3] &clkgatemask))
-            while(((0)!=(*(unsigned long volatile *)(0xf4104204) &(1<<0)))
-                ||((0)!=(*(unsigned long volatile *)(0xf4104038) &(1<<0))))
-                    /*while(1)*/;
-            delayus(1);
-        }
-        while(((0xf<<14)!=(pSCU_Reg->CRU_CLKGATE_CON[3] &(0xf<<14))) &&
-            (*(unsigned long volatile *)(0xf4120004) !=0x7fffffff));
-        {
-               static unsigned long save_sp;
-
-               DDR_SAVE_SP(save_sp);
-            {
-                   __ddr_reconfig(mode);
-
-            }
-               DDR_RESTORE_SP(save_sp);
-        } //    do_ddr_reconfig(mode);
-///////////////////////////////////////////////////////////   
-        if(gpu_suspended)
-        {
-            *(int *)(currcmdbufadr +0x60000000) =0x380000c8;
-            dmac_flush_range((currcmdbufadr +0x60000000),(currcmdbufadr +0x60000000));
-            *(int *)(0xf4120654) =currcmdbufadr;
-            *(int *)(0xf4120658) =0x10002;
-            while(*(unsigned long volatile *)(0xf4120004) &1);
-        }
-    
-//    *(int *)(0xf50080d4) +=0x1;
-        count++;
-//    *(unsigned long volatile *)(0xf410c000) &= ~(1<<17);
-//    *(unsigned long volatile *)(0xf410c0a0) |= (1<<0);
-        pSCU_Reg->CRU_CLKGATE_CON[3] &=~(1<<3);
-
-//    delayus(1000);      //
-    }
-        asm volatile ("cpsie   if");
-            
-}
+#ifdef CONFIG_DDR_RECONFIG
+#include "ddr_reconfig.c"
 #endif

diff --git a/arch/arm/mach-rk29/include/mach/ddr.h b/arch/arm/mach-rk29/include/mach/ddr.h
index 25a5f514b9a31041bef691ddccaa21695f6316e7..17ba02e04c09f22f9b1819d69de631c852b1dfb0 100755 (executable)
--- a/arch/arm/mach-rk29/include/mach/ddr.h
+++ b/arch/arm/mach-rk29/include/mach/ddr.h
@@ -148,6 +148,11 @@ void __sramfunc ddr_resume(void);
 void __sramlocalfunc delayus(uint32_t us);
 uint32_t __sramfunc ddr_change_freq(uint32_t nMHz);
 int ddr_init(uint32_t dram_type, uint32_t freq);
+#ifdef CONFIG_DDR_RECONFIG
+int rk29fb_irq_notify_ddr(void);
+#else
+static inline int rk29fb_irq_notify_ddr(void) { return 0; }
+#endif
 
 
 #endif

diff --git a/arch/arm/mach-rk29/include/mach/memory.h b/arch/arm/mach-rk29/include/mach/memory.h
index da68f41527c7e675a238cfa62920ce55c2bf0e88..ec54cf72265d1a7a4239dcf3ae37ff41ebde60ec 100644 (file)
--- a/arch/arm/mach-rk29/include/mach/memory.h
+++ b/arch/arm/mach-rk29/include/mach/memory.h
@@ -49,8 +49,8 @@ __arch_adjust_zones(int node, unsigned long *zone_size, unsigned long *zhole_siz
  * SRAM memory whereabouts
  */
 #define SRAM_CODE_OFFSET       0xFEF00000
-#define SRAM_CODE_END          0xFEF01FFF
-#define SRAM_DATA_OFFSET       0xFEF02000
+#define SRAM_CODE_END          0xFEF02FFF
+#define SRAM_DATA_OFFSET       0xFEF03000
 #define SRAM_DATA_END          0xFEF03FFF
 
 #endif

diff --git a/arch/arm/mach-rk29/include/mach/rk29_iomap.h b/arch/arm/mach-rk29/include/mach/rk29_iomap.h
index ec6aaf7cb54e625454f16b1b57fb5ee483bbf828..b81c2cba6aa7b9ae09bb485b70e1b9b0d20caf6e 100755 (executable)
--- a/arch/arm/mach-rk29/include/mach/rk29_iomap.h
+++ b/arch/arm/mach-rk29/include/mach/rk29_iomap.h
@@ -34,47 +34,53 @@
  * FEF00000     0               16K     SRAM
  */
 
-#define RK29_ADDR_BASE0                                0xFEA00000
-#define RK29_ADDR_BASE1                                0xFED00000
+#define RK29_ADDR_BASE0             0xFEA00000
+#define RK29_ADDR_BASE1             0xFED00000
 
-#define RK29_SDRAM_PHYS                                0x60000000U
-#define RK29_AXI1_PHYS                         0x10000000      
-#define RK29_AXI0_PHYS                         0x1012C000                      
-#define RK29_PERI_PHYS                         0x10140000      
+#define RK29_SDRAM_PHYS             0x60000000U
+#define RK29_AXI1_PHYS              0x10000000
+#define RK29_AXI0_PHYS              0x1012C000
+#define RK29_PERI_PHYS              0x10140000
 
 //CPU system AXI 1
-#define RK29_BOOTROM_PHYS              0x10100000
-#define RK29_BOOTROM_SIZE              SZ_16K
-#define RK29_VCODEC_PHYS                       0x10104000
-#define RK29_VCODEC_SIZE                       SZ_16K
-#define RK29_VIP_PHYS                          0x10108000
-#define RK29_VIP_SIZE                          SZ_16K
-#define RK29_LCDC_PHYS                         0x1010C000
-#define RK29_LCDC_SIZE                         SZ_16K
-#define RK29_IPP_PHYS                          0x10110000
-#define RK29_IPP_SIZE                          SZ_16K
-#define RK29_EBC_PHYS                          0x10114000
-#define RK29_EBC_SIZE                          SZ_16K
-#define RK29_I2S_8CH_PHYS                      0x10118000
-#define RK29_I2S_8CH_SIZE                      SZ_16K
-#define RK29_I2S_2CH_PHYS                      0x1011C000
-#define RK29_I2S_2CH_SIZE                      SZ_8K
-#define RK29_SPDIF_PHYS                                0x1011E000
-#define RK29_SPDIF_SIZE                                SZ_8K
-#define RK29_GPU_PHYS                          0x10120000
-#define RK29_GPU_SIZE                          SZ_16K
-#define RK29_DDRC_PHYS                 0x10124000
-#define RK29_DDRC_BASE                 (RK29_ADDR_BASE0+0x124000)
-#define RK29_DDRC_SIZE                 SZ_16K
+#define RK29_BOOTROM_PHYS           0x10100000
+#define RK29_BOOTROM_SIZE           SZ_16K
+#define RK29_VCODEC_PHYS            0x10104000
+#define RK29_VCODEC_SIZE            SZ_16K
+#define RK29_VCODEC_BASE            (RK29_ADDR_BASE0+0x104000)
+#define RK29_VIP_PHYS               0x10108000
+#define RK29_VIP_SIZE               SZ_16K
+#define RK29_VIP_BASE               (RK29_ADDR_BASE0+0x108000)
+#define RK29_LCDC_PHYS              0x1010C000
+#define RK29_LCDC_SIZE              SZ_16K
+#define RK29_LCDC_BASE              (RK29_ADDR_BASE0+0x10C000)
+#define RK29_IPP_PHYS               0x10110000
+#define RK29_IPP_SIZE               SZ_16K
+#define RK29_IPP_BASE               (RK29_ADDR_BASE0+0x110000)
+#define RK29_EBC_PHYS               0x10114000
+#define RK29_EBC_SIZE               SZ_16K
+#define RK29_I2S_8CH_PHYS           0x10118000
+#define RK29_I2S_8CH_SIZE           SZ_16K
+#define RK29_I2S_2CH_PHYS           0x1011C000
+#define RK29_I2S_2CH_SIZE           SZ_8K
+#define RK29_I2S0_BASE              (RK29_ADDR_BASE0+0x11C000)
+#define RK29_SPDIF_PHYS             0x1011E000
+#define RK29_SPDIF_SIZE             SZ_8K
+#define RK29_GPU_PHYS               0x10120000
+#define RK29_GPU_SIZE               SZ_16K
+#define RK29_GPU_BASE               (RK29_ADDR_BASE0+0x120000)
+#define RK29_DDRC_PHYS              0x10124000
+#define RK29_DDRC_BASE              (RK29_ADDR_BASE0+0x124000)
+#define RK29_DDRC_SIZE              SZ_16K
 
 //CPU system AXI 0
-#define RK29_GICCPU_PHYS                       0x1012C000
-#define RK29_GICCPU_BASE                       (RK29_ADDR_BASE0+0x12C000)
-#define RK29_GICCPU_SIZE                       SZ_8K
-#define RK29_GICPERI_PHYS                      0x1012E000
-#define RK29_GICPERI_BASE                      (RK29_ADDR_BASE0+0x12E000)
-#define RK29_GICPERI_SIZE                      SZ_8K
-#define RK29_CPU_AXI_BUS0_PHYS         0x15000000
+#define RK29_GICCPU_PHYS            0x1012C000
+#define RK29_GICCPU_BASE            (RK29_ADDR_BASE0+0x12C000)
+#define RK29_GICCPU_SIZE            SZ_8K
+#define RK29_GICPERI_PHYS           0x1012E000
+#define RK29_GICPERI_BASE           (RK29_ADDR_BASE0+0x12E000)
+#define RK29_GICPERI_SIZE           SZ_8K
+#define RK29_CPU_AXI_BUS0_PHYS      0x15000000
 
 //peri system
 #define RK29_USBHOST_PHYS           0x10140000
@@ -83,120 +89,123 @@
 #define RK29_USBOTG0_SIZE           SZ_256K
 #define RK29_USBOTG1_PHYS           0x101c0000
 #define RK29_USBOTG1_SIZE           SZ_256K
-#define RK29_MAC_PHYS                          0x10204000
-#define RK29_MAC_SIZE                  SZ_16K
-#define RK29_HOSTIF_PHYS                       0x1020C000
-#define RK29_HOSTIF_SIZE               SZ_16K
-#define RK29_HSADC_PHYS                                0x10210000
-#define RK29_HSADC_SIZE                SZ_16K
-#define RK29_SDMMC0_PHYS                       0x10214000
-#define RK29_SDMMC0_SIZE               SZ_16K
-#define RK29_SDMMC1_PHYS                       0x10218000
-#define RK29_SDMMC1_SIZE               SZ_16K
-#define RK29_EMMC_PHYS                         0x1021C000
-#define RK29_EMMC_SIZE                 SZ_16K
-#define RK29_PIDF_PHYS                         0x10220000
-#define RK29_EMMC_SIZE                 SZ_16K
-#define RK29_ARBITER0_PHYS                     0x10224000
+#define RK29_MAC_PHYS               0x10204000
+#define RK29_MAC_SIZE               SZ_16K
+#define RK29_HOSTIF_PHYS            0x1020C000
+#define RK29_HOSTIF_SIZE            SZ_16K
+#define RK29_HSADC_PHYS             0x10210000
+#define RK29_HSADC_SIZE             SZ_16K
+#define RK29_SDMMC0_PHYS            0x10214000
+#define RK29_SDMMC0_SIZE            SZ_16K
+#define RK29_SDMMC1_PHYS            0x10218000
+#define RK29_SDMMC1_SIZE            SZ_16K
+#define RK29_EMMC_PHYS              0x1021C000
+#define RK29_EMMC_SIZE              SZ_16K
+#define RK29_PIDF_PHYS              0x10220000
+#define RK29_EMMC_SIZE              SZ_16K
+#define RK29_ARBITER0_PHYS          0x10224000
 #define RK29_ARBITER0_SIZE          SZ_16K
-#define RK29_ARBITER1_PHYS                     0x10228000
+#define RK29_ARBITER1_PHYS          0x10228000
 #define RK29_ARBITER1_SIZE          SZ_16K
-#define RK29_PERI_AXI_BUS0_PHYS                0x10300000
+#define RK29_PERI_AXI_BUS0_PHYS     0x10300000
 
-#define RK29_NANDC_PHYS                                0x10500000
-#define RK29_NANDC_BASE                                0xFEC00000
-#define RK29_NANDC_SIZE                                SZ_16K
+#define RK29_NANDC_PHYS             0x10500000
+#define RK29_NANDC_BASE             0xFEC00000
+#define RK29_NANDC_SIZE             SZ_16K
 
 //CPU AXI 1 APB
-#define RK29_CRU_PHYS                          0x20000000
-#define RK29_CRU_BASE                          RK29_ADDR_BASE1
-#define RK29_CRU_SIZE                          SZ_4K
-#define RK29_PMU_PHYS                  0x20004000
-#define RK29_PMU_BASE                  (RK29_ADDR_BASE1 + 0x4000)
-#define RK29_PMU_SIZE                  SZ_4K
-#define RK29_GRF_BASE                          (RK29_ADDR_BASE1+0x8000)
-#define RK29_GRF_PHYS                          0x20008000
-#define RK29_GRF_SIZE                          SZ_16K
-#define RK29_RTC_PHYS                          0x2000C000
-#define RK29_RTC_SIZE                          SZ_16K
-#define RK29_EFUSE_PHYS                0x20010000
-#define RK29_EFUSE_SIZE                                SZ_16K
-#define RK29_TZPC_PHYS                 0x20014000
-#define RK29_TZPC_SIZE                         SZ_16K
-#define RK29_SDMAC0_PHYS               0x20018000
-#define RK29_SDMAC0_SIZE                       SZ_16K
-#define RK29_DMAC0_PHYS                0x2001C000
-#define RK29_DMAC0_SIZE                                SZ_16K
-#define RK29_DEBUG_PHYS                0x20024000
-#define RK29_DEBUG_SIZE                                SZ_16K
-#define RK29_I2C0_PHYS                 0x2002C000
-#define RK29_I2C0_SIZE                         SZ_16K
-#define RK29_UART0_PHYS                0x20030000
-#define RK29_UART0_SIZE                                SZ_4K
-#define RK29_GPIO0_BASE                                (RK29_ADDR_BASE1+0x34000)
-#define RK29_GPIO0_PHYS                0x20034000
-#define RK29_GPIO0_SIZE                                SZ_16K
-#define RK29_TIMER0_BASE                       (RK29_ADDR_BASE1+0x38000)
-#define RK29_TIMER0_PHYS                       0x20038000
-#define RK29_TIMER0_SIZE                       SZ_8K
-#define RK29_TIMER1_BASE                       (RK29_ADDR_BASE1+0x3A000)
-#define RK29_TIMER1_PHYS                       0x2003A000
-#define RK29_TIMER1_SIZE                       SZ_8K
-#define RK29_GPIO4_BASE                                (RK29_ADDR_BASE1+0x3C000)
-#define RK29_GPIO4_PHYS                0x2003C000
-#define RK29_GPIO4_SIZE                                SZ_8K
-#define RK29_GPIO6_BASE                                (RK29_ADDR_BASE1+0x3E000)
-#define RK29_GPIO6_PHYS                0x2003E000
-#define RK29_GPIO6_SIZE                                SZ_8K
+#define RK29_CRU_PHYS               0x20000000
+#define RK29_CRU_BASE               RK29_ADDR_BASE1
+#define RK29_CRU_SIZE               SZ_4K
+#define RK29_PMU_PHYS               0x20004000
+#define RK29_PMU_BASE               (RK29_ADDR_BASE1 + 0x4000)
+#define RK29_PMU_SIZE               SZ_4K
+#define RK29_GRF_BASE               (RK29_ADDR_BASE1+0x8000)
+#define RK29_GRF_PHYS               0x20008000
+#define RK29_GRF_SIZE               SZ_16K
+#define RK29_RTC_PHYS               0x2000C000
+#define RK29_RTC_SIZE               SZ_16K
+#define RK29_EFUSE_PHYS             0x20010000
+#define RK29_EFUSE_SIZE             SZ_16K
+#define RK29_TZPC_PHYS              0x20014000
+#define RK29_TZPC_SIZE              SZ_16K
+#define RK29_SDMAC0_PHYS            0x20018000
+#define RK29_SDMAC0_SIZE            SZ_16K
+#define RK29_SDMAC0_BASE            (RK29_ADDR_BASE1+0x18000)
+#define RK29_DMAC0_PHYS             0x2001C000
+#define RK29_DMAC0_SIZE             SZ_16K
+#define RK29_DMAC0_BASE             (RK29_ADDR_BASE1+0x1C000)
+#define RK29_DEBUG_PHYS             0x20024000
+#define RK29_DEBUG_SIZE             SZ_16K
+#define RK29_I2C0_PHYS              0x2002C000
+#define RK29_I2C0_SIZE              SZ_16K
+#define RK29_UART0_PHYS             0x20030000
+#define RK29_UART0_SIZE             SZ_4K
+#define RK29_GPIO0_BASE             (RK29_ADDR_BASE1+0x34000)
+#define RK29_GPIO0_PHYS             0x20034000
+#define RK29_GPIO0_SIZE             SZ_16K
+#define RK29_TIMER0_BASE            (RK29_ADDR_BASE1+0x38000)
+#define RK29_TIMER0_PHYS            0x20038000
+#define RK29_TIMER0_SIZE            SZ_8K
+#define RK29_TIMER1_BASE            (RK29_ADDR_BASE1+0x3A000)
+#define RK29_TIMER1_PHYS            0x2003A000
+#define RK29_TIMER1_SIZE            SZ_8K
+#define RK29_GPIO4_BASE             (RK29_ADDR_BASE1+0x3C000)
+#define RK29_GPIO4_PHYS             0x2003C000
+#define RK29_GPIO4_SIZE             SZ_8K
+#define RK29_GPIO6_BASE             (RK29_ADDR_BASE1+0x3E000)
+#define RK29_GPIO6_PHYS             0x2003E000
+#define RK29_GPIO6_SIZE             SZ_8K
 
 //peri system APB
-#define RK29_TIMER2_BASE                       (RK29_ADDR_BASE1+0x44000)
-#define RK29_TIMER2_PHYS                       0x20044000
-#define RK29_TIMER2_SIZE                       SZ_16K
-#define RK29_TIMER3_BASE                       (RK29_ADDR_BASE1+0x48000)
-#define RK29_TIMER3_PHYS                       0x20048000
-#define RK29_TIMER3_SIZE                       SZ_16K
-#define RK29_WDT_PHYS                          0x2004C000
-#define RK29_WDT_SIZE                          SZ_16K
-#define RK29_PWM_BASE                          (RK29_ADDR_BASE1+0x50000)
-#define RK29_PWM_PHYS                          0x20050000
-#define RK29_PWM_SIZE                          SZ_16K
-#define RK29_I2C1_PHYS                         0x20054000
-#define RK29_I2C1_SIZE                         SZ_16K
-#define RK29_I2C2_PHYS                         0x20058000
-#define RK29_I2C2_SIZE                         SZ_16K
-#define RK29_I2C3_PHYS                         0x2005C000
-#define RK29_I2C3_SIZE                         SZ_16K
-#define RK29_UART1_PHYS                0x20060000
-#define RK29_UART1_BASE                (RK29_ADDR_BASE1+0x60000)
-#define RK29_UART1_SIZE                SZ_4K
-#define RK29_UART2_PHYS                                0x20064000
-#define RK29_UART2_SIZE                                SZ_4K
-#define RK29_UART3_PHYS                                0x20068000
-#define RK29_UART3_SIZE                                SZ_4K
-#define RK29_TIMER2_SIZE                       SZ_16K
-#define RK29_ADC_PHYS                          0x2006C000
-#define RK29_ADC_SIZE                          SZ_16K
-#define RK29_SPI0_PHYS                         0x20070000
-#define RK29_SPI0_BASE                         (RK29_ADDR_BASE1+0x70000)
-#define RK29_SPI0_SIZE                         SZ_16K
-#define RK29_SPI1_PHYS                         0x20074000
-#define RK29_SPI1_BASE                         (RK29_ADDR_BASE1+0x74000)
-#define RK29_SPI1_SIZE                         SZ_16K
-#define RK29_DMAC1_PHYS                                0x20078000
-#define RK29_DMAC1_SIZE                                SZ_16K
-#define RK29_SMC_PHYS                          0x2007C000
-#define RK29_SMC_SIZE                          SZ_16K
-#define RK29_GPIO1_BASE                                (RK29_ADDR_BASE1+0x80000)
-#define RK29_GPIO1_PHYS                                0x20080000
-#define RK29_GPIO1_SIZE                                SZ_16K
-#define RK29_GPIO2_BASE                                (RK29_ADDR_BASE1+0x84000)
-#define RK29_GPIO2_PHYS                                0x20084000
-#define RK29_GPIO2_SIZE                                SZ_16K
-#define RK29_GPIO3_BASE                                (RK29_ADDR_BASE1+0x88000)
-#define RK29_GPIO3_PHYS                                0x20088000
-#define RK29_GPIO3_SIZE                                SZ_16K
-#define RK29_GPIO5_BASE                                (RK29_ADDR_BASE1+0x8C000)
-#define RK29_GPIO5_PHYS                                0x2008C000
-#define RK29_GPIO5_SIZE                                SZ_16K
+#define RK29_TIMER2_BASE            (RK29_ADDR_BASE1+0x44000)
+#define RK29_TIMER2_PHYS            0x20044000
+#define RK29_TIMER2_SIZE            SZ_16K
+#define RK29_TIMER3_BASE            (RK29_ADDR_BASE1+0x48000)
+#define RK29_TIMER3_PHYS            0x20048000
+#define RK29_TIMER3_SIZE            SZ_16K
+#define RK29_WDT_PHYS               0x2004C000
+#define RK29_WDT_SIZE               SZ_16K
+#define RK29_PWM_BASE               (RK29_ADDR_BASE1+0x50000)
+#define RK29_PWM_PHYS               0x20050000
+#define RK29_PWM_SIZE               SZ_16K
+#define RK29_I2C1_PHYS              0x20054000
+#define RK29_I2C1_SIZE              SZ_16K
+#define RK29_I2C2_PHYS              0x20058000
+#define RK29_I2C2_SIZE              SZ_16K
+#define RK29_I2C3_PHYS              0x2005C000
+#define RK29_I2C3_SIZE              SZ_16K
+#define RK29_UART1_PHYS             0x20060000
+#define RK29_UART1_BASE             (RK29_ADDR_BASE1+0x60000)
+#define RK29_UART1_SIZE             SZ_4K
+#define RK29_UART2_PHYS             0x20064000
+#define RK29_UART2_SIZE             SZ_4K
+#define RK29_UART3_PHYS             0x20068000
+#define RK29_UART3_SIZE             SZ_4K
+#define RK29_TIMER2_SIZE            SZ_16K
+#define RK29_ADC_PHYS               0x2006C000
+#define RK29_ADC_SIZE               SZ_16K
+#define RK29_SPI0_PHYS              0x20070000
+#define RK29_SPI0_BASE              (RK29_ADDR_BASE1+0x70000)
+#define RK29_SPI0_SIZE              SZ_16K
+#define RK29_SPI1_PHYS              0x20074000
+#define RK29_SPI1_BASE              (RK29_ADDR_BASE1+0x74000)
+#define RK29_SPI1_SIZE              SZ_16K
+#define RK29_DMAC1_PHYS             0x20078000
+#define RK29_DMAC1_SIZE             SZ_16K
+#define RK29_DMAC1_BASE             (RK29_ADDR_BASE1+0x78000)
+#define RK29_SMC_PHYS               0x2007C000
+#define RK29_SMC_SIZE               SZ_16K
+#define RK29_GPIO1_BASE             (RK29_ADDR_BASE1+0x80000)
+#define RK29_GPIO1_PHYS             0x20080000
+#define RK29_GPIO1_SIZE             SZ_16K
+#define RK29_GPIO2_BASE             (RK29_ADDR_BASE1+0x84000)
+#define RK29_GPIO2_PHYS             0x20084000
+#define RK29_GPIO2_SIZE             SZ_16K
+#define RK29_GPIO3_BASE             (RK29_ADDR_BASE1+0x88000)
+#define RK29_GPIO3_PHYS             0x20088000
+#define RK29_GPIO3_SIZE             SZ_16K
+#define RK29_GPIO5_BASE             (RK29_ADDR_BASE1+0x8C000)
+#define RK29_GPIO5_PHYS             0x2008C000
+#define RK29_GPIO5_SIZE             SZ_16K
 #endif

diff --git a/arch/arm/mach-rk29/io.c b/arch/arm/mach-rk29/io.c
index b2e930417e95148220b89e3d8af6d7f8ffab4bd1..e4be8f679d4e76b97cb15926d25fdf9461529e60 100644 (file)
--- a/arch/arm/mach-rk29/io.c
+++ b/arch/arm/mach-rk29/io.c
@@ -52,6 +52,16 @@ static struct map_desc rk29_io_desc[] __initdata = {
        RK29_DEVICE(NANDC),
        RK29_DEVICE(SPI0),
        RK29_DEVICE(SPI1),
+#ifdef CONFIG_DDR_RECONFIG
+       RK29_DEVICE(LCDC),
+       RK29_DEVICE(GPU),
+       RK29_DEVICE(VCODEC),
+       RK29_DEVICE(VIP),
+       RK29_DEVICE(IPP),
+       RK29_DEVICE(DMAC0),
+       RK29_DEVICE(DMAC1),
+       RK29_DEVICE(SDMAC0),
+#endif
 };
 
 void __init rk29_map_common_io(void)

diff --git a/drivers/video/rk29_fb.c b/drivers/video/rk29_fb.c
index baad242a3bd525bba18fc9ac3cc9eb3c4caade05..3e1a90cc0525873301c279098b0d129eb39f4fc9 100644 (file)
--- a/drivers/video/rk29_fb.c
+++ b/drivers/video/rk29_fb.c
@@ -57,6 +57,7 @@
 #include <mach/rk29_iomap.h>
 #include <mach/pmu.h>
 #include <mach/rk29-ipp.h>
+#include <mach/ddr.h>
 
 #include "./display/screen/screen.h"
 
@@ -973,12 +974,16 @@ static int win0_blank(int blank_mode, struct fb_info *info)
     {
     case FB_BLANK_UNBLANK:
         LcdMskReg(inf, SYS_CONFIG, m_W0_ENABLE, v_W0_ENABLE(1));
+       LcdWrReg(inf, REG_CFG_DONE, 0x01);
         break;
     default:
         LcdMskReg(inf, SYS_CONFIG, m_W0_ENABLE, v_W0_ENABLE(0));
+       LcdWrReg(inf, REG_CFG_DONE, 0x01);
+#ifdef CONFIG_DDR_RECONFIG
+       msleep(40);
+#endif
         break;
     }
-    LcdWrReg(inf, REG_CFG_DONE, 0x01);
 
        mcu_refresh(inf);
     return 0;
@@ -2401,6 +2406,7 @@ static irqreturn_t rk29fb_irq(int irq, void *dev_id)
        wq_condition = 1;
        wake_up_interruptible(&wq);
 
+       rk29fb_irq_notify_ddr();
        return IRQ_HANDLED;
 }