OMAP3 clock: use pr_debug() rather than pr_info() in some clock change code

The CORE DPLL M2 frequency change code should use pr_debug(), not
pr_info(), for its debug messages.  Same with
omap2_clksel_round_rate_div().  While here, convert a few printk(KERN_ERR ..
into pr_err().

Signed-off-by: Paul Walmsley <paul@pwsan.com>

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 4247a1534411ba9f9cf5bfd23c9abf94bcd799c0..8935a8b261865870bb3b775bfc076e7ada8e5dfe 100644 (file)
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -547,8 +547,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
        const struct clksel_rate *clkr;
        u32 last_div = 0;
 
-       printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
-              clk->name, target_rate);
+       pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
+                clk->name, target_rate);
 
        *new_div = 1;
 
@@ -562,7 +562,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
 
                /* Sanity check */
                if (clkr->div <= last_div)
-                       printk(KERN_ERR "clock: clksel_rate table not sorted "
+                       pr_err("clock: clksel_rate table not sorted "
                               "for clock %s", clk->name);
 
                last_div = clkr->div;
@@ -574,7 +574,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
        }
 
        if (!clkr->div) {
-               printk(KERN_ERR "clock: Could not find divisor for target "
+               pr_err("clock: Could not find divisor for target "
                       "rate %ld for clock %s parent %s\n", target_rate,
                       clk->name, clk->parent->name);
                return ~0;
@@ -582,8 +582,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
 
        *new_div = clkr->div;
 
-       printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
-              (clk->parent->rate / clkr->div));
+       pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
+                (clk->parent->rate / clkr->div));
 
        return (clk->parent->rate / clkr->div);
 }

diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 811360af60dc23633f551d4e00676e02c1cd429c..2ee58fa5dc70b8333f3323cdd5f79f6fd38e53d5 100644 (file)
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -737,10 +737,10 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
                unlock_dll = 1;
        }
 
-       pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
-               validrate);
-       pr_info("clock: SDRC timing params used: %08x %08x %08x\n",
-               sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
+       pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
+                validrate);
+       pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
+                sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
 
        /* REVISIT: SRAM code doesn't support other M2 divisors yet */
        WARN_ON(new_div != 1 && new_div != 2);