Emit cross regclass register moves for thumb2.

Minor code duplication cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76124 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index a8a519a5ec3e4d586723e8db4d3a21cef208c5f6..72f40a017b4db2d8bcbef39756b69f59a9d1dbfc 100644 (file)
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -30,16 +30,6 @@ static cl::opt<bool>
 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
                cl::desc("Enable ARM 2-addr to 3-addr conv"));
 
-static inline
-const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
-  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
-}
-
-static inline
-const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
-  return MIB.addReg(0);
-}
-
 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget &STI)
   : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)) {
 }

diff --git a/lib/Target/ARM/ARMBaseInstrInfo.h b/lib/Target/ARM/ARMBaseInstrInfo.h
index c300264c822ccc71ea71ed98998ad6492130dc2d..1b0ef21fbaef7f5a4b463fc9c7489580f6c4c95f 100644 (file)
--- a/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -14,9 +14,10 @@
 #ifndef ARMBASEINSTRUCTIONINFO_H
 #define ARMBASEINSTRUCTIONINFO_H
 
-#include "llvm/Target/TargetInstrInfo.h"
-#include "ARMRegisterInfo.h"
 #include "ARM.h"
+#include "ARMRegisterInfo.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/Target/TargetInstrInfo.h"
 
 namespace llvm {
   class ARMSubtarget;
@@ -187,6 +188,16 @@ namespace ARMII {
   };
 }
 
+static inline
+const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
+  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
+}
+
+static inline
+const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
+  return MIB.addReg(0);
+}
+
 class ARMBaseInstrInfo : public TargetInstrInfoImpl {
 protected:
   // Can be only subclassed.

diff --git a/lib/Target/ARM/Thumb1InstrInfo.cpp b/lib/Target/ARM/Thumb1InstrInfo.cpp
index 356e2e2c50a6cdbd18881a7e1971444088fd9257..ddc6e0d154af633cf0355d66bea053d518f4e275 100644 (file)
--- a/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -22,11 +22,6 @@
 
 using namespace llvm;
 
-static inline
-const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
-  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
-}
-
 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
   : ARMBaseInstrInfo(STI), RI(*this, STI) {
 }

diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp
index 9c933063230a3ea5aad2563ed49de21cef214bf8..e2c511a849f1348fc300334105c8d35c4b4b27cf 100644 (file)
--- a/lib/Target/ARM/Thumb1RegisterInfo.cpp
+++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp
@@ -47,16 +47,6 @@ Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
   : ARMBaseRegisterInfo(tii, sti) {
 }
 
-static inline
-const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
-  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
-}
-
-static inline
-const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
-  return MIB.addReg(ARM::CPSR);
-}
-
 /// emitLoadConstPool - Emits a load from constpool to materialize the
 /// specified immediate.
 void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,

diff --git a/lib/Target/ARM/Thumb2InstrInfo.cpp b/lib/Target/ARM/Thumb2InstrInfo.cpp
index 6103463e87be31aecab4fc3a6cc55c8f639fc3e0..081cf4f550341d09fbf166c773d30ab30a921625 100644 (file)
--- a/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -87,3 +87,24 @@ Thumb2InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
 
   return false;
 }
+
+bool
+Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
+                              MachineBasicBlock::iterator I,
+                              unsigned DestReg, unsigned SrcReg,
+                              const TargetRegisterClass *DestRC,
+                              const TargetRegisterClass *SrcRC) const {
+  DebugLoc DL = DebugLoc::getUnknownLoc();
+  if (I != MBB.end()) DL = I->getDebugLoc();
+
+  if ((DestRC == ARM::GPRRegisterClass &&
+       SrcRC == ARM::tGPRRegisterClass) ||
+      (DestRC == ARM::tGPRRegisterClass &&
+       SrcRC == ARM::GPRRegisterClass)) {
+    AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::MOVr)),
+                                        DestReg).addReg(SrcReg)));
+    return true;
+  }
+
+  return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC);
+}

diff --git a/lib/Target/ARM/Thumb2InstrInfo.h b/lib/Target/ARM/Thumb2InstrInfo.h
index d408a7cffaf965fd0543248dac8aba614a09ba15..ac31707ab781b89d2f96f59aaa68ba08b7112e74 100644 (file)
--- a/lib/Target/ARM/Thumb2InstrInfo.h
+++ b/lib/Target/ARM/Thumb2InstrInfo.h
@@ -37,6 +37,12 @@ public:
   // Return true if the block does not fall through.
   bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
 
+  bool copyRegToReg(MachineBasicBlock &MBB,
+                    MachineBasicBlock::iterator I,
+                    unsigned DestReg, unsigned SrcReg,
+                    const TargetRegisterClass *DestRC,
+                    const TargetRegisterClass *SrcRC) const;
+
   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).

diff --git a/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll b/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll
new file mode 100644 (file)
index 0000000..c1fceee
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll
@@ -0,0 +1,35 @@
+; RUN: llvm-as < %s | llc
+
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
+target triple = "thumbv6t2-elf"
+       %struct.dwarf_cie = type <{ i32, i32, i8, [0 x i8], [3 x i8] }>
+
+declare arm_apcscc i8* @read_sleb128(i8*, i32* nocapture) nounwind
+
+define arm_apcscc i32 @get_cie_encoding(%struct.dwarf_cie* %cie) nounwind {
+entry:
+       br i1 undef, label %bb1, label %bb13
+
+bb1:           ; preds = %entry
+       %tmp38 = add i32 undef, 10              ; <i32> [#uses=1]
+       br label %bb.i
+
+bb.i:          ; preds = %bb.i, %bb1
+       %indvar.i = phi i32 [ 0, %bb1 ], [ %2, %bb.i ]          ; <i32> [#uses=3]
+       %tmp39 = add i32 %indvar.i, %tmp38              ; <i32> [#uses=1]
+       %p_addr.0.i = getelementptr i8* undef, i32 %tmp39               ; <i8*> [#uses=1]
+       %0 = load i8* %p_addr.0.i, align 1              ; <i8> [#uses=1]
+       %1 = icmp slt i8 %0, 0          ; <i1> [#uses=1]
+       %2 = add i32 %indvar.i, 1               ; <i32> [#uses=1]
+       br i1 %1, label %bb.i, label %read_uleb128.exit
+
+read_uleb128.exit:             ; preds = %bb.i
+       %.sum40 = add i32 %indvar.i, undef              ; <i32> [#uses=1]
+       %.sum31 = add i32 %.sum40, 2            ; <i32> [#uses=1]
+       %scevgep.i = getelementptr %struct.dwarf_cie* %cie, i32 0, i32 3, i32 %.sum31           ; <i8*> [#uses=1]
+       %3 = call arm_apcscc  i8* @read_sleb128(i8* %scevgep.i, i32* undef)             ; <i8*> [#uses=0]
+       unreachable
+
+bb13:          ; preds = %entry
+       ret i32 0
+}