MIPS: BCM63XX: use the new reset helper

Use the new reset helper where appropriate.

Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4453
Signed-off-by: John Crispin <blogic@openwrt.org>

diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index 89a5fb077862dcb6394f06d3b592271ce123ccc2..b9e948d594300281cc4199c3a89e5756630e111d 100644 (file)
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -14,6 +14,7 @@
 #include <bcm63xx_cpu.h>
 #include <bcm63xx_io.h>
 #include <bcm63xx_regs.h>
+#include <bcm63xx_reset.h>
 #include <bcm63xx_clk.h>
 
 static DEFINE_MUTEX(clocks_mutex);
@@ -124,15 +125,10 @@ static void enetsw_set(struct clk *clk, int enable)
                        CKCTL_6368_SWPKT_USB_EN |
                        CKCTL_6368_SWPKT_SAR_EN, enable);
        if (enable) {
-               u32 val;
-
                /* reset switch core afer clock change */
-               val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
-               val &= ~SOFTRESET_6368_ENETSW_MASK;
-               bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+               bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 1);
                msleep(10);
-               val |= SOFTRESET_6368_ENETSW_MASK;
-               bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+               bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 0);
                msleep(10);
        }
 }
@@ -222,15 +218,10 @@ static void xtm_set(struct clk *clk, int enable)
                        CKCTL_6368_SWPKT_SAR_EN, enable);
 
        if (enable) {
-               u32 val;
-
                /* reset sar core afer clock change */
-               val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
-               val &= ~SOFTRESET_6368_SAR_MASK;
-               bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+               bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 1);
                mdelay(1);
-               val |= SOFTRESET_6368_SAR_MASK;
-               bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+               bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 0);
                mdelay(1);
        }
 }

diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index fa8c320936feec452fc46b51a5c78f8441def1e9..ca179b6ff39b374e0743f76815775972e29e15c0 100644 (file)
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -14,6 +14,8 @@
 #include <linux/clk.h>
 #include <asm/bootinfo.h>
 
+#include <bcm63xx_reset.h>
+
 #include "pci-bcm63xx.h"
 
 /*
@@ -126,23 +128,14 @@ static void __init bcm63xx_reset_pcie(void)
        bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
 
        /* reset the PCIe core */
-       val = bcm_perf_readl(PERF_SOFTRESET_6328_REG);
-
-       val &= ~SOFTRESET_6328_PCIE_MASK;
-       val &= ~SOFTRESET_6328_PCIE_CORE_MASK;
-       val &= ~SOFTRESET_6328_PCIE_HARD_MASK;
-       val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
-       bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
+       bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
+       bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1);
        mdelay(10);
 
-       val |= SOFTRESET_6328_PCIE_MASK;
-       val |= SOFTRESET_6328_PCIE_CORE_MASK;
-       val |= SOFTRESET_6328_PCIE_HARD_MASK;
-       bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
+       bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0);
        mdelay(10);
 
-       val |= SOFTRESET_6328_PCIE_EXT_MASK;
-       bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
+       bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 0);
        mdelay(200);
 }