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Specify S registers as D registers' sub-registers.
author
Evan Cheng
<evan.cheng@apple.com>
Fri, 20 Apr 2007 21:20:10 +0000
(21:20 +0000)
committer
Evan Cheng
<evan.cheng@apple.com>
Fri, 20 Apr 2007 21:20:10 +0000
(21:20 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36280
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/ARM/ARMRegisterInfo.td
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diff --git
a/lib/Target/ARM/ARMRegisterInfo.td
b/lib/Target/ARM/ARMRegisterInfo.td
index b46a9522049cf7ca6d1ecb95fe90e385380a867a..691514cd8eeb20c785e776756887218339c68f5d 100644
(file)
--- a/
lib/Target/ARM/ARMRegisterInfo.td
+++ b/
lib/Target/ARM/ARMRegisterInfo.td
@@
-13,10
+13,10
@@
//===----------------------------------------------------------------------===//
// Registers are identified with 4-bit ID numbers.
-class ARMReg<bits<4> num, string n, list<Register>
aliase
s = []> : Register<n> {
+class ARMReg<bits<4> num, string n, list<Register>
subreg
s = []> : Register<n> {
field bits<4> Num;
let Namespace = "ARM";
- let
Aliases = aliase
s;
+ let
SubRegs = subreg
s;
}
class ARMFReg<bits<5> num, string n> : Register<n> {