It's "necessary" to spell "necessarily" correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5833 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp
index 6adccb15e8a95c9ddcb158b0b90623b2121dd280..5569708700f245ae22ba493730241f8ec196548b 100644 (file)
--- a/lib/Target/X86/InstSelectSimple.cpp
+++ b/lib/Target/X86/InstSelectSimple.cpp
@@ -1209,7 +1209,7 @@ void ISel::EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class) {
   // Emit the byte swap instruction...
   switch (Class) {
   case cByte:
-    // No byteswap neccesary for 8 bit value...
+    // No byteswap necessary for 8 bit value...
     BuildMI(BB, X86::MOVrr8, 1, DestReg).addReg(SrcReg);
     break;
   case cInt:
@@ -1219,7 +1219,7 @@ void ISel::EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class) {
     
   case cShort:
     // For 16 bit we have to use an xchg instruction, because there is no
-    // 16-bit bswap.  XCHG is neccesarily not in SSA form, so we force things
+    // 16-bit bswap.  XCHG is necessarily not in SSA form, so we force things
     // into AX to do the xchg.
     //
     BuildMI(BB, X86::MOVrr16, 1, X86::AX).addReg(SrcReg);

diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp
index 6adccb15e8a95c9ddcb158b0b90623b2121dd280..5569708700f245ae22ba493730241f8ec196548b 100644 (file)
--- a/lib/Target/X86/X86ISelSimple.cpp
+++ b/lib/Target/X86/X86ISelSimple.cpp
@@ -1209,7 +1209,7 @@ void ISel::EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class) {
   // Emit the byte swap instruction...
   switch (Class) {
   case cByte:
-    // No byteswap neccesary for 8 bit value...
+    // No byteswap necessary for 8 bit value...
     BuildMI(BB, X86::MOVrr8, 1, DestReg).addReg(SrcReg);
     break;
   case cInt:
@@ -1219,7 +1219,7 @@ void ISel::EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class) {
     
   case cShort:
     // For 16 bit we have to use an xchg instruction, because there is no
-    // 16-bit bswap.  XCHG is neccesarily not in SSA form, so we force things
+    // 16-bit bswap.  XCHG is necessarily not in SSA form, so we force things
     // into AX to do the xchg.
     //
     BuildMI(BB, X86::MOVrr16, 1, X86::AX).addReg(SrcReg);