Simplify FastISel's constructor argument list, make the FastISel

class hold a MachineRegisterInfo member, and make the
MachineBasicBlock be passed in to SelectInstructions rather
than the FastISel constructor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55076 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/FastISel.h b/include/llvm/CodeGen/FastISel.h
index a241756df5b32733072a4296adf08237199153ee..27504ac8bdb4ca4a2b1593c646c0eae2e8439438 100644 (file)
--- a/include/llvm/CodeGen/FastISel.h
+++ b/include/llvm/CodeGen/FastISel.h
@@ -22,6 +22,7 @@ namespace llvm {
 
 class MachineBasicBlock;
 class MachineFunction;
+class MachineRegisterInfo;
 class TargetInstrInfo;
 class TargetRegisterClass;
 
@@ -30,8 +31,9 @@ class TargetRegisterClass;
 /// lowering, but runs quickly.
 class FastISel {
   MachineBasicBlock *MBB;
-  MachineFunction *MF;
-  const TargetInstrInfo *TII;
+  MachineFunction &MF;
+  MachineRegisterInfo &MRI;
+  const TargetInstrInfo &TII;
 
 public:
   /// SelectInstructions - Do "fast" instruction selection over the
@@ -41,14 +43,13 @@ public:
   /// register numbers.
   BasicBlock::iterator
   SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
-                     DenseMap<const Value*, unsigned> &ValueMap);
+                     DenseMap<const Value*, unsigned> &ValueMap,
+                     MachineBasicBlock *mbb);
 
   virtual ~FastISel();
 
 protected:
-  FastISel(MachineBasicBlock *mbb, MachineFunction *mf,
-           const TargetInstrInfo *tii)
-    : MBB(mbb), MF(mf), TII(tii) {}
+  explicit FastISel(MachineFunction &mf);
 
   /// FastEmit_r - This method is called by target-independent code
   /// to request that an instruction with the given type and opcode

diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index 3702dbae9181a7f67212e87f9f1c72a84ee292fa..bb3105b5e82f21848f6bf8b4fce5664437da889c 100644 (file)
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -42,7 +42,6 @@ namespace llvm {
   class SDValue;
   class SelectionDAG;
   class TargetData;
-  class TargetInstrInfo;
   class TargetMachine;
   class TargetRegisterClass;
   class TargetSubtarget;
@@ -1116,9 +1115,7 @@ public:
 
   /// createFastISel - This method returns a target specific FastISel object,
   /// or null if the target does not support "fast" ISel.
-  virtual FastISel *createFastISel(MachineBasicBlock *,
-                                   MachineFunction *,
-                                   const TargetInstrInfo *) { return 0; }
+  virtual FastISel *createFastISel(MachineFunction &) { return 0; }
 
   //===--------------------------------------------------------------------===//
   // Inline Asm Support hooks

diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index 3ff8148e99e0a03b8c2ed7d3a7abc7c23ae95ae5..70e0248c23ec4784d1afc1c8dcfe78f2de2797de 100644 (file)
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -16,6 +16,7 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetMachine.h"
 using namespace llvm;
 
 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
@@ -54,7 +55,9 @@ bool FastISel::SelectGetElementPtr(Instruction *I,
 BasicBlock::iterator
 FastISel::SelectInstructions(BasicBlock::iterator Begin,
                              BasicBlock::iterator End,
-                             DenseMap<const Value*, unsigned> &ValueMap) {
+                             DenseMap<const Value*, unsigned> &ValueMap,
+                             MachineBasicBlock *mbb) {
+  MBB = mbb;
   BasicBlock::iterator I = Begin;
 
   for (; I != End; ++I) {
@@ -108,7 +111,7 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin,
       if (BI->isUnconditional()) {
          MachineFunction::iterator NextMBB =
            next(MachineFunction::iterator(MBB));
-         if (NextMBB != MF->end() &&
+         if (NextMBB != MF.end() &&
              NextMBB->getBasicBlock() == BI->getSuccessor(0)) {
           MBB->addSuccessor(NextMBB);
           break;
@@ -127,6 +130,10 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin,
   return I;
 }
 
+FastISel::FastISel(MachineFunction &mf)
+  : MF(mf), MRI(mf.getRegInfo()), TII(*mf.getTarget().getInstrInfo()) {
+}
+
 FastISel::~FastISel() {}
 
 unsigned FastISel::FastEmit_(MVT::SimpleValueType, ISD::NodeType) {
@@ -145,11 +152,10 @@ unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType,
 
 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
                                  const TargetRegisterClass* RC) {
-  MachineRegisterInfo &MRI = MF->getRegInfo();
   unsigned ResultReg = MRI.createVirtualRegister(RC);
-  const TargetInstrDesc &II = TII->get(MachineInstOpcode);
+  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 
-  MachineInstr *MI = BuildMI(*MF, II, ResultReg);
+  MachineInstr *MI = BuildMI(MF, II, ResultReg);
   MBB->push_back(MI);
   return ResultReg;
 }
@@ -157,11 +163,10 @@ unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
                                   const TargetRegisterClass *RC,
                                   unsigned Op0) {
-  MachineRegisterInfo &MRI = MF->getRegInfo();
   unsigned ResultReg = MRI.createVirtualRegister(RC);
-  const TargetInstrDesc &II = TII->get(MachineInstOpcode);
+  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 
-  MachineInstr *MI = BuildMI(*MF, II, ResultReg).addReg(Op0);
+  MachineInstr *MI = BuildMI(MF, II, ResultReg).addReg(Op0);
   MBB->push_back(MI);
   return ResultReg;
 }
@@ -169,11 +174,10 @@ unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
                                    const TargetRegisterClass *RC,
                                    unsigned Op0, unsigned Op1) {
-  MachineRegisterInfo &MRI = MF->getRegInfo();
   unsigned ResultReg = MRI.createVirtualRegister(RC);
-  const TargetInstrDesc &II = TII->get(MachineInstOpcode);
+  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 
-  MachineInstr *MI = BuildMI(*MF, II, ResultReg).addReg(Op0).addReg(Op1);
+  MachineInstr *MI = BuildMI(MF, II, ResultReg).addReg(Op0).addReg(Op1);
   MBB->push_back(MI);
   return ResultReg;
 }

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 997bd116048de373ed4d3d331c11520afe5f6faf..9ffb6ccc4af4ba648730596001c26afc8aca1f59 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -5111,9 +5111,9 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
       !BB->isLandingPad() &&
       isa<BranchInst>(LLVMBB->getTerminator()) &&
       cast<BranchInst>(LLVMBB->getTerminator())->isUnconditional()) {
-    if (FastISel *F = TLI.createFastISel(BB, &FuncInfo.MF,
-                                       TLI.getTargetMachine().getInstrInfo())) {
-      Begin = F->SelectInstructions(Begin, LLVMBB->end(), FuncInfo.ValueMap);
+    if (FastISel *F = TLI.createFastISel(FuncInfo.MF)) {
+      Begin = F->SelectInstructions(Begin, LLVMBB->end(),
+                                    FuncInfo.ValueMap, BB);
 
       // Clean up the FastISel object. TODO: Reorganize what data is
       // stored in the FastISel class itself and what is merely passed

diff --git a/lib/Target/X86/X86FastISel.h b/lib/Target/X86/X86FastISel.h
index 0f2b26a4d2f534c522d9447501c450783d2965cf..56dfc4f4b9e4a327591e35e4b94ebfc7d7ac095c 100644 (file)
--- a/lib/Target/X86/X86FastISel.h
+++ b/lib/Target/X86/X86FastISel.h
@@ -18,14 +18,11 @@
 namespace llvm {
 
 class FastISel;
-class MachineBasicBlock;
 class MachineFunction;
-class TargetInstrInfo;
 
 namespace X86 {
 
-FastISel *createFastISel(MachineBasicBlock *mbb, MachineFunction *mf,
-                         const TargetInstrInfo *tii);
+FastISel *createFastISel(MachineFunction &mf);
 
 } // namespace X86
 

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index c43ce33c8c6ba69e2e9d02865945e33e9e93c426..9a77c8e61c6edb48c8df86a718ef5c9340fd164a 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1872,10 +1872,8 @@ bool X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Call,
   return false;
 }
 
-FastISel *X86TargetLowering::createFastISel(MachineBasicBlock *mbb,
-                                            MachineFunction *mf,
-                                            const TargetInstrInfo *tii) {
-  return X86::createFastISel(mbb, mf, tii);
+FastISel *X86TargetLowering::createFastISel(MachineFunction &mf) {
+  return X86::createFastISel(mf);
 }
 
 

diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h
index 1415be7b63d38857b7efcdaad474e4c557e37713..c35cce2c8123bce49f1a0adb4658cbb87390e59c 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.h
+++ b/lib/Target/X86/X86ISelLowering.h
@@ -469,9 +469,7 @@ namespace llvm {
 
     /// createFastISel - This method returns a target specific FastISel object,
     /// or null if the target does not support "fast" ISel.
-    virtual FastISel *createFastISel(MachineBasicBlock *mbb,
-                                     MachineFunction *mf,
-                                     const TargetInstrInfo *tii);
+    virtual FastISel *createFastISel(MachineFunction &mf);
     
   private:
     /// Subtarget - Keep a pointer to the X86Subtarget around so that we can

diff --git a/utils/TableGen/FastISelEmitter.cpp b/utils/TableGen/FastISelEmitter.cpp
index b434c15d8c2de39f2fe356b6b8fc6cb57520cb92..9650ea8855b83d265b24423dd6f5baeaf893a639 100644 (file)
--- a/utils/TableGen/FastISelEmitter.cpp
+++ b/utils/TableGen/FastISelEmitter.cpp
@@ -295,16 +295,14 @@ void FastISelEmitter::run(std::ostream &OS) {
     OS << ");\n";
   }
   OS << "public:\n";
-  OS << "  FastISel(MachineBasicBlock *mbb, MachineFunction *mf, ";
-  OS << "const TargetInstrInfo *tii) : llvm::FastISel(mbb, mf, tii) {}\n";
+  OS << "  explicit FastISel(MachineFunction &mf) : llvm::FastISel(mf) {}\n";
   OS << "};\n";
   OS << "\n";
 
   // Define the target FastISel creation function.
   OS << "llvm::FastISel *" << InstNS
-     << "createFastISel(MachineBasicBlock *mbb, MachineFunction *mf, ";
-  OS << "const TargetInstrInfo *tii) {\n";
-  OS << "  return new " << InstNS << "FastISel(mbb, mf, tii);\n";
+     << "createFastISel(MachineFunction &mf) {\n";
+  OS << "  return new " << InstNS << "FastISel(mf);\n";
   OS << "}\n";
   OS << "\n";