drm/i915: vlv: check port power domain instead of only D0 for eDP VDD on
authorImre Deak <imre.deak@intel.com>
Mon, 14 Apr 2014 17:24:33 +0000 (20:24 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 5 May 2014 07:09:03 +0000 (09:09 +0200)
Some platforms need additional power domains to be on in addition to the
device D0 state to access the panel registers.

Suggested by Daniel.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76987
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_dp.c

index a421c81f2d883aa1b0139ba34c70a9490cf29807..34ed143ab479317568ccdbc0c46fe943f85e030b 100644 (file)
@@ -313,8 +313,12 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 {
        struct drm_device *dev = intel_dp_to_dev(intel_dp);
        struct drm_i915_private *dev_priv = dev->dev_private;
+       struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+       struct intel_encoder *intel_encoder = &intel_dig_port->base;
+       enum intel_display_power_domain power_domain;
 
-       return !dev_priv->pm.suspended &&
+       power_domain = intel_display_port_power_domain(intel_encoder);
+       return intel_display_power_enabled(dev_priv, power_domain) &&
               (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
 }