Add getAllocatableSet() function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16059 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/MRegisterInfo.h b/include/llvm/Target/MRegisterInfo.h
index 8ec2dde297dfadcef1f5f7b0b6f473f4bd115731..572af3f1d282b5aef153b25dabf46fe1a3613ddc 100644 (file)
--- a/include/llvm/Target/MRegisterInfo.h
+++ b/include/llvm/Target/MRegisterInfo.h
@@ -160,6 +160,10 @@ public:
     return Reg >= FirstVirtualRegister;
   }
 
+  /// getAllocatableSet - Returns a bitset indexed by register number
+  /// indicating if a register is allocatable or not.
+  std::vector<bool> getAllocatableSet(MachineFunction &MF) const;
+
   const MRegisterDesc &operator[](unsigned RegNo) const {
     assert(RegNo < NumRegs &&
            "Attempting to access record for invalid register number!");

diff --git a/lib/Target/MRegisterInfo.cpp b/lib/Target/MRegisterInfo.cpp
index 7c1028bc32379834f7e77fb5819c4a94cedabadf..30b54a6414dc146743ce9c17c63a35a7b31b7f56 100644 (file)
--- a/lib/Target/MRegisterInfo.cpp
+++ b/lib/Target/MRegisterInfo.cpp
@@ -28,12 +28,14 @@ MRegisterInfo::MRegisterInfo(const MRegisterDesc *D, unsigned NR,
 
   // Fill in the PhysRegClasses map
   for (MRegisterInfo::regclass_iterator I = regclass_begin(),
-         E = regclass_end(); I != E; ++I)
-    for (unsigned i = 0, e = (*I)->getNumRegs(); i != e; ++i) {
-      unsigned Reg = (*I)->getRegister(i);
+         E = regclass_end(); I != E; ++I) {
+    const TargetRegisterClass *RC = *I;
+    for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i) {
+      unsigned Reg = RC->getRegister(i);
       assert(PhysRegClasses[Reg] == 0 && "Register in more than one class?");
-      PhysRegClasses[Reg] = *I;
+      PhysRegClasses[Reg] = RC;
     }
+  }
 
   CallFrameSetupOpcode   = CFSO;
   CallFrameDestroyOpcode = CFDO;
@@ -44,4 +46,16 @@ MRegisterInfo::~MRegisterInfo() {
   delete[] PhysRegClasses;
 }
 
+std::vector<bool> MRegisterInfo::getAllocatableSet(MachineFunction &MF) const {
+  std::vector<bool> Allocatable(NumRegs);
+  for (MRegisterInfo::regclass_iterator I = regclass_begin(),
+         E = regclass_end(); I != E; ++I) {
+    const TargetRegisterClass *RC = *I;
+    for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
+           E = RC->allocation_order_end(MF); I != E; ++I)
+      Allocatable[*I] = true;
+  }
+  return Allocatable;
+}  
+
 } // End llvm namespace