drm/i915: convert PIPE_CLK_SEL to transcoder
authorPaulo Zanoni <paulo.r.zanoni@intel.com>
Tue, 23 Oct 2012 20:29:56 +0000 (18:29 -0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 26 Oct 2012 08:24:46 +0000 (10:24 +0200)
This register appeared in Haswell. It does not have an EDP version
because the EDP transcoder is always tied to the DDIA clock. Notice
that if we call PIPE_CLK_SEL(pipe) when pipe is PIPE_A and transcoder
is TRANSCODER_EDP we might introduce a bug, that's why this is a
transcoder register even though it does not have an EDP version.

Even though Haswell names this register PIPE_CLK_SEL, it will be
renamed to TRANS_CLK_SEL in the future, so let's just start using the
real name that makes more sense and avoids misusage.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_ddi.c

index 598f83a298cf22349d11907f0e9fe7990efd86f3..99cda88819c7c5bbbf1224f7eb92e5e03dfa31b3 100644 (file)
 #define  PORT_CLK_SEL_WRPLL2           (5<<29)
 #define  PORT_CLK_SEL_NONE             (7<<29)
 
-/* Pipe clock selection */
-#define PIPE_CLK_SEL_A                 0x46140
-#define PIPE_CLK_SEL_B                 0x46144
-#define PIPE_CLK_SEL(pipe) _PIPE(pipe, PIPE_CLK_SEL_A, PIPE_CLK_SEL_B)
-/* For each pipe, we need to select the corresponding port clock */
-#define  PIPE_CLK_SEL_DISABLED         (0x0<<29)
-#define  PIPE_CLK_SEL_PORT(x)          ((x+1)<<29)
+/* Transcoder clock selection */
+#define TRANS_CLK_SEL_A                        0x46140
+#define TRANS_CLK_SEL_B                        0x46144
+#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
+/* For each transcoder, we need to select the corresponding port clock */
+#define  TRANS_CLK_SEL_DISABLED                (0x0<<29)
+#define  TRANS_CLK_SEL_PORT(x)         ((x+1)<<29)
 
 #define _PIPEA_MSA_MISC                        0x60410
 #define _PIPEB_MSA_MISC                        0x61410
index 81cca482c9dc71e3bde3c96e072e8407ed3125c1..f568862aca579b598b1d5480bf2cc923ecdb6352 100644 (file)
@@ -1095,15 +1095,21 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
        struct drm_i915_private *dev_priv = crtc->dev->dev_private;
        struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
        enum port port = intel_ddi_get_encoder_port(intel_encoder);
+       enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 
-       I915_WRITE(PIPE_CLK_SEL(intel_crtc->pipe), PIPE_CLK_SEL_PORT(port));
+       if (cpu_transcoder != TRANSCODER_EDP)
+               I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+                          TRANS_CLK_SEL_PORT(port));
 }
 
 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
 {
        struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
+       enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 
-       I915_WRITE(PIPE_CLK_SEL(intel_crtc->pipe), PIPE_CLK_SEL_DISABLED);
+       if (cpu_transcoder != TRANSCODER_EDP)
+               I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+                          TRANS_CLK_SEL_DISABLED);
 }
 
 void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)