\r
//set rmii ref clock 50MHz\r
mac_clk = clk_get(NULL, "mac_ref_div");\r
+ if (IS_ERR(mac_clk))\r
+ mac_clk = NULL;\r
arm_clk = clk_get(NULL, "arm_pll");\r
- mac_parent = clk_get_parent(mac_clk);\r
+ if (IS_ERR(arm_clk))\r
+ arm_clk = NULL;\r
+ if (mac_clk) {\r
+ mac_parent = clk_get_parent(mac_clk);\r
+ if (IS_ERR(mac_parent))\r
+ mac_parent = NULL;\r
+ }\r
if (arm_clk && mac_parent && (arm_clk == mac_parent))\r
wake_lock(&idlelock);\r
\r
\r
//clock close\r
mac_clk = clk_get(NULL, "mac_ref_div");\r
- mac_parent = clk_get_parent(mac_clk); \r
+ if (IS_ERR(mac_clk))\r
+ mac_clk = NULL;\r
+ if (mac_clk) {\r
+ mac_parent = clk_get_parent(mac_clk);\r
+ if (IS_ERR(mac_parent))\r
+ mac_parent = NULL;\r
+ }\r
arm_clk = clk_get(NULL, "arm_pll");\r
+ if (IS_ERR(arm_clk))\r
+ arm_clk = NULL;\r
\r
if (arm_clk && mac_parent && (arm_clk == mac_parent))\r
wake_unlock(&idlelock);\r
#define VMAC_VERSION "1.0"\r
\r
/* Buffer descriptors */\r
+#ifdef CONFIG_ARCH_RK29\r
#define TX_BDT_LEN 16 /* Number of receive BD's */\r
+#else\r
+#define TX_BDT_LEN 255 /* Number of receive BD's */\r
+#endif\r
#define RX_BDT_LEN 255 /* Number of transmit BD's */\r
\r
/* BD poll rate, in 1024 cycles. @100Mhz: x * 1024 cy * 10ns = 1ms */\r