Properly support v8i8 and v4i16 types. It now converts them to v2i32 for

load and stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35002 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index b017e2a7460c712c228f1d203666174eb6171b88..9bcff7acb1658ef5ce23aef5493c33ecb84fc585 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -327,9 +327,12 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
     addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
 
     // FIXME: add MMX packed arithmetics
-    setOperationAction(ISD::LOAD,             MVT::v8i8,  Legal);
-    setOperationAction(ISD::LOAD,             MVT::v4i16, Legal);
+    setOperationAction(ISD::LOAD,             MVT::v8i8,  Promote);
+    AddPromotedToType (ISD::LOAD,             MVT::v8i8,  MVT::v2i32);
+    setOperationAction(ISD::LOAD,             MVT::v4i16, Promote);
+    AddPromotedToType (ISD::LOAD,             MVT::v4i16, MVT::v2i32);
     setOperationAction(ISD::LOAD,             MVT::v2i32, Legal);
+
     setOperationAction(ISD::BUILD_VECTOR,     MVT::v8i8,  Expand);
     setOperationAction(ISD::BUILD_VECTOR,     MVT::v4i16, Expand);
     setOperationAction(ISD::BUILD_VECTOR,     MVT::v2i32, Expand);

diff --git a/lib/Target/X86/X86InstrMMX.td b/lib/Target/X86/X86InstrMMX.td
index 579fb9e7c8b5bca41592f3ff27ccff14841a925d..4209e56733ef207142e51b61f51a946e51bd360a 100644 (file)
--- a/lib/Target/X86/X86InstrMMX.td
+++ b/lib/Target/X86/X86InstrMMX.td
@@ -1,4 +1,4 @@
-//====- X86InstrMMX.td - Describe the X86 Instruction Set -------*- C++ -*-===//
+//====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
 // 
 //                     The LLVM Compiler Infrastructure
 //
@@ -33,14 +33,17 @@ def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst),
                           [(set VR64:$dst, (v8i8 (undef)))]>,
                         Requires<[HasMMX]>;
 
-def : Pat<(v8i8  (undef)), (IMPLICIT_DEF_VR64)>,  Requires<[HasMMX]>;
-def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>,  Requires<[HasMMX]>;
-def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>,  Requires<[HasMMX]>;
+// 64-bit vector undef's.
+def : Pat<(v8i8  (undef)), (IMPLICIT_DEF_VR64)>;
+def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>;
+def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>;
 
 //===----------------------------------------------------------------------===//
 // MMX Pattern Fragments
 //===----------------------------------------------------------------------===//
 
+def loadv8i8  : PatFrag<(ops node:$ptr), (v8i8  (load node:$ptr))>;
+def loadv4i16 : PatFrag<(ops node:$ptr), (v4i16 (load node:$ptr))>;
 def loadv2i32 : PatFrag<(ops node:$ptr), (v2i32 (load node:$ptr))>;
 
 //===----------------------------------------------------------------------===//
@@ -120,3 +123,11 @@ def : Pat<(store (v8i8  VR64:$src), addr:$dst),
           (MOVQ64mr addr:$dst, VR64:$src)>;
 def : Pat<(store (v4i16 VR64:$src), addr:$dst),
           (MOVQ64mr addr:$dst, VR64:$src)>;
+
+// Bit convert.
+def : Pat<(v8i8  (bitconvert (v2i32 VR64:$src))), (v8i8  VR64:$src)>;
+def : Pat<(v8i8  (bitconvert (v4i16 VR64:$src))), (v8i8  VR64:$src)>;
+def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
+def : Pat<(v4i16 (bitconvert (v8i8  VR64:$src))), (v4i16 VR64:$src)>;
+def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
+def : Pat<(v2i32 (bitconvert (v8i8  VR64:$src))), (v2i32 VR64:$src)>;