drm/radeon/kms: add initial Evergreen support (Radeon HD 5xxx)
authorAlex Deucher <alexdeucher@gmail.com>
Tue, 12 Jan 2010 22:54:34 +0000 (17:54 -0500)
committerDave Airlie <airlied@redhat.com>
Mon, 8 Feb 2010 23:44:02 +0000 (09:44 +1000)
This adds initial Evergreen KMS support, it doesn't include
any acceleration features or interrupt handling yet.

Major changes are DCE4 handling for PLLs for the > 2 crtcs.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
19 files changed:
drivers/gpu/drm/radeon/Makefile
drivers/gpu/drm/radeon/atombios_crtc.c
drivers/gpu/drm/radeon/atombios_dp.c
drivers/gpu/drm/radeon/evergreen.c [new file with mode: 0644]
drivers/gpu/drm/radeon/evergreen_reg.h [new file with mode: 0644]
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_asic.h
drivers/gpu/drm/radeon/radeon_atombios.c
drivers/gpu/drm/radeon/radeon_clocks.c
drivers/gpu/drm/radeon/radeon_combios.c
drivers/gpu/drm/radeon/radeon_cursor.c
drivers/gpu/drm/radeon/radeon_device.c
drivers/gpu/drm/radeon/radeon_display.c
drivers/gpu/drm/radeon/radeon_encoders.c
drivers/gpu/drm/radeon/radeon_family.h
drivers/gpu/drm/radeon/radeon_mode.h
drivers/gpu/drm/radeon/radeon_reg.h
drivers/gpu/drm/radeon/rv770d.h
include/drm/drm_pciids.h

index 1cc7b937b1eaea4cdaac2df729613a6142fa9e90..83c59079193b56f784a362f4281b37f14f7307ad 100644 (file)
@@ -54,7 +54,8 @@ radeon-y += radeon_device.o radeon_kms.o \
        radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \
        rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \
        r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \
-       r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o
+       r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \
+       evergreen.o
 
 radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
 
index bb45517719aeb8b959ad8fe7916a4a1be85a18f9..7e7c0b32bb650245c85e369026e0ff0bcc45dfed 100644 (file)
@@ -249,13 +249,17 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
                if (ASIC_IS_DCE3(rdev))
                        atombios_enable_crtc_memreq(crtc, 1);
                atombios_blank_crtc(crtc, 0);
-               drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
+               /* XXX re-enable when interrupt support is added */
+               if (!ASIC_IS_DCE4(rdev))
+                       drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
                radeon_crtc_load_lut(crtc);
                break;
        case DRM_MODE_DPMS_STANDBY:
        case DRM_MODE_DPMS_SUSPEND:
        case DRM_MODE_DPMS_OFF:
-               drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
+               /* XXX re-enable when interrupt support is added */
+               if (!ASIC_IS_DCE4(rdev))
+                       drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
                atombios_blank_crtc(crtc, 1);
                if (ASIC_IS_DCE3(rdev))
                        atombios_enable_crtc_memreq(crtc, 0);
@@ -367,6 +371,10 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable)
        uint16_t percentage = 0;
        uint8_t type = 0, step = 0, delay = 0, range = 0;
 
+       /* XXX add ss support for DCE4 */
+       if (ASIC_IS_DCE4(rdev))
+               return;
+
        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
                if (encoder->crtc == crtc) {
                        radeon_encoder = to_radeon_encoder(encoder);
@@ -411,6 +419,7 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable)
 
 union adjust_pixel_clock {
        ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
+       ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
 };
 
 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
@@ -422,6 +431,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
        struct drm_encoder *encoder = NULL;
        struct radeon_encoder *radeon_encoder = NULL;
        u32 adjusted_clock = mode->clock;
+       int encoder_mode = 0;
 
        /* reset the pll flags */
        pll->flags = 0;
@@ -459,6 +469,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
                if (encoder->crtc == crtc) {
                        radeon_encoder = to_radeon_encoder(encoder);
+                       encoder_mode = atombios_get_encoder_mode(encoder);
                        if (ASIC_IS_AVIVO(rdev)) {
                                /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
                                if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
@@ -484,14 +495,9 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
         */
        if (ASIC_IS_DCE3(rdev)) {
                union adjust_pixel_clock args;
-               struct radeon_encoder_atom_dig *dig;
                u8 frev, crev;
                int index;
 
-               if (!radeon_encoder->enc_priv)
-                       return adjusted_clock;
-               dig = radeon_encoder->enc_priv;
-
                index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
                atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
                                      &crev);
@@ -505,12 +511,51 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
                        case 2:
                                args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
                                args.v1.ucTransmitterID = radeon_encoder->encoder_id;
-                               args.v1.ucEncodeMode = atombios_get_encoder_mode(encoder);
+                               args.v1.ucEncodeMode = encoder_mode;
 
                                atom_execute_table(rdev->mode_info.atom_context,
                                                   index, (uint32_t *)&args);
                                adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
                                break;
+                       case 3:
+                               args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
+                               args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
+                               args.v3.sInput.ucEncodeMode = encoder_mode;
+                               args.v3.sInput.ucDispPllConfig = 0;
+                               if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
+                                       struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
+
+                                       if (encoder_mode == ATOM_ENCODER_MODE_DP)
+                                               args.v3.sInput.ucDispPllConfig |=
+                                                       DISPPLL_CONFIG_COHERENT_MODE;
+                                       else {
+                                               if (dig->coherent_mode)
+                                                       args.v3.sInput.ucDispPllConfig |=
+                                                               DISPPLL_CONFIG_COHERENT_MODE;
+                                               if (mode->clock > 165000)
+                                                       args.v3.sInput.ucDispPllConfig |=
+                                                               DISPPLL_CONFIG_DUAL_LINK;
+                                       }
+                               } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
+                                       /* may want to enable SS on DP/eDP eventually */
+                                       args.v3.sInput.ucDispPllConfig |=
+                                               DISPPLL_CONFIG_SS_ENABLE;
+                                       if (mode->clock > 165000)
+                                               args.v3.sInput.ucDispPllConfig |=
+                                                       DISPPLL_CONFIG_DUAL_LINK;
+                               }
+                               atom_execute_table(rdev->mode_info.atom_context,
+                                                  index, (uint32_t *)&args);
+                               adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
+                               if (args.v3.sOutput.ucRefDiv) {
+                                       pll->flags |= RADEON_PLL_USE_REF_DIV;
+                                       pll->reference_div = args.v3.sOutput.ucRefDiv;
+                               }
+                               if (args.v3.sOutput.ucPostDiv) {
+                                       pll->flags |= RADEON_PLL_USE_POST_DIV;
+                                       pll->post_div = args.v3.sOutput.ucPostDiv;
+                               }
+                               break;
                        default:
                                DRM_ERROR("Unknown table version %d %d\n", frev, crev);
                                return adjusted_clock;
@@ -529,9 +574,47 @@ union set_pixel_clock {
        PIXEL_CLOCK_PARAMETERS v1;
        PIXEL_CLOCK_PARAMETERS_V2 v2;
        PIXEL_CLOCK_PARAMETERS_V3 v3;
+       PIXEL_CLOCK_PARAMETERS_V5 v5;
 };
 
-void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
+static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
+{
+       struct drm_device *dev = crtc->dev;
+       struct radeon_device *rdev = dev->dev_private;
+       u8 frev, crev;
+       int index;
+       union set_pixel_clock args;
+
+       memset(&args, 0, sizeof(args));
+
+       index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
+       atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
+                             &crev);
+
+       switch (frev) {
+       case 1:
+               switch (crev) {
+               case 5:
+                       /* if the default dcpll clock is specified,
+                        * SetPixelClock provides the dividers
+                        */
+                       args.v5.ucCRTC = ATOM_CRTC_INVALID;
+                       args.v5.usPixelClock = rdev->clock.default_dispclk;
+                       args.v5.ucPpll = ATOM_DCPLL;
+                       break;
+               default:
+                       DRM_ERROR("Unknown table version %d %d\n", frev, crev);
+                       return;
+               }
+               break;
+       default:
+               DRM_ERROR("Unknown table version %d %d\n", frev, crev);
+               return;
+       }
+       atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+}
+
+static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 {
        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
        struct drm_device *dev = crtc->dev;
@@ -545,12 +628,14 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
        u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
        struct radeon_pll *pll;
        u32 adjusted_clock;
+       int encoder_mode = 0;
 
        memset(&args, 0, sizeof(args));
 
        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
                if (encoder->crtc == crtc) {
                        radeon_encoder = to_radeon_encoder(encoder);
+                       encoder_mode = atombios_get_encoder_mode(encoder);
                        break;
                }
        }
@@ -558,10 +643,18 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
        if (!radeon_encoder)
                return;
 
-       if (radeon_crtc->crtc_id == 0)
+       switch (radeon_crtc->pll_id) {
+       case ATOM_PPLL1:
                pll = &rdev->clock.p1pll;
-       else
+               break;
+       case ATOM_PPLL2:
                pll = &rdev->clock.p2pll;
+               break;
+       case ATOM_DCPLL:
+       case ATOM_PPLL_INVALID:
+               pll = &rdev->clock.dcpll;
+               break;
+       }
 
        /* adjust pixel clock as needed */
        adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
@@ -582,8 +675,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
                        args.v1.usFbDiv = cpu_to_le16(fb_div);
                        args.v1.ucFracFbDiv = frac_fb_div;
                        args.v1.ucPostDiv = post_div;
-                       args.v1.ucPpll =
-                           radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
+                       args.v1.ucPpll = radeon_crtc->pll_id;
                        args.v1.ucCRTC = radeon_crtc->crtc_id;
                        args.v1.ucRefDivSrc = 1;
                        break;
@@ -593,8 +685,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
                        args.v2.usFbDiv = cpu_to_le16(fb_div);
                        args.v2.ucFracFbDiv = frac_fb_div;
                        args.v2.ucPostDiv = post_div;
-                       args.v2.ucPpll =
-                           radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
+                       args.v2.ucPpll = radeon_crtc->pll_id;
                        args.v2.ucCRTC = radeon_crtc->crtc_id;
                        args.v2.ucRefDivSrc = 1;
                        break;
@@ -604,12 +695,22 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
                        args.v3.usFbDiv = cpu_to_le16(fb_div);
                        args.v3.ucFracFbDiv = frac_fb_div;
                        args.v3.ucPostDiv = post_div;
-                       args.v3.ucPpll =
-                           radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
-                       args.v3.ucMiscInfo = (radeon_crtc->crtc_id << 2);
+                       args.v3.ucPpll = radeon_crtc->pll_id;
+                       args.v3.ucMiscInfo = (radeon_crtc->pll_id << 2);
                        args.v3.ucTransmitterId = radeon_encoder->encoder_id;
-                       args.v3.ucEncoderMode =
-                           atombios_get_encoder_mode(encoder);
+                       args.v3.ucEncoderMode = encoder_mode;
+                       break;
+               case 5:
+                       args.v5.ucCRTC = radeon_crtc->crtc_id;
+                       args.v5.usPixelClock = cpu_to_le16(mode->clock / 10);
+                       args.v5.ucRefDiv = ref_div;
+                       args.v5.usFbDiv = cpu_to_le16(fb_div);
+                       args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
+                       args.v5.ucPostDiv = post_div;
+                       args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
+                       args.v5.ucTransmitterID = radeon_encoder->encoder_id;
+                       args.v5.ucEncoderMode = encoder_mode;
+                       args.v5.ucPpll = radeon_crtc->pll_id;
                        break;
                default:
                        DRM_ERROR("Unknown table version %d %d\n", frev, crev);
@@ -624,6 +725,140 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }
 
+static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
+                                  struct drm_framebuffer *old_fb)
+{
+       struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+       struct drm_device *dev = crtc->dev;
+       struct radeon_device *rdev = dev->dev_private;
+       struct radeon_framebuffer *radeon_fb;
+       struct drm_gem_object *obj;
+       struct radeon_bo *rbo;
+       uint64_t fb_location;
+       uint32_t fb_format, fb_pitch_pixels, tiling_flags;
+       int r;
+
+       /* no fb bound */
+       if (!crtc->fb) {
+               DRM_DEBUG("No FB bound\n");
+               return 0;
+       }
+
+       radeon_fb = to_radeon_framebuffer(crtc->fb);
+
+       /* Pin framebuffer & get tilling informations */
+       obj = radeon_fb->obj;
+       rbo = obj->driver_private;
+       r = radeon_bo_reserve(rbo, false);
+       if (unlikely(r != 0))
+               return r;
+       r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
+       if (unlikely(r != 0)) {
+               radeon_bo_unreserve(rbo);
+               return -EINVAL;
+       }
+       radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
+       radeon_bo_unreserve(rbo);
+
+       switch (crtc->fb->bits_per_pixel) {
+       case 8:
+               fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
+                            EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
+               break;
+       case 15:
+               fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
+                            EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
+               break;
+       case 16:
+               fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
+                            EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
+               break;
+       case 24:
+       case 32:
+               fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
+                            EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
+               break;
+       default:
+               DRM_ERROR("Unsupported screen depth %d\n",
+                         crtc->fb->bits_per_pixel);
+               return -EINVAL;
+       }
+
+       switch (radeon_crtc->crtc_id) {
+       case 0:
+               WREG32(AVIVO_D1VGA_CONTROL, 0);
+               break;
+       case 1:
+               WREG32(AVIVO_D2VGA_CONTROL, 0);
+               break;
+       case 2:
+               WREG32(EVERGREEN_D3VGA_CONTROL, 0);
+               break;
+       case 3:
+               WREG32(EVERGREEN_D4VGA_CONTROL, 0);
+               break;
+       case 4:
+               WREG32(EVERGREEN_D5VGA_CONTROL, 0);
+               break;
+       case 5:
+               WREG32(EVERGREEN_D6VGA_CONTROL, 0);
+               break;
+       default:
+               break;
+       }
+
+       WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
+              upper_32_bits(fb_location));
+       WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
+              upper_32_bits(fb_location));
+       WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
+              (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
+       WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
+              (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
+       WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
+
+       WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
+       WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
+       WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
+       WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
+       WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
+       WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
+
+       fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
+       WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
+       WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
+
+       WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
+              crtc->mode.vdisplay);
+       x &= ~3;
+       y &= ~1;
+       WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
+              (x << 16) | y);
+       WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
+              (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
+
+       if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
+               WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
+                      EVERGREEN_INTERLEAVE_EN);
+       else
+               WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
+
+       if (old_fb && old_fb != crtc->fb) {
+               radeon_fb = to_radeon_framebuffer(old_fb);
+               rbo = radeon_fb->obj->driver_private;
+               r = radeon_bo_reserve(rbo, false);
+               if (unlikely(r != 0))
+                       return r;
+               radeon_bo_unpin(rbo);
+               radeon_bo_unreserve(rbo);
+       }
+
+       /* Bytes per pixel may have changed */
+       radeon_bandwidth_update(rdev);
+
+       return 0;
+}
+
 static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
                               struct drm_framebuffer *old_fb)
 {
@@ -761,7 +996,9 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
        struct drm_device *dev = crtc->dev;
        struct radeon_device *rdev = dev->dev_private;
 
-       if (ASIC_IS_AVIVO(rdev))
+       if (ASIC_IS_DCE4(rdev))
+               return evergreen_crtc_set_base(crtc, x, y, old_fb);
+       else if (ASIC_IS_AVIVO(rdev))
                return avivo_crtc_set_base(crtc, x, y, old_fb);
        else
                return radeon_crtc_set_base(crtc, x, y, old_fb);
@@ -791,6 +1028,46 @@ static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
        }
 }
 
+static int radeon_atom_pick_pll(struct drm_crtc *crtc)
+{
+       struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+       struct drm_device *dev = crtc->dev;
+       struct radeon_device *rdev = dev->dev_private;
+       struct drm_encoder *test_encoder;
+       struct drm_crtc *test_crtc;
+       uint32_t pll_in_use = 0;
+
+       if (ASIC_IS_DCE4(rdev)) {
+               /* if crtc is driving DP and we have an ext clock, use that */
+               list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
+                       if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
+                               if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
+                                       if (rdev->clock.dp_extclk)
+                                               return ATOM_PPLL_INVALID;
+                               }
+                       }
+               }
+
+               /* otherwise, pick one of the plls */
+               list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
+                       struct radeon_crtc *radeon_test_crtc;
+
+                       if (crtc == test_crtc)
+                               continue;
+
+                       radeon_test_crtc = to_radeon_crtc(test_crtc);
+                       if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
+                           (radeon_test_crtc->pll_id <= ATOM_PPLL2))
+                               pll_in_use |= (1 << radeon_test_crtc->pll_id);
+               }
+               if (!(pll_in_use & 1))
+                       return ATOM_PPLL1;
+               return ATOM_PPLL2;
+       } else
+               return radeon_crtc->crtc_id;
+
+}
+
 int atombios_crtc_mode_set(struct drm_crtc *crtc,
                           struct drm_display_mode *mode,
                           struct drm_display_mode *adjusted_mode,
@@ -802,19 +1079,27 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
 
        /* TODO color tiling */
 
+       /* pick pll */
+       radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
+
        atombios_set_ss(crtc, 0);
+       /* always set DCPLL */
+       if (ASIC_IS_DCE4(rdev))
+               atombios_crtc_set_dcpll(crtc);
        atombios_crtc_set_pll(crtc, adjusted_mode);
        atombios_set_ss(crtc, 1);
-       atombios_crtc_set_timing(crtc, adjusted_mode);
 
-       if (ASIC_IS_AVIVO(rdev))
-               atombios_crtc_set_base(crtc, x, y, old_fb);
+       if (ASIC_IS_DCE4(rdev))
+               atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
+       else if (ASIC_IS_AVIVO(rdev))
+               atombios_crtc_set_timing(crtc, adjusted_mode);
        else {
+               atombios_crtc_set_timing(crtc, adjusted_mode);
                if (radeon_crtc->crtc_id == 0)
                        atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
-               atombios_crtc_set_base(crtc, x, y, old_fb);
                radeon_legacy_atom_fixup(crtc);
        }
+       atombios_crtc_set_base(crtc, x, y, old_fb);
        atombios_overscan_setup(crtc, mode, adjusted_mode);
        atombios_scaler_setup(crtc);
        return 0;
@@ -854,8 +1139,37 @@ static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
 void radeon_atombios_init_crtc(struct drm_device *dev,
                               struct radeon_crtc *radeon_crtc)
 {
-       if (radeon_crtc->crtc_id == 1)
-               radeon_crtc->crtc_offset =
-                   AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
+       struct radeon_device *rdev = dev->dev_private;
+
+       if (ASIC_IS_DCE4(rdev)) {
+               switch (radeon_crtc->crtc_id) {
+               case 0:
+               default:
+                       radeon_crtc->crtc_id = EVERGREEN_CRTC0_REGISTER_OFFSET;
+                       break;
+               case 1:
+                       radeon_crtc->crtc_id = EVERGREEN_CRTC1_REGISTER_OFFSET;
+                       break;
+               case 2:
+                       radeon_crtc->crtc_id = EVERGREEN_CRTC2_REGISTER_OFFSET;
+                       break;
+               case 3:
+                       radeon_crtc->crtc_id = EVERGREEN_CRTC3_REGISTER_OFFSET;
+                       break;
+               case 4:
+                       radeon_crtc->crtc_id = EVERGREEN_CRTC4_REGISTER_OFFSET;
+                       break;
+               case 5:
+                       radeon_crtc->crtc_id = EVERGREEN_CRTC5_REGISTER_OFFSET;
+                       break;
+               }
+       } else {
+               if (radeon_crtc->crtc_id == 1)
+                       radeon_crtc->crtc_offset =
+                               AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
+               else
+                       radeon_crtc->crtc_offset = 0;
+       }
+       radeon_crtc->pll_id = -1;
        drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
 }
index 71060114d5deea4bf77293730dfae6ff63934495..0b6f2cef1c52aef505cfe0874df70778f85dccf1 100644 (file)
@@ -321,6 +321,10 @@ static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
                train_set[lane] = v | p;
 }
 
+union aux_channel_transaction {
+       PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
+       PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
+};
 
 /* radeon aux chan functions */
 bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
@@ -329,7 +333,7 @@ bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
 {
        struct drm_device *dev = chan->dev;
        struct radeon_device *rdev = dev->dev_private;
-       PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION args;
+       union aux_channel_transaction args;
        int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
        unsigned char *base;
 
@@ -339,29 +343,31 @@ bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
 
        memcpy(base, req_bytes, num_bytes);
 
-       args.lpAuxRequest = 0;
-       args.lpDataOut = 16;
-       args.ucDataOutLen = 0;
-       args.ucChannelID = chan->rec.i2c_id;
-       args.ucDelay = delay / 10;
+       args.v1.lpAuxRequest = 0;
+       args.v1.lpDataOut = 16;
+       args.v1.ucDataOutLen = 0;
+       args.v1.ucChannelID = chan->rec.i2c_id;
+       args.v1.ucDelay = delay / 10;
+       if (ASIC_IS_DCE4(rdev))
+               args.v2.ucHPD_ID = chan->rec.hpd_id;
 
        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 
-       if (args.ucReplyStatus) {
+       if (args.v1.ucReplyStatus) {
                DRM_DEBUG("failed to get auxch %02x%02x %02x %02x 0x%02x %02x\n",
                          req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3],
-                         chan->rec.i2c_id, args.ucReplyStatus);
+                         chan->rec.i2c_id, args.v1.ucReplyStatus);
                return false;
        }
 
-       if (args.ucDataOutLen && read_byte && read_buf_len) {
-               if (read_buf_len < args.ucDataOutLen) {
+       if (args.v1.ucDataOutLen && read_byte && read_buf_len) {
+               if (read_buf_len < args.v1.ucDataOutLen) {
                        DRM_ERROR("Buffer to small for return answer %d %d\n",
-                                 read_buf_len, args.ucDataOutLen);
+                                 read_buf_len, args.v1.ucDataOutLen);
                        return false;
                }
                {
-                       int len = min(read_buf_len, args.ucDataOutLen);
+                       int len = min(read_buf_len, args.v1.ucDataOutLen);
                        memcpy(read_byte, base + 16, len);
                }
        }
@@ -622,12 +628,19 @@ void dp_link_train(struct drm_encoder *encoder,
        dp_set_link_bw_lanes(radeon_connector, link_configuration);
        /* disable downspread on the sink */
        dp_set_downspread(radeon_connector, 0);
-       /* start training on the source */
-       radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_START,
-                                 dig_connector->dp_clock, enc_id, 0);
-       /* set training pattern 1 on the source */
-       radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
-                                 dig_connector->dp_clock, enc_id, 0);
+       if (ASIC_IS_DCE4(rdev)) {
+               /* start training on the source */
+               atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_START);
+               /* set training pattern 1 on the source */
+               atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1);
+       } else {
+               /* start training on the source */
+               radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_START,
+                                         dig_connector->dp_clock, enc_id, 0);
+               /* set training pattern 1 on the source */
+               radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
+                                         dig_connector->dp_clock, enc_id, 0);
+       }
 
        /* set initial vs/emph */
        memset(train_set, 0, 4);
@@ -687,8 +700,11 @@ void dp_link_train(struct drm_encoder *encoder,
        /* set training pattern 2 on the sink */
        dp_set_training(radeon_connector, DP_TRAINING_PATTERN_2);
        /* set training pattern 2 on the source */
-       radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
-                                 dig_connector->dp_clock, enc_id, 1);
+       if (ASIC_IS_DCE4(rdev))
+               atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2);
+       else
+               radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
+                                         dig_connector->dp_clock, enc_id, 1);
 
        /* channel equalization loop */
        tries = 0;
@@ -725,7 +741,11 @@ void dp_link_train(struct drm_encoder *encoder,
                          >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
 
        /* disable the training pattern on the sink */
-       dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
+       if (ASIC_IS_DCE4(rdev))
+               atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE);
+       else
+               radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
+                                         dig_connector->dp_clock, enc_id, 0);
 
        radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
                                  dig_connector->dp_clock, enc_id, 0);
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
new file mode 100644 (file)
index 0000000..c2f9752
--- /dev/null
@@ -0,0 +1,794 @@
+/*
+ * Copyright 2010 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Alex Deucher
+ */
+#include <linux/firmware.h>
+#include <linux/platform_device.h>
+#include "drmP.h"
+#include "radeon.h"
+#include "radeon_drm.h"
+#include "rv770d.h"
+#include "atom.h"
+#include "avivod.h"
+#include "evergreen_reg.h"
+
+static void evergreen_gpu_init(struct radeon_device *rdev);
+void evergreen_fini(struct radeon_device *rdev);
+
+bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
+{
+       bool connected = false;
+       /* XXX */
+       return connected;
+}
+
+void evergreen_hpd_set_polarity(struct radeon_device *rdev,
+                               enum radeon_hpd_id hpd)
+{
+       /* XXX */
+}
+
+void evergreen_hpd_init(struct radeon_device *rdev)
+{
+       /* XXX */
+}
+
+
+void evergreen_bandwidth_update(struct radeon_device *rdev)
+{
+       /* XXX */
+}
+
+void evergreen_hpd_fini(struct radeon_device *rdev)
+{
+       /* XXX */
+}
+
+static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
+{
+       unsigned i;
+       u32 tmp;
+
+       for (i = 0; i < rdev->usec_timeout; i++) {
+               /* read MC_STATUS */
+               tmp = RREG32(SRBM_STATUS) & 0x1F00;
+               if (!tmp)
+                       return 0;
+               udelay(1);
+       }
+       return -1;
+}
+
+/*
+ * GART
+ */
+int evergreen_pcie_gart_enable(struct radeon_device *rdev)
+{
+       u32 tmp;
+       int r, i;
+
+       if (rdev->gart.table.vram.robj == NULL) {
+               dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
+               return -EINVAL;
+       }
+       r = radeon_gart_table_vram_pin(rdev);
+       if (r)
+               return r;
+       /* Setup L2 cache */
+       WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
+                               ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
+                               EFFECTIVE_L2_QUEUE_SIZE(7));
+       WREG32(VM_L2_CNTL2, 0);
+       WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
+       /* Setup TLB control */
+       tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
+               SYSTEM_ACCESS_MODE_NOT_IN_SYS |
+               SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
+               EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
+       WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
+       WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
+       WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
+       WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
+       WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
+       WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
+       WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
+       WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
+       WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
+       WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
+       WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
+                               RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
+       WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
+                       (u32)(rdev->dummy_page.addr >> 12));
+       for (i = 1; i < 7; i++)
+               WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
+
+       r600_pcie_gart_tlb_flush(rdev);
+       rdev->gart.ready = true;
+       return 0;
+}
+
+void evergreen_pcie_gart_disable(struct radeon_device *rdev)
+{
+       u32 tmp;
+       int i, r;
+
+       /* Disable all tables */
+       for (i = 0; i < 7; i++)
+               WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
+
+       /* Setup L2 cache */
+       WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
+                               EFFECTIVE_L2_QUEUE_SIZE(7));
+       WREG32(VM_L2_CNTL2, 0);
+       WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
+       /* Setup TLB control */
+       tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
+       WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
+       WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
+       WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
+       WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
+       WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
+       WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
+       WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
+       if (rdev->gart.table.vram.robj) {
+               r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
+               if (likely(r == 0)) {
+                       radeon_bo_kunmap(rdev->gart.table.vram.robj);
+                       radeon_bo_unpin(rdev->gart.table.vram.robj);
+                       radeon_bo_unreserve(rdev->gart.table.vram.robj);
+               }
+       }
+}
+
+void evergreen_pcie_gart_fini(struct radeon_device *rdev)
+{
+       evergreen_pcie_gart_disable(rdev);
+       radeon_gart_table_vram_free(rdev);
+       radeon_gart_fini(rdev);
+}
+
+
+void evergreen_agp_enable(struct radeon_device *rdev)
+{
+       u32 tmp;
+       int i;
+
+       /* Setup L2 cache */
+       WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
+                               ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
+                               EFFECTIVE_L2_QUEUE_SIZE(7));
+       WREG32(VM_L2_CNTL2, 0);
+       WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
+       /* Setup TLB control */
+       tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
+               SYSTEM_ACCESS_MODE_NOT_IN_SYS |
+               SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
+               EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
+       WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
+       WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
+       WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
+       WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
+       WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
+       WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
+       WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
+       for (i = 0; i < 7; i++)
+               WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
+}
+
+static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
+{
+       save->vga_control[0] = RREG32(D1VGA_CONTROL);
+       save->vga_control[1] = RREG32(D2VGA_CONTROL);
+       save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
+       save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
+       save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
+       save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
+       save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
+       save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
+       save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
+       save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
+       save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
+       save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
+       save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
+       save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
+
+       /* Stop all video */
+       WREG32(VGA_RENDER_CONTROL, 0);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
+       WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
+       WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
+       WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
+       WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
+       WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
+       WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
+
+       WREG32(D1VGA_CONTROL, 0);
+       WREG32(D2VGA_CONTROL, 0);
+       WREG32(EVERGREEN_D3VGA_CONTROL, 0);
+       WREG32(EVERGREEN_D4VGA_CONTROL, 0);
+       WREG32(EVERGREEN_D5VGA_CONTROL, 0);
+       WREG32(EVERGREEN_D6VGA_CONTROL, 0);
+}
+
+static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
+{
+       WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
+              upper_32_bits(rdev->mc.vram_start));
+       WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
+              upper_32_bits(rdev->mc.vram_start));
+       WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
+              (u32)rdev->mc.vram_start);
+       WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
+              (u32)rdev->mc.vram_start);
+
+       WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
+              upper_32_bits(rdev->mc.vram_start));
+       WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
+              upper_32_bits(rdev->mc.vram_start));
+       WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
+              (u32)rdev->mc.vram_start);
+       WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
+              (u32)rdev->mc.vram_start);
+
+       WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
+              upper_32_bits(rdev->mc.vram_start));
+       WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
+              upper_32_bits(rdev->mc.vram_start));
+       WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
+              (u32)rdev->mc.vram_start);
+       WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
+              (u32)rdev->mc.vram_start);
+
+       WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
+              upper_32_bits(rdev->mc.vram_start));
+       WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
+              upper_32_bits(rdev->mc.vram_start));
+       WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
+              (u32)rdev->mc.vram_start);
+       WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
+              (u32)rdev->mc.vram_start);
+
+       WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
+              upper_32_bits(rdev->mc.vram_start));
+       WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
+              upper_32_bits(rdev->mc.vram_start));
+       WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
+              (u32)rdev->mc.vram_start);
+       WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
+              (u32)rdev->mc.vram_start);
+
+       WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
+              upper_32_bits(rdev->mc.vram_start));
+       WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
+              upper_32_bits(rdev->mc.vram_start));
+       WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
+              (u32)rdev->mc.vram_start);
+       WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
+              (u32)rdev->mc.vram_start);
+
+       WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
+       WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
+       /* Unlock host access */
+       WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
+       mdelay(1);
+       /* Restore video state */
+       WREG32(D1VGA_CONTROL, save->vga_control[0]);
+       WREG32(D2VGA_CONTROL, save->vga_control[1]);
+       WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
+       WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
+       WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
+       WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
+       WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
+       WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
+       WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
+       WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
+       WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
+       WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
+       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
+       WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
+}
+
+static void evergreen_mc_program(struct radeon_device *rdev)
+{
+       struct evergreen_mc_save save;
+       u32 tmp;
+       int i, j;
+
+       /* Initialize HDP */
+       for (i = 0, j = 0; i < 32; i++, j += 0x18) {
+               WREG32((0x2c14 + j), 0x00000000);
+               WREG32((0x2c18 + j), 0x00000000);
+               WREG32((0x2c1c + j), 0x00000000);
+               WREG32((0x2c20 + j), 0x00000000);
+               WREG32((0x2c24 + j), 0x00000000);
+       }
+       WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
+
+       evergreen_mc_stop(rdev, &save);
+       if (evergreen_mc_wait_for_idle(rdev)) {
+               dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
+       }
+       /* Lockout access through VGA aperture*/
+       WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
+       /* Update configuration */
+       if (rdev->flags & RADEON_IS_AGP) {
+               if (rdev->mc.vram_start < rdev->mc.gtt_start) {
+                       /* VRAM before AGP */
+                       WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
+                               rdev->mc.vram_start >> 12);
+                       WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+                               rdev->mc.gtt_end >> 12);
+               } else {
+                       /* VRAM after AGP */
+                       WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
+                               rdev->mc.gtt_start >> 12);
+                       WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+                               rdev->mc.vram_end >> 12);
+               }
+       } else {
+               WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
+                       rdev->mc.vram_start >> 12);
+               WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+                       rdev->mc.vram_end >> 12);
+       }
+       WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
+       tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
+       tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
+       WREG32(MC_VM_FB_LOCATION, tmp);
+       WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
+       WREG32(HDP_NONSURFACE_INFO, (2 << 7));
+       WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
+       if (rdev->flags & RADEON_IS_AGP) {
+               WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
+               WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
+               WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
+       } else {
+               WREG32(MC_VM_AGP_BASE, 0);
+               WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
+               WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
+       }
+       if (evergreen_mc_wait_for_idle(rdev)) {
+               dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
+       }
+       evergreen_mc_resume(rdev, &save);
+       /* we need to own VRAM, so turn off the VGA renderer here
+        * to stop it overwriting our objects */
+       rv515_vga_render_disable(rdev);
+}
+
+#if 0
+/*
+ * CP.
+ */
+static void evergreen_cp_stop(struct radeon_device *rdev)
+{
+       /* XXX */
+}
+
+
+static int evergreen_cp_load_microcode(struct radeon_device *rdev)
+{
+       /* XXX */
+
+       return 0;
+}
+
+
+/*
+ * Core functions
+ */
+static u32 evergreen_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
+                                                 u32 num_backends,
+                                                 u32 backend_disable_mask)
+{
+       u32 backend_map = 0;
+
+       return backend_map;
+}
+#endif
+
+static void evergreen_gpu_init(struct radeon_device *rdev)
+{
+       /* XXX */
+}
+
+int evergreen_mc_init(struct radeon_device *rdev)
+{
+       fixed20_12 a;
+       u32 tmp;
+       int chansize, numchan;
+       int r;
+
+       /* Get VRAM informations */
+       rdev->mc.vram_is_ddr = true;
+       tmp = RREG32(MC_ARB_RAMCFG);
+       if (tmp & CHANSIZE_OVERRIDE) {
+               chansize = 16;
+       } else if (tmp & CHANSIZE_MASK) {
+               chansize = 64;
+       } else {
+               chansize = 32;
+       }
+       tmp = RREG32(MC_SHARED_CHMAP);
+       switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
+       case 0:
+       default:
+               numchan = 1;
+               break;
+       case 1:
+               numchan = 2;
+               break;
+       case 2:
+               numchan = 4;
+               break;
+       case 3:
+               numchan = 8;
+               break;
+       }
+       rdev->mc.vram_width = numchan * chansize;
+       /* Could aper size report 0 ? */
+       rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
+       rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
+       /* Setup GPU memory space */
+       /* size in MB on evergreen */
+       rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
+       rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
+
+       if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
+               rdev->mc.mc_vram_size = rdev->mc.aper_size;
+
+       if (rdev->mc.real_vram_size > rdev->mc.aper_size)
+               rdev->mc.real_vram_size = rdev->mc.aper_size;
+
+       if (rdev->flags & RADEON_IS_AGP) {
+               r = radeon_agp_init(rdev);
+               if (r)
+                       return r;
+               /* gtt_size is setup by radeon_agp_init */
+               rdev->mc.gtt_location = rdev->mc.agp_base;
+               tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
+               /* Try to put vram before or after AGP because we
+                * we want SYSTEM_APERTURE to cover both VRAM and
+                * AGP so that GPU can catch out of VRAM/AGP access
+                */
+               if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
+                       /* Enought place before */
+                       rdev->mc.vram_location = rdev->mc.gtt_location -
+                                                       rdev->mc.mc_vram_size;
+               } else if (tmp > rdev->mc.mc_vram_size) {
+                       /* Enought place after */
+                       rdev->mc.vram_location = rdev->mc.gtt_location +
+                                                       rdev->mc.gtt_size;
+               } else {
+                       /* Try to setup VRAM then AGP might not
+                        * not work on some card
+                        */
+                       rdev->mc.vram_location = 0x00000000UL;
+                       rdev->mc.gtt_location = rdev->mc.mc_vram_size;
+               }
+       } else {
+               rdev->mc.vram_location = 0x00000000UL;
+               rdev->mc.gtt_location = rdev->mc.mc_vram_size;
+               rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+       }
+       rdev->mc.vram_start = rdev->mc.vram_location;
+       rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
+       rdev->mc.gtt_start = rdev->mc.gtt_location;
+       rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
+       /* FIXME: we should enforce default clock in case GPU is not in
+        * default setup
+        */
+       a.full = rfixed_const(100);
+       rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
+       rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
+       return 0;
+}
+int evergreen_gpu_reset(struct radeon_device *rdev)
+{
+       /* FIXME: implement for evergreen */
+       return 0;
+}
+
+static int evergreen_startup(struct radeon_device *rdev)
+{
+#if 0
+       int r;
+
+       if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
+               r = r600_init_microcode(rdev);
+               if (r) {
+                       DRM_ERROR("Failed to load firmware!\n");
+                       return r;
+               }
+       }
+#endif
+       evergreen_mc_program(rdev);
+#if 0
+       if (rdev->flags & RADEON_IS_AGP) {
+               evergreem_agp_enable(rdev);
+       } else {
+               r = evergreen_pcie_gart_enable(rdev);
+               if (r)
+                       return r;
+       }
+#endif
+       evergreen_gpu_init(rdev);
+#if 0
+       if (!rdev->r600_blit.shader_obj) {
+               r = r600_blit_init(rdev);
+               if (r) {
+                       DRM_ERROR("radeon: failed blitter (%d).\n", r);
+                       return r;
+               }
+       }
+
+       r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
+       if (unlikely(r != 0))
+               return r;
+       r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
+                       &rdev->r600_blit.shader_gpu_addr);
+       radeon_bo_unreserve(rdev->r600_blit.shader_obj);
+       if (r) {
+               DRM_ERROR("failed to pin blit object %d\n", r);
+               return r;
+       }
+
+       /* Enable IRQ */
+       r = r600_irq_init(rdev);
+       if (r) {
+               DRM_ERROR("radeon: IH init failed (%d).\n", r);
+               radeon_irq_kms_fini(rdev);
+               return r;
+       }
+       r600_irq_set(rdev);
+
+       r = radeon_ring_init(rdev, rdev->cp.ring_size);
+       if (r)
+               return r;
+       r = evergreen_cp_load_microcode(rdev);
+       if (r)
+               return r;
+       r = r600_cp_resume(rdev);
+       if (r)
+               return r;
+       /* write back buffer are not vital so don't worry about failure */
+       r600_wb_enable(rdev);
+#endif
+       return 0;
+}
+
+int evergreen_resume(struct radeon_device *rdev)
+{
+       int r;
+
+       /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
+        * posting will perform necessary task to bring back GPU into good
+        * shape.
+        */
+       /* post card */
+       atom_asic_init(rdev->mode_info.atom_context);
+       /* Initialize clocks */
+       r = radeon_clocks_init(rdev);
+       if (r) {
+               return r;
+       }
+
+       r = evergreen_startup(rdev);
+       if (r) {
+               DRM_ERROR("r600 startup failed on resume\n");
+               return r;
+       }
+#if 0
+       r = r600_ib_test(rdev);
+       if (r) {
+               DRM_ERROR("radeon: failled testing IB (%d).\n", r);
+               return r;
+       }
+#endif
+       return r;
+
+}
+
+int evergreen_suspend(struct radeon_device *rdev)
+{
+#if 0
+       int r;
+
+       /* FIXME: we should wait for ring to be empty */
+       r700_cp_stop(rdev);
+       rdev->cp.ready = false;
+       r600_wb_disable(rdev);
+       evergreen_pcie_gart_disable(rdev);
+       /* unpin shaders bo */
+       r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
+       if (likely(r == 0)) {
+               radeon_bo_unpin(rdev->r600_blit.shader_obj);
+               radeon_bo_unreserve(rdev->r600_blit.shader_obj);
+       }
+#endif
+       return 0;
+}
+
+static bool evergreen_card_posted(struct radeon_device *rdev)
+{
+       u32 reg;
+
+       /* first check CRTCs */
+       reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
+               RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
+               RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
+               RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
+               RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
+               RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
+       if (reg & EVERGREEN_CRTC_MASTER_EN)
+               return true;
+
+       /* then check MEM_SIZE, in case the crtcs are off */
+       if (RREG32(CONFIG_MEMSIZE))
+               return true;
+
+       return false;
+}
+
+/* Plan is to move initialization in that function and use
+ * helper function so that radeon_device_init pretty much
+ * do nothing more than calling asic specific function. This
+ * should also allow to remove a bunch of callback function
+ * like vram_info.
+ */
+int evergreen_init(struct radeon_device *rdev)
+{
+       int r;
+
+       r = radeon_dummy_page_init(rdev);
+       if (r)
+               return r;
+       /* This don't do much */
+       r = radeon_gem_init(rdev);
+       if (r)
+               return r;
+       /* Read BIOS */
+       if (!radeon_get_bios(rdev)) {
+               if (ASIC_IS_AVIVO(rdev))
+                       return -EINVAL;
+       }
+       /* Must be an ATOMBIOS */
+       if (!rdev->is_atom_bios) {
+               dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
+               return -EINVAL;
+       }
+       r = radeon_atombios_init(rdev);
+       if (r)
+               return r;
+       /* Post card if necessary */
+       if (!evergreen_card_posted(rdev)) {
+               if (!rdev->bios) {
+                       dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
+                       return -EINVAL;
+               }
+               DRM_INFO("GPU not posted. posting now...\n");
+               atom_asic_init(rdev->mode_info.atom_context);
+       }
+       /* Initialize scratch registers */
+       r600_scratch_init(rdev);
+       /* Initialize surface registers */
+       radeon_surface_init(rdev);
+       /* Initialize clocks */
+       radeon_get_clock_info(rdev->ddev);
+       r = radeon_clocks_init(rdev);
+       if (r)
+               return r;
+       /* Initialize power management */
+       radeon_pm_init(rdev);
+       /* Fence driver */
+       r = radeon_fence_driver_init(rdev);
+       if (r)
+               return r;
+       r = evergreen_mc_init(rdev);
+       if (r)
+               return r;
+       /* Memory manager */
+       r = radeon_bo_init(rdev);
+       if (r)
+               return r;
+#if 0
+       r = radeon_irq_kms_init(rdev);
+       if (r)
+               return r;
+
+       rdev->cp.ring_obj = NULL;
+       r600_ring_init(rdev, 1024 * 1024);
+
+       rdev->ih.ring_obj = NULL;
+       r600_ih_ring_init(rdev, 64 * 1024);
+
+       r = r600_pcie_gart_init(rdev);
+       if (r)
+               return r;
+#endif
+       rdev->accel_working = false;
+       r = evergreen_startup(rdev);
+       if (r) {
+               evergreen_suspend(rdev);
+               /*r600_wb_fini(rdev);*/
+               /*radeon_ring_fini(rdev);*/
+               /*evergreen_pcie_gart_fini(rdev);*/
+               rdev->accel_working = false;
+       }
+       if (rdev->accel_working) {
+               r = radeon_ib_pool_init(rdev);
+               if (r) {
+                       DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
+                       rdev->accel_working = false;
+               }
+               r = r600_ib_test(rdev);
+               if (r) {
+                       DRM_ERROR("radeon: failed testing IB (%d).\n", r);
+                       rdev->accel_working = false;
+               }
+       }
+       return 0;
+}
+
+void evergreen_fini(struct radeon_device *rdev)
+{
+       evergreen_suspend(rdev);
+#if 0
+       r600_blit_fini(rdev);
+       r600_irq_fini(rdev);
+       radeon_irq_kms_fini(rdev);
+       radeon_ring_fini(rdev);
+       r600_wb_fini(rdev);
+       evergreen_pcie_gart_fini(rdev);
+#endif
+       radeon_gem_fini(rdev);
+       radeon_fence_driver_fini(rdev);
+       radeon_clocks_fini(rdev);
+       radeon_agp_fini(rdev);
+       radeon_bo_fini(rdev);
+       radeon_atombios_fini(rdev);
+       kfree(rdev->bios);
+       rdev->bios = NULL;
+       radeon_dummy_page_fini(rdev);
+}
diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h
new file mode 100644 (file)
index 0000000..f7c7c96
--- /dev/null
@@ -0,0 +1,176 @@
+/*
+ * Copyright 2010 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Alex Deucher
+ */
+#ifndef __EVERGREEN_REG_H__
+#define __EVERGREEN_REG_H__
+
+/* evergreen */
+#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS               0x310
+#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH          0x324
+#define EVERGREEN_D3VGA_CONTROL                         0x3e0
+#define EVERGREEN_D4VGA_CONTROL                         0x3e4
+#define EVERGREEN_D5VGA_CONTROL                         0x3e8
+#define EVERGREEN_D6VGA_CONTROL                         0x3ec
+
+#define EVERGREEN_P1PLL_SS_CNTL                         0x414
+#define EVERGREEN_P2PLL_SS_CNTL                         0x454
+#       define EVERGREEN_PxPLL_SS_EN                    (1 << 12)
+/* GRPH blocks at 0x6800, 0x7400, 0x10000, 0x10c00, 0x11800, 0x12400 */
+#define EVERGREEN_GRPH_ENABLE                           0x6800
+#define EVERGREEN_GRPH_CONTROL                          0x6804
+#       define EVERGREEN_GRPH_DEPTH(x)                  (((x) & 0x3) << 0)
+#       define EVERGREEN_GRPH_DEPTH_8BPP                0
+#       define EVERGREEN_GRPH_DEPTH_16BPP               1
+#       define EVERGREEN_GRPH_DEPTH_32BPP               2
+#       define EVERGREEN_GRPH_FORMAT(x)                 (((x) & 0x7) << 8)
+/* 8 BPP */
+#       define EVERGREEN_GRPH_FORMAT_INDEXED            0
+/* 16 BPP */
+#       define EVERGREEN_GRPH_FORMAT_ARGB1555           0
+#       define EVERGREEN_GRPH_FORMAT_ARGB565            1
+#       define EVERGREEN_GRPH_FORMAT_ARGB4444           2
+#       define EVERGREEN_GRPH_FORMAT_AI88               3
+#       define EVERGREEN_GRPH_FORMAT_MONO16             4
+#       define EVERGREEN_GRPH_FORMAT_BGRA5551           5
+/* 32 BPP */
+#       define EVERGREEN_GRPH_FORMAT_ARGB8888           0
+#       define EVERGREEN_GRPH_FORMAT_ARGB2101010        1
+#       define EVERGREEN_GRPH_FORMAT_32BPP_DIG          2
+#       define EVERGREEN_GRPH_FORMAT_8B_ARGB2101010     3
+#       define EVERGREEN_GRPH_FORMAT_BGRA1010102        4
+#       define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102     5
+#       define EVERGREEN_GRPH_FORMAT_RGB111110          6
+#       define EVERGREEN_GRPH_FORMAT_BGR101111          7
+#define EVERGREEN_GRPH_SWAP_CONTROL                     0x680c
+#       define EVERGREEN_GRPH_ENDIAN_SWAP(x)            (((x) & 0x3) << 0)
+#       define EVERGREEN_GRPH_ENDIAN_NONE               0
+#       define EVERGREEN_GRPH_ENDIAN_8IN16              1
+#       define EVERGREEN_GRPH_ENDIAN_8IN32              2
+#       define EVERGREEN_GRPH_ENDIAN_8IN64              3
+#       define EVERGREEN_GRPH_RED_CROSSBAR(x)           (((x) & 0x3) << 4)
+#       define EVERGREEN_GRPH_RED_SEL_R                 0
+#       define EVERGREEN_GRPH_RED_SEL_G                 1
+#       define EVERGREEN_GRPH_RED_SEL_B                 2
+#       define EVERGREEN_GRPH_RED_SEL_A                 3
+#       define EVERGREEN_GRPH_GREEN_CROSSBAR(x)         (((x) & 0x3) << 6)
+#       define EVERGREEN_GRPH_GREEN_SEL_G               0
+#       define EVERGREEN_GRPH_GREEN_SEL_B               1
+#       define EVERGREEN_GRPH_GREEN_SEL_A               2
+#       define EVERGREEN_GRPH_GREEN_SEL_R               3
+#       define EVERGREEN_GRPH_BLUE_CROSSBAR(x)          (((x) & 0x3) << 8)
+#       define EVERGREEN_GRPH_BLUE_SEL_B                0
+#       define EVERGREEN_GRPH_BLUE_SEL_A                1
+#       define EVERGREEN_GRPH_BLUE_SEL_R                2
+#       define EVERGREEN_GRPH_BLUE_SEL_G                3
+#       define EVERGREEN_GRPH_ALPHA_CROSSBAR(x)         (((x) & 0x3) << 10)
+#       define EVERGREEN_GRPH_ALPHA_SEL_A               0
+#       define EVERGREEN_GRPH_ALPHA_SEL_R               1
+#       define EVERGREEN_GRPH_ALPHA_SEL_G               2
+#       define EVERGREEN_GRPH_ALPHA_SEL_B               3
+#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS          0x6810
+#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS        0x6814
+#       define EVERGREEN_GRPH_DFQ_ENABLE                (1 << 0)
+#       define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK      0xffffff00
+#define EVERGREEN_GRPH_PITCH                            0x6818
+#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH     0x681c
+#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH   0x6820
+#define EVERGREEN_GRPH_SURFACE_OFFSET_X                 0x6824
+#define EVERGREEN_GRPH_SURFACE_OFFSET_Y                 0x6828
+#define EVERGREEN_GRPH_X_START                          0x682c
+#define EVERGREEN_GRPH_Y_START                          0x6830
+#define EVERGREEN_GRPH_X_END                            0x6834
+#define EVERGREEN_GRPH_Y_END                            0x6838
+
+/* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */
+#define EVERGREEN_CUR_CONTROL                           0x6998
+#       define EVERGREEN_CURSOR_EN                      (1 << 0)
+#       define EVERGREEN_CURSOR_MODE(x)                 (((x) & 0x3) << 8)
+#       define EVERGREEN_CURSOR_MONO                    0
+#       define EVERGREEN_CURSOR_24_1                    1
+#       define EVERGREEN_CURSOR_24_8_PRE_MULT           2
+#       define EVERGREEN_CURSOR_24_8_UNPRE_MULT         3
+#       define EVERGREEN_CURSOR_2X_MAGNIFY              (1 << 16)
+#       define EVERGREEN_CURSOR_FORCE_MC_ON             (1 << 20)
+#       define EVERGREEN_CURSOR_URGENT_CONTROL(x)       (((x) & 0x7) << 24)
+#       define EVERGREEN_CURSOR_URGENT_ALWAYS           0
+#       define EVERGREEN_CURSOR_URGENT_1_8              1
+#       define EVERGREEN_CURSOR_URGENT_1_4              2
+#       define EVERGREEN_CURSOR_URGENT_3_8              3
+#       define EVERGREEN_CURSOR_URGENT_1_2              4
+#define EVERGREEN_CUR_SURFACE_ADDRESS                   0x699c
+#       define EVERGREEN_CUR_SURFACE_ADDRESS_MASK       0xfffff000
+#define EVERGREEN_CUR_SIZE                              0x69a0
+#define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH              0x69a4
+#define EVERGREEN_CUR_POSITION                          0x69a8
+#define EVERGREEN_CUR_HOT_SPOT                          0x69ac
+#define EVERGREEN_CUR_COLOR1                            0x69b0
+#define EVERGREEN_CUR_COLOR2                            0x69b4
+#define EVERGREEN_CUR_UPDATE                            0x69b8
+#       define EVERGREEN_CURSOR_UPDATE_PENDING          (1 << 0)
+#       define EVERGREEN_CURSOR_UPDATE_TAKEN            (1 << 1)
+#       define EVERGREEN_CURSOR_UPDATE_LOCK             (1 << 16)
+#       define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
+
+/* LUT blocks at 0x69e0, 0x75e0, 0x101e0, 0x10de0, 0x119e0, 0x125e0 */
+#define EVERGREEN_DC_LUT_RW_MODE                        0x69e0
+#define EVERGREEN_DC_LUT_RW_INDEX                       0x69e4
+#define EVERGREEN_DC_LUT_SEQ_COLOR                      0x69e8
+#define EVERGREEN_DC_LUT_PWL_DATA                       0x69ec
+#define EVERGREEN_DC_LUT_30_COLOR                       0x69f0
+#define EVERGREEN_DC_LUT_VGA_ACCESS_ENABLE              0x69f4
+#define EVERGREEN_DC_LUT_WRITE_EN_MASK                  0x69f8
+#define EVERGREEN_DC_LUT_AUTOFILL                       0x69fc
+#define EVERGREEN_DC_LUT_CONTROL                        0x6a00
+#define EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE              0x6a04
+#define EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN             0x6a08
+#define EVERGREEN_DC_LUT_BLACK_OFFSET_RED               0x6a0c
+#define EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE              0x6a10
+#define EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN             0x6a14
+#define EVERGREEN_DC_LUT_WHITE_OFFSET_RED               0x6a18
+
+#define EVERGREEN_DATA_FORMAT                           0x6b00
+#       define EVERGREEN_INTERLEAVE_EN                  (1 << 0)
+#define EVERGREEN_DESKTOP_HEIGHT                        0x6b04
+
+#define EVERGREEN_VIEWPORT_START                        0x6d70
+#define EVERGREEN_VIEWPORT_SIZE                         0x6d74
+
+/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */
+#define EVERGREEN_CRTC0_REGISTER_OFFSET                 (0x6df0 - 0x6df0)
+#define EVERGREEN_CRTC1_REGISTER_OFFSET                 (0x79f0 - 0x6df0)
+#define EVERGREEN_CRTC2_REGISTER_OFFSET                 (0x105f0 - 0x6df0)
+#define EVERGREEN_CRTC3_REGISTER_OFFSET                 (0x111f0 - 0x6df0)
+#define EVERGREEN_CRTC4_REGISTER_OFFSET                 (0x11df0 - 0x6df0)
+#define EVERGREEN_CRTC5_REGISTER_OFFSET                 (0x129f0 - 0x6df0)
+
+/* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */
+#define EVERGREEN_CRTC_CONTROL                          0x6e70
+#       define EVERGREEN_CRTC_MASTER_EN                 (1 << 0)
+#define EVERGREEN_CRTC_UPDATE_LOCK                      0x6ed4
+
+#define EVERGREEN_DC_GPIO_HPD_MASK                      0x64b0
+#define EVERGREEN_DC_GPIO_HPD_A                         0x64b4
+#define EVERGREEN_DC_GPIO_HPD_EN                        0x64b8
+#define EVERGREEN_DC_GPIO_HPD_Y                         0x64bc
+
+#endif
index b519d7db2dcba41b1ba7f67553be7d7385864a46..a7a96a2408440052cde6c43aa905764a6c34592d 100644 (file)
@@ -138,11 +138,14 @@ void radeon_dummy_page_fini(struct radeon_device *rdev);
 struct radeon_clock {
        struct radeon_pll p1pll;
        struct radeon_pll p2pll;
+       struct radeon_pll dcpll;
        struct radeon_pll spll;
        struct radeon_pll mpll;
        /* 10 Khz units */
        uint32_t default_mclk;
        uint32_t default_sclk;
+       uint32_t default_dispclk;
+       uint32_t dp_extclk;
 };
 
 /*
@@ -1062,7 +1065,7 @@ void r100_pll_errata_after_index(struct radeon_device *rdev);
 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
-
+#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
 
 /*
  * BIOS helpers.
@@ -1296,6 +1299,14 @@ extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
                                            uint8_t status_bits,
                                            uint8_t category_code);
 
+/* evergreen */
+struct evergreen_mc_save {
+       u32 vga_control[6];
+       u32 vga_render_control;
+       u32 vga_hdp_control;
+       u32 crtc_control[6];
+};
+
 #include "radeon_object.h"
 
 #endif
index 3f3c7a2169f18a962f1848ccf16f0562a22046fc..4b0cb67a379a32691bd776d109ec80e5513f9990 100644 (file)
@@ -606,4 +606,54 @@ static struct radeon_asic rv770_asic = {
        .ioctl_wait_idle = r600_ioctl_wait_idle,
 };
 
+/*
+ * evergreen
+ */
+int evergreen_init(struct radeon_device *rdev);
+void evergreen_fini(struct radeon_device *rdev);
+int evergreen_suspend(struct radeon_device *rdev);
+int evergreen_resume(struct radeon_device *rdev);
+int evergreen_gpu_reset(struct radeon_device *rdev);
+void evergreen_bandwidth_update(struct radeon_device *rdev);
+void evergreen_hpd_init(struct radeon_device *rdev);
+void evergreen_hpd_fini(struct radeon_device *rdev);
+bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
+void evergreen_hpd_set_polarity(struct radeon_device *rdev,
+                               enum radeon_hpd_id hpd);
+
+static struct radeon_asic evergreen_asic = {
+       .init = &evergreen_init,
+       .fini = &evergreen_fini,
+       .suspend = &evergreen_suspend,
+       .resume = &evergreen_resume,
+       .cp_commit = NULL,
+       .gpu_reset = &evergreen_gpu_reset,
+       .vga_set_state = &r600_vga_set_state,
+       .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
+       .gart_set_page = &rs600_gart_set_page,
+       .ring_test = NULL,
+       .ring_ib_execute = NULL,
+       .irq_set = NULL,
+       .irq_process = NULL,
+       .get_vblank_counter = NULL,
+       .fence_ring_emit = NULL,
+       .cs_parse = NULL,
+       .copy_blit = NULL,
+       .copy_dma = NULL,
+       .copy = NULL,
+       .get_engine_clock = &radeon_atom_get_engine_clock,
+       .set_engine_clock = &radeon_atom_set_engine_clock,
+       .get_memory_clock = &radeon_atom_get_memory_clock,
+       .set_memory_clock = &radeon_atom_set_memory_clock,
+       .set_pcie_lanes = NULL,
+       .set_clock_gating = NULL,
+       .set_surface_reg = r600_set_surface_reg,
+       .clear_surface_reg = r600_clear_surface_reg,
+       .bandwidth_update = &evergreen_bandwidth_update,
+       .hpd_init = &evergreen_hpd_init,
+       .hpd_fini = &evergreen_hpd_fini,
+       .hpd_sense = &evergreen_hpd_sense,
+       .hpd_set_polarity = &evergreen_hpd_set_polarity,
+};
+
 #endif
index c3198453528fc2d82c917a58fb65ff11c7b0f2ed..4f7dbce9883a4bce41754c59a5facfa86edbf7b6 100644 (file)
@@ -159,8 +159,15 @@ static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device
                                                            struct radeon_gpio_rec *gpio)
 {
        struct radeon_hpd hpd;
+       u32 reg;
+
+       if (ASIC_IS_DCE4(rdev))
+               reg = EVERGREEN_DC_GPIO_HPD_A;
+       else
+               reg = AVIVO_DC_GPIO_HPD_A;
+
        hpd.gpio = *gpio;
-       if (gpio->reg == AVIVO_DC_GPIO_HPD_A) {
+       if (gpio->reg == reg) {
                switch(gpio->mask) {
                case (1 << 0):
                        hpd.hpd = RADEON_HPD_1;
@@ -556,6 +563,9 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
                                ddc_bus.valid = false;
                        }
 
+                       /* needed for aux chan transactions */
+                       ddc_bus.hpd_id = hpd.hpd ? (hpd.hpd - 1) : 0;
+
                        conn_id = le16_to_cpu(path->usConnObjectId);
 
                        if (!radeon_atom_apply_quirks
@@ -820,6 +830,7 @@ union firmware_info {
        ATOM_FIRMWARE_INFO_V1_2 info_12;
        ATOM_FIRMWARE_INFO_V1_3 info_13;
        ATOM_FIRMWARE_INFO_V1_4 info_14;
+       ATOM_FIRMWARE_INFO_V2_1 info_21;
 };
 
 bool radeon_atom_get_clock_info(struct drm_device *dev)
@@ -831,6 +842,7 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
        uint8_t frev, crev;
        struct radeon_pll *p1pll = &rdev->clock.p1pll;
        struct radeon_pll *p2pll = &rdev->clock.p2pll;
+       struct radeon_pll *dcpll = &rdev->clock.dcpll;
        struct radeon_pll *spll = &rdev->clock.spll;
        struct radeon_pll *mpll = &rdev->clock.mpll;
        uint16_t data_offset;
@@ -933,8 +945,19 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
                rdev->clock.default_mclk =
                    le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
 
+               if (ASIC_IS_DCE4(rdev)) {
+                       rdev->clock.default_dispclk =
+                               le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
+                       if (rdev->clock.default_dispclk == 0)
+                               rdev->clock.default_dispclk = 60000; /* 600 Mhz */
+                       rdev->clock.dp_extclk =
+                               le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
+               }
+               *dcpll = *p1pll;
+
                return true;
        }
+
        return false;
 }
 
index 3ec94a0d3109da5ad37fa086fe0ac484a0756133..f64936cc4dd9dfaffeee50d02ea529544b338abc 100644 (file)
@@ -96,6 +96,7 @@ void radeon_get_clock_info(struct drm_device *dev)
        struct radeon_device *rdev = dev->dev_private;
        struct radeon_pll *p1pll = &rdev->clock.p1pll;
        struct radeon_pll *p2pll = &rdev->clock.p2pll;
+       struct radeon_pll *dcpll = &rdev->clock.dcpll;
        struct radeon_pll *spll = &rdev->clock.spll;
        struct radeon_pll *mpll = &rdev->clock.mpll;
        int ret;
@@ -204,6 +205,17 @@ void radeon_get_clock_info(struct drm_device *dev)
                p2pll->max_frac_feedback_div = 0;
        }
 
+       /* dcpll is DCE4 only */
+       dcpll->min_post_div = 2;
+       dcpll->max_post_div = 0x7f;
+       dcpll->min_frac_feedback_div = 0;
+       dcpll->max_frac_feedback_div = 9;
+       dcpll->min_ref_div = 2;
+       dcpll->max_ref_div = 0x3ff;
+       dcpll->min_feedback_div = 4;
+       dcpll->max_feedback_div = 0xfff;
+       dcpll->best_vco = 0;
+
        p1pll->min_ref_div = 2;
        p1pll->max_ref_div = 0x3ff;
        p1pll->min_feedback_div = 4;
index a4d40de50434a0a4c98fcf0a3d08ddf2daf9b66f..26fb42450cb22b5c8a76a6f25b9ccca367828e10 100644 (file)
@@ -600,6 +600,7 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde
        }
        i2c.mm_i2c = false;
        i2c.i2c_id = 0;
+       i2c.hpd_id = 0;
 
        if (ddc_line)
                i2c.valid = true;
index 28772a37009c189a04f94bae7d891087c1e53dfc..9514f32753576d11f10534568024adac79d962a7 100644 (file)
@@ -36,7 +36,14 @@ static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock)
        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
        uint32_t cur_lock;
 
-       if (ASIC_IS_AVIVO(rdev)) {
+       if (ASIC_IS_DCE4(rdev)) {
+               cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
+               if (lock)
+                       cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK;
+               else
+                       cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK;
+               WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
+       } else if (ASIC_IS_AVIVO(rdev)) {
                cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
                if (lock)
                        cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK;
@@ -58,7 +65,10 @@ static void radeon_hide_cursor(struct drm_crtc *crtc)
        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
        struct radeon_device *rdev = crtc->dev->dev_private;
 
-       if (ASIC_IS_AVIVO(rdev)) {
+       if (ASIC_IS_DCE4(rdev)) {
+               WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
+               WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT));
+       } else if (ASIC_IS_AVIVO(rdev)) {
                WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
                WREG32(RADEON_MM_DATA, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
        } else {
@@ -81,10 +91,14 @@ static void radeon_show_cursor(struct drm_crtc *crtc)
        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
        struct radeon_device *rdev = crtc->dev->dev_private;
 
-       if (ASIC_IS_AVIVO(rdev)) {
+       if (ASIC_IS_DCE4(rdev)) {
+               WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
+               WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |
+                      EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT));
+       } else if (ASIC_IS_AVIVO(rdev)) {
                WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
                WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
-                            (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
+                      (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
        } else {
                switch (radeon_crtc->crtc_id) {
                case 0:
@@ -109,7 +123,10 @@ static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
        struct radeon_device *rdev = crtc->dev->dev_private;
 
-       if (ASIC_IS_AVIVO(rdev)) {
+       if (ASIC_IS_DCE4(rdev)) {
+               WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 0);
+               WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr);
+       } else if (ASIC_IS_AVIVO(rdev)) {
                if (rdev->family >= CHIP_RV770) {
                        if (radeon_crtc->crtc_id)
                                WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, 0);
@@ -201,7 +218,15 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
                yorigin = CURSOR_HEIGHT - 1;
 
        radeon_lock_cursor(crtc, true);
-       if (ASIC_IS_AVIVO(rdev)) {
+       if (ASIC_IS_DCE4(rdev)) {
+               /* XXX: check if evergreen has the same issues as avivo chips */
+               WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset,
+                      ((xorigin ? 0 : x) << 16) |
+                      (yorigin ? 0 : y));
+               WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
+               WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
+                      ((radeon_crtc->cursor_width - 1) << 16) | (radeon_crtc->cursor_height - 1));
+       } else if (ASIC_IS_AVIVO(rdev)) {
                int w = radeon_crtc->cursor_width;
                int i = 0;
                struct drm_crtc *crtc_p;
index c90f8d370266392fb38e891006ac404a05e34dde..c224c1d944ef9aa111e87a15e32c1d25ef2b8644 100644 (file)
@@ -182,7 +182,16 @@ bool radeon_card_posted(struct radeon_device *rdev)
        uint32_t reg;
 
        /* first check CRTCs */
-       if (ASIC_IS_AVIVO(rdev)) {
+       if (ASIC_IS_DCE4(rdev)) {
+               reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
+                       RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
+                       RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
+                       RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
+                       RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
+                       RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
+               if (reg & EVERGREEN_CRTC_MASTER_EN)
+                       return true;
+       } else if (ASIC_IS_AVIVO(rdev)) {
                reg = RREG32(AVIVO_D1CRTC_CONTROL) |
                      RREG32(AVIVO_D2CRTC_CONTROL);
                if (reg & AVIVO_CRTC_EN) {
@@ -310,7 +319,7 @@ void radeon_register_accessor_init(struct radeon_device *rdev)
                rdev->mc_rreg = &rs600_mc_rreg;
                rdev->mc_wreg = &rs600_mc_wreg;
        }
-       if (rdev->family >= CHIP_R600) {
+       if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) {
                rdev->pciep_rreg = &r600_pciep_rreg;
                rdev->pciep_wreg = &r600_pciep_wreg;
        }
@@ -387,6 +396,13 @@ int radeon_asic_init(struct radeon_device *rdev)
        case CHIP_RV740:
                rdev->asic = &rv770_asic;
                break;
+       case CHIP_CEDAR:
+       case CHIP_REDWOOD:
+       case CHIP_JUNIPER:
+       case CHIP_CYPRESS:
+       case CHIP_HEMLOCK:
+               rdev->asic = &evergreen_asic;
+               break;
        default:
                /* FIXME: not supported yet */
                return -EINVAL;
index a41ed40c13fbba38cec2e488535ea926bebc1eb0..257827806aee0d522c337ac822a12b702cbec8cd 100644 (file)
@@ -68,6 +68,36 @@ static void avivo_crtc_load_lut(struct drm_crtc *crtc)
        WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
 }
 
+static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
+{
+       struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+       struct drm_device *dev = crtc->dev;
+       struct radeon_device *rdev = dev->dev_private;
+       int i;
+
+       DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
+       WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
+
+       WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
+       WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
+       WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
+
+       WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
+       WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
+       WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
+
+       WREG32(EVERGREEN_DC_LUT_RW_MODE, radeon_crtc->crtc_id);
+       WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK, 0x00000007);
+
+       WREG32(EVERGREEN_DC_LUT_RW_INDEX, 0);
+       for (i = 0; i < 256; i++) {
+               WREG32(EVERGREEN_DC_LUT_30_COLOR,
+                      (radeon_crtc->lut_r[i] << 20) |
+                      (radeon_crtc->lut_g[i] << 10) |
+                      (radeon_crtc->lut_b[i] << 0));
+       }
+}
+
 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 {
        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
@@ -100,7 +130,9 @@ void radeon_crtc_load_lut(struct drm_crtc *crtc)
        if (!crtc->enabled)
                return;
 
-       if (ASIC_IS_AVIVO(rdev))
+       if (ASIC_IS_DCE4(rdev))
+               evergreen_crtc_load_lut(crtc);
+       else if (ASIC_IS_AVIVO(rdev))
                avivo_crtc_load_lut(crtc);
        else
                legacy_crtc_load_lut(crtc);
@@ -862,8 +894,12 @@ int radeon_modeset_init(struct radeon_device *rdev)
 
        if (rdev->flags & RADEON_SINGLE_CRTC)
                rdev->num_crtc = 1;
-       else
-               rdev->num_crtc = 2;
+       else {
+               if (ASIC_IS_DCE4(rdev))
+                       rdev->num_crtc = 6;
+               else
+                       rdev->num_crtc = 2;
+       }
 
        /* allocate crtcs */
        for (i = 0; i < rdev->num_crtc; i++) {
index f7d6078876c57902505945fc2b22fafeaf1ac15d..bc926ea0a530e014c2b075fed8ac35e0a94d04ae 100644 (file)
@@ -53,7 +53,7 @@ static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
        /* DVO requires 2x ppll clocks depending on tmds chip */
        if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
                return index_mask;
-       
+
        count = -1;
        list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
                struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
@@ -671,6 +671,18 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
  * - 2 DIG encoder blocks.
  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
  *
+ * DCE 4.0
+ * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
+ * Supports up to 6 digital outputs
+ * - 6 DIG encoder blocks.
+ * - DIG to PHY mapping is hardcoded
+ * DIG1 drives UNIPHY0 link A, A+B
+ * DIG2 drives UNIPHY0 link B
+ * DIG3 drives UNIPHY1 link A, A+B
+ * DIG4 drives UNIPHY1 link B
+ * DIG5 drives UNIPHY2 link A, A+B
+ * DIG6 drives UNIPHY2 link B
+ *
  * Routing
  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
  * Examples:
@@ -679,7 +691,14 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
  */
-static void
+
+union dig_encoder_control {
+       DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
+       DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
+       DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
+};
+
+void
 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
 {
        struct drm_device *dev = encoder->dev;
@@ -688,7 +707,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
        struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
        struct radeon_connector_atom_dig *dig_connector =
                radeon_get_atom_connector_priv_from_encoder(encoder);
-       DIG_ENCODER_CONTROL_PS_ALLOCATION args;
+       union dig_encoder_control args;
        int index = 0, num = 0;
        uint8_t frev, crev;
 
@@ -697,56 +716,53 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
 
        memset(&args, 0, sizeof(args));
 
-       if (dig->dig_encoder)
-               index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
-       else
-               index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
+       if (ASIC_IS_DCE4(rdev))
+               index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
+       else {
+               if (dig->dig_encoder)
+                       index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
+               else
+                       index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
+       }
        num = dig->dig_encoder + 1;
 
        atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
 
-       args.ucAction = action;
-       args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
+       args.v1.ucAction = action;
+       args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
+       args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 
-       if (ASIC_IS_DCE32(rdev)) {
+       if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
+               if (dig_connector->dp_clock == 270000)
+                       args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
+               args.v1.ucLaneNum = dig_connector->dp_lane_count;
+       } else if (radeon_encoder->pixel_clock > 165000)
+               args.v1.ucLaneNum = 8;
+       else
+               args.v1.ucLaneNum = 4;
+
+       if (ASIC_IS_DCE4(rdev)) {
+               args.v3.acConfig.ucDigSel = dig->dig_encoder;
+               args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
+       } else {
                switch (radeon_encoder->encoder_id) {
                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
-                       args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
+                       args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
                        break;
                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
-                       args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
+               case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
+                       args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
                        break;
                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
-                       args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
-                       break;
-               }
-       } else {
-               switch (radeon_encoder->encoder_id) {
-               case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
-                       args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1;
-                       break;
-               case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
-                       args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2;
+                       args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
                        break;
                }
+               if (dig_connector->linkb)
+                       args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
+               else
+                       args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
        }
 
-       args.ucEncoderMode = atombios_get_encoder_mode(encoder);
-
-       if (args.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
-               if (dig_connector->dp_clock == 270000)
-                       args.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
-               args.ucLaneNum = dig_connector->dp_lane_count;
-       } else if (radeon_encoder->pixel_clock > 165000)
-               args.ucLaneNum = 8;
-       else
-               args.ucLaneNum = 4;
-
-       if (dig_connector->linkb)
-               args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
-       else
-               args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
-
        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 
 }
@@ -754,6 +770,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
 union dig_transmitter_control {
        DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
        DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
+       DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 };
 
 void
@@ -771,6 +788,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
        int index = 0, num = 0;
        uint8_t frev, crev;
        bool is_dp = false;
+       int pll_id = 0;
 
        if (!dig || !dig_connector)
                return;
@@ -783,7 +801,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
 
        memset(&args, 0, sizeof(args));
 
-       if (ASIC_IS_DCE32(rdev))
+       if (ASIC_IS_DCE32(rdev) || ASIC_IS_DCE4(rdev))
                index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
        else {
                switch (radeon_encoder->encoder_id) {
@@ -813,7 +831,54 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
                else
                        args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
        }
-       if (ASIC_IS_DCE32(rdev)) {
+       if (ASIC_IS_DCE4(rdev)) {
+               if (is_dp)
+                       args.v3.ucLaneNum = dig_connector->dp_lane_count;
+               else if (radeon_encoder->pixel_clock > 165000)
+                       args.v3.ucLaneNum = 8;
+               else
+                       args.v3.ucLaneNum = 4;
+
+               if (dig_connector->linkb) {
+                       args.v3.acConfig.ucLinkSel = 1;
+                       args.v3.acConfig.ucEncoderSel = 1;
+               }
+
+               /* Select the PLL for the PHY
+                * DP PHY should be clocked from external src if there is
+                * one.
+                */
+               if (encoder->crtc) {
+                       struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+                       pll_id = radeon_crtc->pll_id;
+               }
+               if (is_dp && rdev->clock.dp_extclk)
+                       args.v3.acConfig.ucRefClkSource = 2; /* external src */
+               else
+                       args.v3.acConfig.ucRefClkSource = pll_id;
+
+               switch (radeon_encoder->encoder_id) {
+               case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+                       args.v3.acConfig.ucTransmitterSel = 0;
+                       num = 0;
+                       break;
+               case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+                       args.v3.acConfig.ucTransmitterSel = 1;
+                       num = 1;
+                       break;
+               case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+                       args.v3.acConfig.ucTransmitterSel = 2;
+                       num = 2;
+                       break;
+               }
+
+               if (is_dp)
+                       args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
+               else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
+                       if (dig->coherent_mode)
+                               args.v3.acConfig.fCoherentMode = 1;
+               }
+       } else if (ASIC_IS_DCE32(rdev)) {
                if (dig->dig_encoder == 1)
                        args.v2.acConfig.ucEncoderSel = 1;
                if (dig_connector->linkb)
@@ -841,7 +906,6 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
                                args.v2.acConfig.fCoherentMode = 1;
                }
        } else {
-
                args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 
                if (dig->dig_encoder)
@@ -1102,10 +1166,26 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
                                dig = radeon_encoder->enc_priv;
-                               if (dig->dig_encoder)
-                                       args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
-                               else
+                               switch (dig->dig_encoder) {
+                               case 0:
                                        args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
+                                       break;
+                               case 1:
+                                       args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
+                                       break;
+                               case 2:
+                                       args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
+                                       break;
+                               case 3:
+                                       args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
+                                       break;
+                               case 4:
+                                       args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
+                                       break;
+                               case 5:
+                                       args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
+                                       break;
+                               }
                                break;
                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
                                args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
@@ -1162,6 +1242,7 @@ atombios_apply_encoder_quirks(struct drm_encoder *encoder,
        }
 
        /* set scaler clears this on some chips */
+       /* XXX check DCE4 */
        if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
                if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
                        WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
@@ -1178,6 +1259,33 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
        struct drm_encoder *test_encoder;
        struct radeon_encoder_atom_dig *dig;
        uint32_t dig_enc_in_use = 0;
+
+       if (ASIC_IS_DCE4(rdev)) {
+               struct radeon_connector_atom_dig *dig_connector =
+                       radeon_get_atom_connector_priv_from_encoder(encoder);
+
+               switch (radeon_encoder->encoder_id) {
+               case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+                       if (dig_connector->linkb)
+                               return 1;
+                       else
+                               return 0;
+                       break;
+               case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+                       if (dig_connector->linkb)
+                               return 3;
+                       else
+                               return 2;
+                       break;
+               case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+                       if (dig_connector->linkb)
+                               return 5;
+                       else
+                               return 4;
+                       break;
+               }
+       }
+
        /* on DCE32 and encoder can driver any block so just crtc id */
        if (ASIC_IS_DCE32(rdev)) {
                return radeon_crtc->crtc_id;
@@ -1249,15 +1357,26 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
-               /* disable the encoder and transmitter */
-               atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
-               atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
-
-               /* setup and enable the encoder and transmitter */
-               atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
-               atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
-               atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
-               atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
+               if (ASIC_IS_DCE4(rdev)) {
+                       /* disable the transmitter */
+                       atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
+                       /* setup and enable the encoder */
+                       atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
+
+                       /* init and enable the transmitter */
+                       atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
+                       atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
+               } else {
+                       /* disable the encoder and transmitter */
+                       atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
+                       atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
+
+                       /* setup and enable the encoder and transmitter */
+                       atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
+                       atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
+                       atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
+                       atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
+               }
                break;
        case ENCODER_OBJECT_ID_INTERNAL_DDI:
                atombios_ddia_setup(encoder, ATOM_ENABLE);
@@ -1277,7 +1396,9 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
        }
        atombios_apply_encoder_quirks(encoder, adjusted_mode);
 
-       r600_hdmi_setmode(encoder, adjusted_mode);
+       /* XXX */
+       if (!ASIC_IS_DCE4(rdev))
+               r600_hdmi_setmode(encoder, adjusted_mode);
 }
 
 static bool
@@ -1475,10 +1596,18 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
                return;
 
        encoder = &radeon_encoder->base;
-       if (rdev->flags & RADEON_SINGLE_CRTC)
+       switch (rdev->num_crtc) {
+       case 1:
                encoder->possible_crtcs = 0x1;
-       else
+               break;
+       case 2:
+       default:
                encoder->possible_crtcs = 0x3;
+               break;
+       case 6:
+               encoder->possible_crtcs = 0x3f;
+               break;
+       }
 
        radeon_encoder->enc_priv = NULL;
 
index 797972e344a64ce70a6e79aca50657146ca80d56..93c7d5d419141456cdbe8b0c455b78709b993439 100644 (file)
@@ -75,6 +75,11 @@ enum radeon_family {
        CHIP_RV730,
        CHIP_RV710,
        CHIP_RV740,
+       CHIP_CEDAR,
+       CHIP_REDWOOD,
+       CHIP_JUNIPER,
+       CHIP_CYPRESS,
+       CHIP_HEMLOCK,
        CHIP_LAST,
 };
 
index d1e859d1dbf9ad4db84cad7ce09b4151e1e3fb65..8912f2e8e640b6fae6691f3e470ee9529c92b17e 100644 (file)
@@ -83,6 +83,8 @@ struct radeon_i2c_bus_rec {
        bool valid;
        /* id used by atom */
        uint8_t i2c_id;
+       /* id used by atom */
+       uint8_t hpd_id;
        /* can be used with hw i2c engine */
        bool hw_capable;
        /* uses multi-media i2c engine */
@@ -207,7 +209,7 @@ struct radeon_mode_info {
        struct card_info *atom_card_info;
        enum radeon_connector_table connector_table;
        bool mode_config_initialized;
-       struct radeon_crtc *crtcs[2];
+       struct radeon_crtc *crtcs[6];
        /* DVI-I properties */
        struct drm_property *coherent_mode_property;
        /* DAC enable load detect */
@@ -252,6 +254,7 @@ struct radeon_crtc {
        fixed20_12 vsc;
        fixed20_12 hsc;
        struct drm_display_mode native_mode;
+       int pll_id;
 };
 
 struct radeon_encoder_primary_dac {
@@ -414,6 +417,7 @@ extern void dp_link_train(struct drm_encoder *encoder,
                          struct drm_connector *connector);
 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
+extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action);
 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
                                           int action, uint8_t lane_num,
                                           uint8_t lane_set);
index b4a06676fff606d3fc4409c4a4ac8a69dfe9cf1c..5c0dc082d3307752a7dbf7067ea1b98f5cafaafa 100644 (file)
@@ -54,7 +54,7 @@
 #include "r300_reg.h"
 #include "r500_reg.h"
 #include "r600_reg.h"
-
+#include "evergreen_reg.h"
 
 #define RADEON_MC_AGP_LOCATION         0x014c
 #define                RADEON_MC_AGP_START_MASK        0x0000FFFF
index a1367ab6f2617353115d76d898409c00a61ad6f9..9506f8cb99e0552a295bef5bd60dfba49bfaaee0 100644 (file)
 
 #define        WAIT_UNTIL                                      0x8040
 
+#define        SRBM_STATUS                                     0x0E50
+
 #endif
index e6f3b120f51a5e4f9d51bf694b8ecba0b8d7503c..403490c7b647419ce1a9645eb7610cd01137c340 100644 (file)
        {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
        {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
        {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x6880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x6888, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x6889, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x688A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x6898, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x6899, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x689c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HEMLOCK|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x689d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HEMLOCK|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x689e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68a0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68a1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68a8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68a9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68b8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68b9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68be, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68c8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68c9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68d9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68e0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68e1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68e5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68e8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68e9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68f1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68f8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68f9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
+       {0x1002, 0x68fe, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
        {0x1002, 0x7100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
        {0x1002, 0x7101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
        {0x1002, 0x7102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \