Change *EXTLOAD to use an VTSDNode operand instead of being an MVTSDNode.

This is the last MVTSDNode.

This allows us to eliminate a bunch of special case code for handling
MVTSDNodes.

Also, remove some uses of dyn_cast that should really be cast (which is
cheaper in a release build).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22368 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index aeb15a02f50d9f5b629632b77cd674bdac9d30cb..8c3a64051b07980a286efeb245e1a6dda510d3fa 100644 (file)
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -429,8 +429,8 @@ LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
                                DAG.getSrcValue(VAListV));
   SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP, 
                               DAG.getConstant(8, MVT::i64));
-  SDOperand Offset = DAG.getNode(ISD::SEXTLOAD, MVT::i64, Base.getValue(1), 
-                                 Tmp, DAG.getSrcValue(VAListV, 8), MVT::i32);
+  SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1), 
+                                    Tmp, DAG.getSrcValue(VAListV, 8), MVT::i32);
   SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
   if (ArgTy->isFloatingPoint())
   {
@@ -444,11 +444,11 @@ LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
 
   SDOperand Result;
   if (ArgTy == Type::IntTy)
-    Result = DAG.getNode(ISD::SEXTLOAD, MVT::i64, Offset.getValue(1), DataPtr, 
-                         DAG.getSrcValue(NULL), MVT::i32);
+    Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Offset.getValue(1),
+                            DataPtr, DAG.getSrcValue(NULL), MVT::i32);
   else if (ArgTy == Type::UIntTy)
-    Result = DAG.getNode(ISD::ZEXTLOAD, MVT::i64, Offset.getValue(1), DataPtr, 
-                         DAG.getSrcValue(NULL), MVT::i32);
+    Result = DAG.getExtLoad(ISD::ZEXTLOAD, MVT::i64, Offset.getValue(1),
+                            DataPtr, DAG.getSrcValue(NULL), MVT::i32);
   else
     Result = DAG.getLoad(getValueType(ArgTy), Offset.getValue(1), DataPtr, 
                          DAG.getSrcValue(NULL));
@@ -474,8 +474,8 @@ LowerVACopy(SDOperand Chain, SDOperand SrcP, Value *SrcV, SDOperand DestP,
                                  Val, DestP, DAG.getSrcValue(DestV));
   SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP, 
                              DAG.getConstant(8, MVT::i64));
-  Val = DAG.getNode(ISD::SEXTLOAD, MVT::i64, Result, NP,
-                    DAG.getSrcValue(SrcV, 8), MVT::i32);
+  Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP,
+                       DAG.getSrcValue(SrcV, 8), MVT::i32);
   SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP, 
                              DAG.getConstant(8, MVT::i64));
   return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
@@ -1252,7 +1252,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
         case MVT::f32: Opc = Alpha::LDS; break;
         }
       else
-        switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
+        switch (cast<VTSDNode>(Node->getOperand(3))->getVT()) {
         default: Node->dump(); assert(0 && "Bad sign extend!");
         case MVT::i32: Opc = Alpha::LDL;
           assert(opcode != ISD::ZEXTLOAD && "Not sext"); break;
@@ -1279,7 +1279,8 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
             .addImm(getUID());
         BuildMI(BB, GetRelVersion(Opc), 2, Result)
           .addGlobalAddress(GASD->getGlobal()).addReg(Tmp1);
-      } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
+      } else if (ConstantPoolSDNode *CP =
+                     dyn_cast<ConstantPoolSDNode>(Address)) {
         AlphaLowering.restoreGP(BB);
         has_sym = true;
         Tmp1 = MakeReg(MVT::i64);
@@ -1473,8 +1474,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
       }
 
       //Alpha has instructions for a bunch of signed 32 bit stuff
-      if( dyn_cast<MVTSDNode>(Node)->getExtraValueType() == MVT::i32)
-      {
+      if(cast<VTSDNode>(Node->getOperand(1))->getVT() == MVT::i32) {
         switch (N.getOperand(0).getOpcode()) {
         case ISD::ADD:
         case ISD::SUB:
@@ -1485,7 +1485,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
             //FIXME: first check for Scaled Adds and Subs!
             ConstantSDNode* CSD = NULL;
             if(!isMul && N.getOperand(0).getOperand(0).getOpcode() == ISD::SHL &&
-               (CSD = dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(0).getOperand(1))) &&
+               (CSD = cast<ConstantSDNode>(N.getOperand(0).getOperand(0).getOperand(1))) &&
                (CSD->getValue() == 2 || CSD->getValue() == 3))
             {
               bool use4 = CSD->getValue() == 2;
@@ -1495,7 +1495,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
                       2,Result).addReg(Tmp1).addReg(Tmp2);
             }
             else if(isAdd && N.getOperand(0).getOperand(1).getOpcode() == ISD::SHL &&
-                    (CSD = dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1).getOperand(1))) &&
+                    (CSD = cast<ConstantSDNode>(N.getOperand(0).getOperand(1).getOperand(1))) &&
                     (CSD->getValue() == 2 || CSD->getValue() == 3))
             {
               bool use4 = CSD->getValue() == 2;
@@ -1524,10 +1524,8 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
         }
       } //Every thing else fall though too, including unhandled opcodes above
       Tmp1 = SelectExpr(N.getOperand(0));
-      MVTSDNode* MVN = dyn_cast<MVTSDNode>(Node);
       //std::cerr << "SrcT: " << MVN->getExtraValueType() << "\n";
-      switch(MVN->getExtraValueType())
-      {
+      switch(cast<VTSDNode>(Node->getOperand(1))->getVT()) {
       default:
         Node->dump();
         assert(0 && "Sign Extend InReg not there yet");
@@ -1636,7 +1634,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
       SDOperand Chain   = N.getOperand(0);
 
       Select(Chain);
-      unsigned r = dyn_cast<RegSDNode>(Node)->getReg();
+      unsigned r = cast<RegSDNode>(Node)->getReg();
       //std::cerr << "CopyFromReg " << Result << " = " << r << "\n";
       if (MVT::isFloatingPoint(N.getValue(0).getValueType()))
         BuildMI(BB, Alpha::CPYS, 2, Result).addReg(r).addReg(r);
@@ -1943,8 +1941,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
       SDOperand CC = N.getOperand(0);
       SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val);
 
-      if (CC.getOpcode() == ISD::SETCC &&
-          !MVT::isInteger(SetCC->getOperand(0).getValueType()))
+      if (SetCC && !MVT::isInteger(SetCC->getOperand(0).getValueType()))
       { //FP Setcc -> Select yay!
 
         
@@ -2296,7 +2293,7 @@ void AlphaISel::Select(SDOperand N) {
 
       int i, j, k;
       if (EnableAlphaLSMark) 
-        getValueInfo(dyn_cast<SrcValueSDNode>(N.getOperand(3))->getValue(), 
+        getValueInfo(cast<SrcValueSDNode>(N.getOperand(3))->getValue(), 
                      i, j, k);
 
       GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(Address);

diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp
index 3b3f90a489c2c5ea76608ef48b17a057d3642d3c..7d19da4c0f1165188b55be1cfa57147fbc716074 100644 (file)
--- a/lib/Target/IA64/IA64ISelPattern.cpp
+++ b/lib/Target/IA64/IA64ISelPattern.cpp
@@ -1815,9 +1815,7 @@ pC = pA OR pB
 
   case ISD::SIGN_EXTEND_INREG: {
     Tmp1 = SelectExpr(N.getOperand(0));
-    MVTSDNode* MVN = dyn_cast<MVTSDNode>(Node);
-    switch(MVN->getExtraValueType())
-    {
+    switch(cast<VTSDNode>(Node->getOperand(1))->getVT()) {
     default:
       Node->dump();
       assert(0 && "don't know how to sign extend this type");
@@ -1963,7 +1961,8 @@ pC = pA OR pB
         case MVT::f64: Opc = IA64::LDF8; break;
       }
     } else { // this is an EXTLOAD or ZEXTLOAD
-      MVT::ValueType TypeBeingLoaded = cast<MVTSDNode>(Node)->getExtraValueType();
+      MVT::ValueType TypeBeingLoaded =
+        cast<VTSDNode>(Node->getOperand(3))->getVT();
       switch (TypeBeingLoaded) {
         default: assert(0 && "Cannot extload/zextload this type!");
         // FIXME: bools?

diff --git a/lib/Target/PowerPC/PPC64ISelPattern.cpp b/lib/Target/PowerPC/PPC64ISelPattern.cpp
index 1fca3391707e09f709f75c6d3d17abe69afe6b3f..98e69e9cc4617600a8cd84c97ad1e0e381b11102 100644 (file)
--- a/lib/Target/PowerPC/PPC64ISelPattern.cpp
+++ b/lib/Target/PowerPC/PPC64ISelPattern.cpp
@@ -1030,7 +1030,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
   case ISD::ZEXTLOAD:
   case ISD::SEXTLOAD: {
     MVT::ValueType TypeBeingLoaded = (ISD::LOAD == opcode) ?
-      Node->getValueType(0) : cast<MVTSDNode>(Node)->getExtraValueType();
+      Node->getValueType(0) : cast<VTSDNode>(Node->getOperand(3))->getVT();
     bool sext = (ISD::SEXTLOAD == opcode);
 
     // Make sure we generate both values.
@@ -1166,7 +1166,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
   case ISD::SIGN_EXTEND:
   case ISD::SIGN_EXTEND_INREG:
     Tmp1 = SelectExpr(N.getOperand(0));
-    switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
+    switch(cast<VTSDNode>(Node->getOperand(1))->getVT()) {
     default: Node->dump(); assert(0 && "Unhandled SIGN_EXTEND type"); break;
     case MVT::i32:
       BuildMI(BB, PPC::EXTSW, 1, Result).addReg(Tmp1);

diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index f5a09a7f60f82e29661812358c3822cad0660d4d..5388eebb6bcb2085f912c72df957421b522cada6 100644 (file)
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -1690,7 +1690,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
   case ISD::ZEXTLOAD:
   case ISD::SEXTLOAD: {
     MVT::ValueType TypeBeingLoaded = (ISD::LOAD == opcode) ?
-      Node->getValueType(0) : cast<MVTSDNode>(Node)->getExtraValueType();
+      Node->getValueType(0) : cast<VTSDNode>(Node->getOperand(3))->getVT();
     bool sext = (ISD::SEXTLOAD == opcode);
 
     // Make sure we generate both values.
@@ -1828,7 +1828,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
   case ISD::SIGN_EXTEND:
   case ISD::SIGN_EXTEND_INREG:
     Tmp1 = SelectExpr(N.getOperand(0));
-    switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
+    switch(cast<VTSDNode>(Node->getOperand(1))->getVT()) {
     default: Node->dump(); assert(0 && "Unhandled SIGN_EXTEND type"); break;
     case MVT::i16:
       BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1);

diff --git a/lib/Target/Sparc/SparcV8ISelPattern.cpp b/lib/Target/Sparc/SparcV8ISelPattern.cpp
index c2740e339bec2d0f0720ad62e5c42ff1f3fc8b12..e557afcf8b51317bcff89aebc916ce855eaa34f8 100644 (file)
--- a/lib/Target/Sparc/SparcV8ISelPattern.cpp
+++ b/lib/Target/Sparc/SparcV8ISelPattern.cpp
@@ -340,7 +340,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
       SDOperand Address = N.getOperand(1);
       Select(Chain);
       unsigned Adr = SelectExpr(Address);
-      switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
+      switch(cast<VTSDNode>(Node->getOperand(3))->getVT()) {
       case MVT::i32: Opc = V8::LD;
       case MVT::i16: Opc = opcode == ISD::ZEXTLOAD ? V8::LDUH : V8::LDSH; break;
       case MVT::i8:  Opc = opcode == ISD::ZEXTLOAD ? V8::LDUB : V8::LDSB; break;

diff --git a/lib/Target/SparcV8/SparcV8ISelPattern.cpp b/lib/Target/SparcV8/SparcV8ISelPattern.cpp
index c2740e339bec2d0f0720ad62e5c42ff1f3fc8b12..e557afcf8b51317bcff89aebc916ce855eaa34f8 100644 (file)
--- a/lib/Target/SparcV8/SparcV8ISelPattern.cpp
+++ b/lib/Target/SparcV8/SparcV8ISelPattern.cpp
@@ -340,7 +340,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
       SDOperand Address = N.getOperand(1);
       Select(Chain);
       unsigned Adr = SelectExpr(Address);
-      switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
+      switch(cast<VTSDNode>(Node->getOperand(3))->getVT()) {
       case MVT::i32: Opc = V8::LD;
       case MVT::i16: Opc = opcode == ISD::ZEXTLOAD ? V8::LDUH : V8::LDSH; break;
       case MVT::i8:  Opc = opcode == ISD::ZEXTLOAD ? V8::LDUB : V8::LDSB; break;

diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp
index af75bdc7796ca07ae0179cc55025e55f192f0fd1..66e6f71bff3e177d7afdcc81d08434974d072a88 100644 (file)
--- a/lib/Target/X86/X86ISelPattern.cpp
+++ b/lib/Target/X86/X86ISelPattern.cpp
@@ -1934,7 +1934,7 @@ bool ISel::isFoldableLoad(SDOperand Op, SDOperand OtherOp, bool FloatPromoteOk){
     if (isa<ConstantPoolSDNode>(Op.getOperand(1)))
       return false;
   } else if (FloatPromoteOk && Op.getOpcode() == ISD::EXTLOAD &&
-             cast<MVTSDNode>(Op)->getExtraValueType() == MVT::f32) {
+             cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::f32) {
     // FIXME: currently can't fold constant pool indexes.
     if (isa<ConstantPoolSDNode>(Op.getOperand(1)))
       return false;
@@ -3377,7 +3377,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
 
     if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N.getOperand(1)))
       if (Node->getValueType(0) == MVT::f64) {
-        assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::f32 &&
+        assert(cast<VTSDNode>(Node->getOperand(3))->getVT() == MVT::f32 &&
                "Bad EXTLOAD!");
         addConstantPoolReference(BuildMI(BB, X86::FLD32m, 4, Result),
                                  CP->getIndex());
@@ -3397,12 +3397,12 @@ unsigned ISel::SelectExpr(SDOperand N) {
     switch (Node->getValueType(0)) {
     default: assert(0 && "Unknown type to sign extend to.");
     case MVT::f64:
-      assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::f32 &&
+      assert(cast<VTSDNode>(Node->getOperand(3))->getVT() == MVT::f32 &&
              "Bad EXTLOAD!");
       addFullAddress(BuildMI(BB, X86::FLD32m, 5, Result), AM);
       break;
     case MVT::i32:
-      switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
+      switch (cast<VTSDNode>(Node->getOperand(3))->getVT()) {
       default:
         assert(0 && "Bad zero extend!");
       case MVT::i1:
@@ -3415,12 +3415,12 @@ unsigned ISel::SelectExpr(SDOperand N) {
       }
       break;
     case MVT::i16:
-      assert(cast<MVTSDNode>(Node)->getExtraValueType() <= MVT::i8 &&
+      assert(cast<VTSDNode>(Node->getOperand(3))->getVT() <= MVT::i8 &&
              "Bad zero extend!");
       addFullAddress(BuildMI(BB, X86::MOVSX16rm8, 5, Result), AM);
       break;
     case MVT::i8:
-      assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::i1 &&
+      assert(cast<VTSDNode>(Node->getOperand(3))->getVT() == MVT::i1 &&
              "Bad zero extend!");
       addFullAddress(BuildMI(BB, X86::MOV8rm, 5, Result), AM);
       break;
@@ -3448,7 +3448,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
     case MVT::i8: assert(0 && "Cannot sign extend from bool!");
     default: assert(0 && "Unknown type to sign extend to.");
     case MVT::i32:
-      switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
+      switch (cast<VTSDNode>(Node->getOperand(3))->getVT()) {
       default:
       case MVT::i1: assert(0 && "Cannot sign extend from bool!");
       case MVT::i8:
@@ -3460,7 +3460,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
       }
       break;
     case MVT::i16:
-      assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::i8 &&
+      assert(cast<VTSDNode>(Node->getOperand(3))->getVT() == MVT::i8 &&
              "Cannot sign extend from bool!");
       addFullAddress(BuildMI(BB, X86::MOVSX16rm8, 5, Result), AM);
       break;