Small correction to unordered memory code generation of ARM LDRD

The information was correct pre-LPAE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184253 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/docs/Atomics.rst b/docs/Atomics.rst
index 705d73fbaba43c62b9dbd80bedd20e3cd77bea30..1243f345483f44d4edf08e5c4ef1d6aaceb383aa 100644 (file)
--- a/docs/Atomics.rst
+++ b/docs/Atomics.rst
@@ -211,7 +211,7 @@ Notes for code generation
   never stored.  A normal load or store instruction is usually sufficient, but
   note that an unordered load or store cannot be split into multiple
   instructions (or an instruction which does multiple memory operations, like
-  ``LDRD`` on ARM).
+  ``LDRD`` on ARM without LPAE, or not naturally-aligned ``LDRD`` on LPAE ARM).
 
 Monotonic
 ---------