MIPS: For Cavium OCTEON handle hazards as per the R10000 handling.
authorDavid Daney <ddaney@caviumnetworks.com>
Thu, 11 Dec 2008 23:33:22 +0000 (15:33 -0800)
committerRalf Baechle <ralf@linux-mips.org>
Sun, 11 Jan 2009 09:57:21 +0000 (09:57 +0000)
For Cavium CPU, we treat the same as R10000, in that all hazards
are dealt with in hardware.

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/hazards.h

index 2de638f84c86ab900f8f29e3303100abed7267ac..43baed16a1093aea91ec92b872976ba0cd605317 100644 (file)
@@ -42,7 +42,7 @@ ASMMACRO(_ehb,
 /*
  * TLB hazards
  */
-#if defined(CONFIG_CPU_MIPSR2)
+#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_CAVIUM_OCTEON)
 
 /*
  * MIPSR2 defines ehb for hazard avoidance
@@ -138,7 +138,7 @@ do {                                                                        \
                __instruction_hazard();                                 \
 } while (0)
 
-#elif defined(CONFIG_CPU_R10000)
+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON)
 
 /*
  * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.