; CHECK: divb
; CHECK: addl
; CHECK: ret
-; CEECK-NOT: idivl
+; CHECK-NOT: idivl
; CHECK-NOT: divb
%resultdiv = sdiv i32 %a, %b
%resultrem = srem i32 %a, %b
define i32 @Test_use_div_reg_imm(i32 %a) nounwind {
; CHECK: Test_use_div_reg_imm:
-; CEHCK-NOT: test
+; CHECK-NOT: test
; CHECK-NOT: idiv
; CHECK-NOT: divb
%resultdiv = sdiv i32 %a, 33
define i32 @Test_use_rem_reg_imm(i32 %a) nounwind {
; CHECK: Test_use_rem_reg_imm:
-; CEHCK-NOT: test
+; CHECK-NOT: test
; CHECK-NOT: idiv
; CHECK-NOT: divb
%resultrem = srem i32 %a, 33
define i32 @Test_use_divrem_reg_imm(i32 %a) nounwind {
; CHECK: Test_use_divrem_reg_imm:
-; CEHCK-NOT: test
+; CHECK-NOT: test
; CHECK-NOT: idiv
; CHECK-NOT: divb
%resultdiv = sdiv i32 %a, 33