rk: support dcache disable

diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index 7e79503ab89b5d395e634fda206e1e97d6262d04..16d92e837c536b638094d737b6278298061398c8 100644 (file)
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -27,7 +27,7 @@
 #define atomic_read(v) (*(volatile int *)&(v)->counter)
 #define atomic_set(v,i)        (((v)->counter) = (i))
 
-#if __LINUX_ARM_ARCH__ >= 6
+#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_DCACHE_DISABLE)
 
 /*
  * ARMv6 UP and SMP safe atomic ops.  We use load exclusive and

diff --git a/arch/arm/include/asm/locks.h b/arch/arm/include/asm/locks.h
index ef4c897772d1459f589ac2a1967a742e822cad2a..82df16603b8fc1eda37939e0595b13e2ee188da3 100644 (file)
--- a/arch/arm/include/asm/locks.h
+++ b/arch/arm/include/asm/locks.h
@@ -12,7 +12,7 @@
 #ifndef __ASM_PROC_LOCKS_H
 #define __ASM_PROC_LOCKS_H
 
-#if __LINUX_ARM_ARCH__ >= 6
+#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_DCACHE_DISABLE)
 
 #define __down_op(ptr,fail)                    \
        ({                                      \

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 832888d0c20c263a761cc093bb96ae4977ed15bc..bb3bc5beb66d317a683bd1887a1678b93ced9290 100644 (file)
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -269,14 +269,14 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
 #ifdef swp_is_buggy
        unsigned long flags;
 #endif
-#if __LINUX_ARM_ARCH__ >= 6
+#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_DCACHE_DISABLE)
        unsigned int tmp;
 #endif
 
        smp_mb();
 
        switch (size) {
-#if __LINUX_ARM_ARCH__ >= 6
+#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_DCACHE_DISABLE)
        case 1:
                asm volatile("@ __xchg1\n"
                "1:     ldrexb  %0, [%3]\n"
@@ -346,7 +346,7 @@ void cpu_idle_wait(void);
 
 #include <asm-generic/cmpxchg-local.h>
 
-#if __LINUX_ARM_ARCH__ < 6
+#if __LINUX_ARM_ARCH__ < 6 || defined(CONFIG_CPU_DCACHE_DISABLE)
 /* min ARCH < ARMv6 */
 
 #ifdef CONFIG_SMP

diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 2cd00764016d78cb48f56954479f663fe1004936..53f63061825bbba4799b4e5b5e406452ae6d0a34 100644 (file)
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -905,7 +905,7 @@ __kuser_cmpxchg:                            @ 0xffff0fc0
        ldmfd   sp!, {r7, pc}
 1:     .word   __ARM_NR_cmpxchg
 
-#elif __LINUX_ARM_ARCH__ < 6
+#elif __LINUX_ARM_ARCH__ < 6 || defined(CONFIG_CPU_DCACHE_DISABLE)
 
 #ifdef CONFIG_MMU
 

diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h
index 10d868a5a48135840278022e153f3610b0b7a640..679c981ee5f06d340c08441f75c4f97b2adad920 100644 (file)
--- a/arch/arm/lib/bitops.h
+++ b/arch/arm/lib/bitops.h
@@ -1,4 +1,4 @@
-#if __LINUX_ARM_ARCH__ >= 6
+#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_DCACHE_DISABLE)
        .macro  bitop, instr
        ands    ip, r1, #3
        strneb  r1, [ip]                @ assert word-aligned

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index acb1c36adaddd37dbf54b4fbdb40ac35f867b16e..a4818f129bd2fb6dc1ee508248a1aec068ece080 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -721,6 +721,8 @@ config CPU_ICACHE_DISABLE
 config CPU_DCACHE_DISABLE
        bool "Disable D-Cache (C-bit)"
        depends on CPU_CP15
+       depends on !SMP && !SWP_EMULATE
+       select GENERIC_ATOMIC64
        help
          Say Y here to disable the processor data cache. Unless
          you have a reason not to or are unsure, say N.