{
iounmap(otg_dev->base);
}
- clk_put(otg_dev->clk);
- clk_disable(otg_dev->clk);
+ clk_put(otg_dev->phyclk);
+ clk_disable(otg_dev->phyclk);
+ clk_put(otg_dev->ahbclk);
+ clk_disable(otg_dev->ahbclk);
+ clk_put(otg_dev->busclk);
+ clk_disable(otg_dev->busclk);
kfree(otg_dev);
/*
int32_t snpsid;
int irq;
int32_t regval;
+ struct clk *ahbclk,*phyclk,*busclk;
+ unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
/*
*Enable usb phy
*/
- unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
- struct clk* clk;
-
- clk = clk_get(NULL, "otgphy0");
- if (IS_ERR(clk)) {
- retval = PTR_ERR(clk);
- DWC_ERROR("can't get USB clock of otgphy0\n");
- goto fail;
- }
- clk_enable(clk);
-
regval = * otg_phy_con1;
regval |= (0x01<<2);
regval |= (0x01<<3); // exit suspend.
memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
dwc_otg_device->reg_offset = 0xFFFFFFFF;
- dwc_otg_device->clk = clk;
+
+ busclk = clk_get(NULL, "usb");
+ if (IS_ERR(busclk)) {
+ retval = PTR_ERR(busclk);
+ DWC_ERROR("can't get USB PERIPH AHB bus clock\n");
+ goto fail;
+ }
+ clk_enable(busclk);
+
+ phyclk = clk_get(NULL, "otgphy0");
+ if (IS_ERR(phyclk)) {
+ retval = PTR_ERR(phyclk);
+ DWC_ERROR("can't get USBPHY0 clock\n");
+ goto fail;
+ }
+ clk_enable(phyclk);
+
+ ahbclk = clk_get(NULL, "usbotg0");
+ if (IS_ERR(ahbclk)) {
+ retval = PTR_ERR(ahbclk);
+ DWC_ERROR("can't get USB otg0 ahb bus clock\n");
+ goto fail;
+ }
+ clk_enable(ahbclk);
+
+ dwc_otg_device->phyclk = phyclk;
+ dwc_otg_device->ahbclk = ahbclk;
+ dwc_otg_device->busclk = busclk;
/*
* Map the DWC_otg Core memory into virtual address space.
*/
{
iounmap(otg_dev->base);
}
- clk_put(otg_dev->clk);
- clk_disable(otg_dev->clk);
+ clk_put(otg_dev->phyclk);
+ clk_disable(otg_dev->phyclk);
+ clk_put(otg_dev->ahbclk);
+ clk_disable(otg_dev->ahbclk);
kfree(otg_dev);
/*
dwc_otg_device_t *dwc_otg_device;
int32_t snpsid;
int irq;
+ struct clk* ahbclk,*phyclk;
/*
*Enable usb phy
*/
unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
- struct clk* clk;
-
- clk = clk_get(NULL, "uhost");
- if (IS_ERR(clk)) {
- retval = PTR_ERR(clk);
- DWC_ERROR("can't get USB clock of uhost\n");
- goto fail;
- }
- clk_enable(clk);
- if (clk_get_rate(clk) != 48000000) {
- DWC_PRINT("Bad USB clock (%d Hz), changing to 48000000 Hz\n",
- (int)clk_get_rate(clk));
- if (clk_set_rate(clk, 48000000)) {
- DWC_ERROR("Unable to set correct USB clock (48MHz)\n");
- retval = -EIO;
- goto fail1;
- }
- }
-
+
*otg_phy_con1 &= ~(0x01<<28); // exit suspend.
#if 0
*otg_phy_con1 |= (0x01<<2);
memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
dwc_otg_device->reg_offset = 0xFFFFFFFF;
- dwc_otg_device->clk = clk;
+
+ phyclk = clk_get(NULL, "uhost");
+ if (IS_ERR(phyclk)) {
+ retval = PTR_ERR(phyclk);
+ DWC_ERROR("can't get UHOST clock\n");
+ goto fail;
+ }
+ clk_enable(phyclk);
+
+ ahbclk = clk_get(NULL, "uhost_ahb");
+ if (IS_ERR(ahbclk)) {
+ retval = PTR_ERR(ahbclk);
+ DWC_ERROR("can't get UHOST ahb bus clock\n");
+ goto fail1;
+ }
+ clk_enable(ahbclk);
+
+ if (clk_get_rate(phyclk) != 48000000) {
+ DWC_PRINT("Bad USB clock (%d Hz), changing to 48000000 Hz\n",
+ (int)clk_get_rate(phyclk));
+ if (clk_set_rate(phyclk, 48000000)) {
+ DWC_ERROR("Unable to set correct USB clock (48MHz)\n");
+ retval = -EIO;
+ goto fail2;
+ }
+ }
+ dwc_otg_device->ahbclk = ahbclk;
+ dwc_otg_device->phyclk = phyclk;
+
/*
* Map the DWC_otg Core memory into virtual address space.
*/
DWC_PRINT("host11_driver_probe end, everest\n");
return 0;
+fail2:
+ clk_put(ahbclk);
+ clk_disable(ahbclk);
fail1:
- clk_put(clk);
- clk_disable(clk);
+ clk_put(phyclk);
+ clk_disable(phyclk);
fail:
devm_kfree(&pdev->dev, dwc_otg_device);
{
iounmap(otg_dev->base);
}
- clk_put(otg_dev->clk);
- clk_disable(otg_dev->clk);
+ clk_put(otg_dev->phyclk);
+ clk_disable(otg_dev->phyclk);
+ clk_put(otg_dev->ahbclk);
+ clk_disable(otg_dev->ahbclk);
kfree(otg_dev);
/*
int32_t snpsid;
int irq;
uint32_t otgreg;
+ struct clk* ahbclk,*phyclk;
/*
*Enable usb phy
*/
unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
- struct clk* clk;
-
- clk = clk_get(NULL, "otgphy1");
- if (IS_ERR(clk)) {
- retval = PTR_ERR(clk);
- DWC_ERROR("can't get USB clock of otgphy1\n");
- goto fail;
- }
- clk_enable(clk);
-
+
otgreg = * otg_phy_con1;
otgreg |= (0x01<<13); // software control
otgreg |= (0x01<<14); // exit suspend.
memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
dwc_otg_device->reg_offset = 0xFFFFFFFF;
- dwc_otg_device->clk = clk;
+
+ phyclk = clk_get(NULL, "otgphy1");
+ if (IS_ERR(phyclk)) {
+ retval = PTR_ERR(phyclk);
+ DWC_ERROR("can't get USBPHY1 clock\n");
+ goto fail;
+ }
+ clk_enable(phyclk);
+
+ ahbclk = clk_get(NULL, "usbotg1");
+ if (IS_ERR(ahbclk)) {
+ retval = PTR_ERR(ahbclk);
+ DWC_ERROR("can't get USBOTG1 ahb bus clock\n");
+ goto fail;
+ }
+ clk_enable(ahbclk);
+ dwc_otg_device->phyclk = phyclk;
+ dwc_otg_device->ahbclk = ahbclk;
+
/*
* Map the DWC_otg Core memory into virtual address space.
*/