80 col.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41812 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 4f075a3f56ee19e56ba43e843e325a3c4ebf3876..fe26e2527737ac9f632439a25745ffb21f2d51a3 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -418,8 +418,9 @@ class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
 }
 
 // Almost all ARM instructions are predicable.
-class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im,
-        Format f, string opc, string asm, string cstr, list<dag> pattern>
+class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
+        IndexMode im, Format f, string opc, string asm, string cstr,
+        list<dag> pattern>
   : InstARM<opcod, am, sz, im, f, cstr> {
   let OutOperandList = oops;
   let InOperandList = !con(iops, (ops pred:$p));
@@ -431,8 +432,9 @@ class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMod
 // Same as I except it can optionally modify CPSR. Note it's modeled as
 // an input operand since by default it's a zero register. It will
 // become an implicit def once it's "flipped".
-class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im,
-         Format f, string opc, string asm, string cstr, list<dag> pattern>
+class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
+         IndexMode im, Format f, string opc, string asm, string cstr,
+         list<dag> pattern>
   : InstARM<opcod, am, sz, im, f, cstr> {
   let OutOperandList = oops;
   let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));