drm/radeon/kms: add radeon_asic struct for trinity

Trinity (TN) is an APU with:
- Cayman 3D
- DCE6.1 display

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index f24e145927908a267470e38b9bbc499cd7b1595c..be4dc2ff0e40f4bfadef1e3085bc5a8ab1b3532f 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -1408,6 +1408,98 @@ static struct radeon_asic cayman_asic = {
        },
 };
 
+static struct radeon_asic trinity_asic = {
+       .init = &cayman_init,
+       .fini = &cayman_fini,
+       .suspend = &cayman_suspend,
+       .resume = &cayman_resume,
+       .gpu_is_lockup = &cayman_gpu_is_lockup,
+       .asic_reset = &cayman_asic_reset,
+       .vga_set_state = &r600_vga_set_state,
+       .ioctl_wait_idle = r600_ioctl_wait_idle,
+       .gui_idle = &r600_gui_idle,
+       .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
+       .gart = {
+               .tlb_flush = &cayman_pcie_gart_tlb_flush,
+               .set_page = &rs600_gart_set_page,
+       },
+       .ring = {
+               [RADEON_RING_TYPE_GFX_INDEX] = {
+                       .ib_execute = &cayman_ring_ib_execute,
+                       .ib_parse = &evergreen_ib_parse,
+                       .emit_fence = &cayman_fence_ring_emit,
+                       .emit_semaphore = &r600_semaphore_ring_emit,
+                       .cs_parse = &evergreen_cs_parse,
+                       .ring_test = &r600_ring_test,
+                       .ib_test = &r600_ib_test,
+               },
+               [CAYMAN_RING_TYPE_CP1_INDEX] = {
+                       .ib_execute = &cayman_ring_ib_execute,
+                       .ib_parse = &evergreen_ib_parse,
+                       .emit_fence = &cayman_fence_ring_emit,
+                       .emit_semaphore = &r600_semaphore_ring_emit,
+                       .cs_parse = &evergreen_cs_parse,
+                       .ring_test = &r600_ring_test,
+                       .ib_test = &r600_ib_test,
+               },
+               [CAYMAN_RING_TYPE_CP2_INDEX] = {
+                       .ib_execute = &cayman_ring_ib_execute,
+                       .ib_parse = &evergreen_ib_parse,
+                       .emit_fence = &cayman_fence_ring_emit,
+                       .emit_semaphore = &r600_semaphore_ring_emit,
+                       .cs_parse = &evergreen_cs_parse,
+                       .ring_test = &r600_ring_test,
+                       .ib_test = &r600_ib_test,
+               }
+       },
+       .irq = {
+               .set = &evergreen_irq_set,
+               .process = &evergreen_irq_process,
+       },
+       .display = {
+               .bandwidth_update = &dce6_bandwidth_update,
+               .get_vblank_counter = &evergreen_get_vblank_counter,
+               .wait_for_vblank = &dce4_wait_for_vblank,
+       },
+       .copy = {
+               .blit = &r600_copy_blit,
+               .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+               .dma = NULL,
+               .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+               .copy = &r600_copy_blit,
+               .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+       },
+       .surface = {
+               .set_reg = r600_set_surface_reg,
+               .clear_reg = r600_clear_surface_reg,
+       },
+       .hpd = {
+               .init = &evergreen_hpd_init,
+               .fini = &evergreen_hpd_fini,
+               .sense = &evergreen_hpd_sense,
+               .set_polarity = &evergreen_hpd_set_polarity,
+       },
+       .pm = {
+               .misc = &evergreen_pm_misc,
+               .prepare = &evergreen_pm_prepare,
+               .finish = &evergreen_pm_finish,
+               .init_profile = &sumo_pm_init_profile,
+               .get_dynpm_state = &r600_pm_get_dynpm_state,
+               .get_engine_clock = &radeon_atom_get_engine_clock,
+               .set_engine_clock = &radeon_atom_set_engine_clock,
+               .get_memory_clock = NULL,
+               .set_memory_clock = NULL,
+               .get_pcie_lanes = NULL,
+               .set_pcie_lanes = NULL,
+               .set_clock_gating = NULL,
+       },
+       .pflip = {
+               .pre_page_flip = &evergreen_pre_page_flip,
+               .page_flip = &evergreen_page_flip,
+               .post_page_flip = &evergreen_post_page_flip,
+       },
+};
+
 static const struct radeon_vm_funcs si_vm_funcs = {
        .init = &si_vm_init,
        .fini = &si_vm_fini,
@@ -1627,6 +1719,12 @@ int radeon_asic_init(struct radeon_device *rdev)
                rdev->num_crtc = 6;
                rdev->vm_manager.funcs = &cayman_vm_funcs;
                break;
+       case CHIP_ARUBA:
+               rdev->asic = &trinity_asic;
+               /* set num crtcs */
+               rdev->num_crtc = 4;
+               rdev->vm_manager.funcs = &cayman_vm_funcs;
+               break;
        case CHIP_TAHITI:
        case CHIP_PITCAIRN:
        case CHIP_VERDE: