--- /dev/null
+/*\r
+defines of FPGA chip ICE65L08's register \r
+*/\r
+\r
+#ifndef SPI_UART_H\r
+#define SPI_UART_H\r
+\r
+#define SPI_FPGA_INT_PIN RK2818_PIN_PA4\r
+#define SPI_DPRAM_BUSY_PIN RK2818_PIN_PA2\r
+#define SPI_FPGA_STANDBY_PIN RK2818_PIN_PH7\r
+\r
+#define SPI_FPGA_TEST_DEBUG 0\r
+#if SPI_FPGA_TEST_DEBUG\r
+#define SPI_FPGA_TEST_DEBUG_PIN RK2818_PIN_PE0\r
+extern int spi_test_wrong_handle(void);\r
+#endif\r
+\r
+struct uart_icount {\r
+ __u32 cts;\r
+ __u32 dsr;\r
+ __u32 rng;\r
+ __u32 dcd;\r
+ __u32 rx;\r
+ __u32 tx;\r
+ __u32 frame;\r
+ __u32 overrun;\r
+ __u32 parity;\r
+ __u32 brk;\r
+};\r
+\r
+struct spi_uart\r
+{\r
+ struct workqueue_struct *spi_uart_workqueue;\r
+ struct work_struct spi_uart_work; \r
+ struct timer_list uart_timer;\r
+ struct tty_struct *tty;\r
+ struct kref kref;\r
+ struct mutex open_lock;\r
+ struct task_struct *in_spi_uart_irq; \r
+ struct circ_buf xmit;\r
+ struct uart_icount icount;\r
+ spinlock_t write_lock;\r
+ spinlock_t irq_lock;\r
+ unsigned int index;\r
+ unsigned int opened;\r
+ unsigned int regs_offset;\r
+ unsigned int uartclk;\r
+ unsigned int mctrl;\r
+ unsigned int read_status_mask;\r
+ unsigned int ignore_status_mask;\r
+ unsigned char x_char;\r
+ unsigned char ier;\r
+ unsigned char lcr;\r
+\r
+};\r
+\r
+struct spi_gpio\r
+{\r
+ struct workqueue_struct *spi_gpio_workqueue;\r
+ struct work_struct spi_gpio_work;\r
+ struct timer_list gpio_timer;\r
+\r
+};\r
+\r
+struct spi_i2c\r
+{\r
+ struct workqueue_struct *spi_i2c_workqueue;\r
+ struct work_struct spi_i2c_work;\r
+ struct timer_list i2c_timer;\r
+ struct i2c_adapter *adapter;\r
+ struct i2c_client *client;\r
+ spinlock_t i2c_lock ; \r
+ unsigned char interrupt;\r
+ unsigned char i2c_data_width[2];\r
+ unsigned int speed[2];\r
+};\r
+\r
+struct spi_dpram\r
+{\r
+ struct workqueue_struct *spi_dpram_workqueue;\r
+ struct work_struct spi_dpram_work; \r
+ struct workqueue_struct *spi_dpram_busy_workqueue;\r
+ struct work_struct spi_dpram_busy_work;\r
+ struct timer_list dpram_timer;\r
+ unsigned char *prx;\r
+ unsigned char *ptx;\r
+ unsigned int rec_len;\r
+ unsigned int send_len;\r
+ unsigned int max_rec_len;\r
+ unsigned int max_send_len;\r
+ volatile int apwrite_en;\r
+ unsigned short int dpram_addr;\r
+ struct semaphore rec_sem; \r
+ struct semaphore send_sem; \r
+ wait_queue_head_t recq, sendq;\r
+ struct miscdevice miscdev;\r
+\r
+ int (*write_dpram)(struct spi_dpram *, unsigned short int addr, unsigned char *buf, unsigned int len);\r
+ int (*read_dpram)(struct spi_dpram *, unsigned short int addr, unsigned char *buf, unsigned int len);\r
+ int (*write_ptr)(struct spi_dpram *, unsigned short int addr, unsigned int size);\r
+ int (*read_ptr)(struct spi_dpram *, unsigned short int addr);\r
+ int (*write_mailbox)(struct spi_dpram *, unsigned int mailbox);\r
+ int (*read_mailbox)(struct spi_dpram *);\r
+\r
+};\r
+\r
+struct spi_fpga_port {\r
+ const char *name;\r
+ struct spi_device *spi;\r
+ struct mutex spi_lock;\r
+ struct workqueue_struct *fpga_irq_workqueue;\r
+ struct work_struct fpga_irq_work; \r
+ struct timer_list fpga_timer;\r
+ /*spi2uart*/\r
+#ifdef CONFIG_SPI_UART\r
+ struct spi_uart uart;\r
+#endif\r
+ /*spi2gpio*/\r
+#ifdef CONFIG_SPI_GPIO\r
+ struct spi_gpio gpio;\r
+#endif\r
+ /*spi2i2c*/\r
+#ifdef CONFIG_SPI_I2C\r
+ struct spi_i2c i2c;\r
+#endif\r
+ /*spi2dpram*/\r
+#ifdef CONFIG_SPI_DPRAM\r
+ struct spi_dpram dpram;\r
+#endif\r
+\r
+};\r
+\r
+\r
+#define ICE_CC72 0\r
+#define ICE_CC196 1\r
+#define FPGA_TYPE ICE_CC196\r
+#define SEL_UART 0\r
+#define SEL_GPIO 1\r
+#define SEL_I2C 2\r
+#define SEL_DPRAM 3\r
+#define READ_TOP_INT 4\r
+\r
+/* CMD */\r
+#define ICE_SEL_UART (SEL_UART<<6)\r
+#define ICE_SEL_GPIO (SEL_GPIO<<6)\r
+#define ICE_SEL_I2C (SEL_I2C<<6)\r
+#define ICE_SEL_DPRAM (SEL_DPRAM<<6)\r
+\r
+#define ICE_SEL_WRITE (~(1<<5))\r
+#define ICE_SEL_READ (1<<5)\r
+\r
+#define ICE_SEL_UART_CH(ch) ((ch&0x03)<<3)\r
+#define ICE_SEL_READ_INT_TYPE (3<<3)\r
+\r
+/*read int type*/\r
+#define ICE_INT_TYPE_UART0 (~(1<<0))\r
+#define ICE_INT_TYPE_UART1 (~(1<<1))\r
+#define ICE_INT_TYPE_UART2 (~(1<<2))\r
+#define ICE_INT_TYPE_I2C2 (~(1<<3))\r
+#define ICE_INT_TYPE_I2C3 (~(1<<4))\r
+#define ICE_INT_TYPE_GPIO (~(1<<5))\r
+#define ICE_INT_TYPE_DPRAM (~(1<<6))\r
+\r
+#define ICE_INT_I2C_ACK (~(1<<0))\r
+#define ICE_INT_I2C_READ (~(1<<1))\r
+#define ICE_INT_I2C_WRITE (~(1<<2))\r
+\r
+/*spi to uart*/\r
+#define ICE_RXFIFO_FULL (1<<8)\r
+#define ICE_RXFIFO_NOT_FULL (~(1<<8))\r
+#define ICE_RXFIFO_EMPTY (1<<9)\r
+#define ICE_RXFIFO_NOT_EMPTY (~(1<<9))\r
+#define ICE_TXFIFO_FULL (1<<10)\r
+#define ICE_TXFIFO_NOT_FULL (~(1<<10))\r
+#define ICE_TXFIFO_EMPTY (1<<11)\r
+#define ICE_TXFIFO_NOT_EMPTY (~(1<<11))\r
+\r
+\r
+/*spi to gpio*/\r
+#define ICE_SEL_GPIO0 (0X00<<3) //INT/GPIO0\r
+#define ICE_SEL_GPIO1 (0X02<<2) //GPIO1\r
+#define ICE_SEL_GPIO2 (0X03<<2)\r
+#define ICE_SEL_GPIO3 (0X04<<2)\r
+#define ICE_SEL_GPIO4 (0X05<<2)\r
+#define ICE_SEL_GPIO5 (0X06<<2)\r
+\r
+#define ICE_SEL_GPIO0_TYPE (0X00)\r
+#define ICE_SEL_GPIO0_DIR (0X01)\r
+#define ICE_SEL_GPIO0_DATA (0X02)\r
+#define ICE_SEL_GPIO0_INT_EN (0X03)\r
+#define ICE_SEL_GPIO0_INT_TRI (0X04)\r
+#define ICE_SEL_GPIO0_INT_STATE (0X05)\r
+\r
+#define ICE_SEL_GPIO_DIR (0X01)\r
+#define ICE_SEL_GPIO_DATA (0X02)\r
+\r
+/*spi to i2c*/\r
+\r
+typedef enum I2C_ch\r
+{\r
+ I2C_CH0,\r
+ I2C_CH1,\r
+ I2C_CH2,\r
+ I2C_CH3 \r
+}eI2C_ch_t;\r
+typedef enum eI2CReadMode\r
+{\r
+ I2C_NORMAL,\r
+ I2C_NOREG\r
+}eI2ReadMode_t;\r
+\r
+typedef enum eI2RegType\r
+{\r
+ I2C_8_BIT,\r
+ I2C_16_BIT\r
+}eI2RegType_t;\r
+\r
+#define ICE_SEL_I2C_START (0<<0)\r
+#define ICE_SEL_I2C_STOP (1<<0)\r
+#define ICE_SEL_I2C_RESTART (2<<0)\r
+#define ICE_SEL_I2C_TRANS (3<<0)\r
+#define ICE_SEL_I2C_SMASK (~(3<<0))\r
+#define ICE_SEL_I2C_CH2 (0<<2)\r
+#define ICE_SEL_I2C_CH3 (1<<2)\r
+#define ICE_SEL_I2C_DEFMODE (0<<3)\r
+#define ICE_SEL_I2C_FIFO (1<<3)\r
+#define ICE_SEL_I2C_SPEED (2<<3)\r
+#define ICE_SEL_I2C_INT (3<<3)\r
+#define ICE_SEL_I2C_MMASK (~(3<<3))\r
+\r
+#define ICE_I2C_SLAVE_WRITE (0<<0)\r
+#define ICE_I2C_SLAVE_READ (1<<0)\r
+\r
+\r
+\r
+#define ICE_SEL_I2C_W8BIT (0<<2)\r
+#define ICE_SEL_I2C_W16BIT (1<<2)\r
+#define ICE_SEL_I2C_DWIDTH (2<<2)\r
+\r
+#define ICE_I2C_AD_ACK (~(1<<0))\r
+#define ICE_I2C_WRITE_ACK (~(1<<1))\r
+#define ICE_I2C_READ_ACK (~(1<<2))\r
+\r
+#define ICE_SEL_I2C_CH2_8BIT (0<<2)\r
+#define ICE_SEL_I2C_CH2_16BIT (1<<2)\r
+#define ICE_SEL_I2C_CH2_MIX (2<<2)\r
+\r
+#define ICE_SEL_I2C_CH3_8BIT (4<<2)\r
+#define ICE_SEL_I2C_CH3_16BIT (5<<2)\r
+#define ICE_SEL_I2C_CH3_MIX (6<<2)\r
+#define ICE_SEL_I2C_RD_A (7<<2)\r
+#define ICE_SEL_I2C_MASK (7<<2)\r
+#define ICE_SEL_I2C_ACK3 (1<<1)\r
+#define ICE_SEL_I2C_ACK2 (0<<1)\r
+\r
+#define INT_I2C_WRITE_ACK (2)\r
+#define INT_I2C_WRITE_NACK (3)\r
+#define INT_I2C_READ_ACK (4) \r
+#define INT_I2C_READ_NACK (5)\r
+#define INT_I2C_WRITE_MASK (~(1<<1))\r
+#define INT_I2C_READ_MASK (~(1<<2))\r
+\r
+#define ICE_SET_10K_I2C_SPEED (0x01)\r
+#define ICE_SET_100K_I2C_SPEED (0x02) \r
+#define ICE_SET_200K_I2C_SPEED (0x04)\r
+#define ICE_SET_300K_I2C_SPEED (0x08)\r
+#define ICE_SET_400K_I2C_SPEED (0x10)\r
+\r
+\r
+/*spi to dpram*/\r
+#define ICE_SEL_DPRAM_NOMAL (~(1<<5))\r
+#define ICE_SEL_DPRAM_SEM (1<<5)\r
+#define ICE_SEL_DPRAM_READ (~(1<<4))\r
+#define ICE_SEL_DPRAM_WRITE (1<<4)\r
+#define ICE_SEL_DPRAM_BL1 (0)\r
+#define ICE_SEL_DPRAM_BL32 (1)\r
+#define ICE_SEL_DPRAM_BL64 (2)\r
+#define ICE_SEL_DPRAM_BL128 (3)\r
+#define ICE_SEL_DPRAM_FULL (4)\r
+\r
+#define ICE_SEL_SEM_WRITE (0x7F)\r
+#define ICE_SEL_SEM_READ (0xBF)\r
+#define ICE_SEL_SEM_WRRD (0x3F)\r
+\r
+typedef void (*pSpiFunc)(void); //¶¨Ò庯ÊýÖ¸Õë, ÓÃÓÚµ÷Óþø¶ÔµØÖ·\r
+typedef void (*pSpiFuncIntr)(int,void *);\r
+typedef struct\r
+{\r
+ pSpiFuncIntr gpio_vector;\r
+ void *gpio_devid;\r
+}SPI_GPIO_PDATA;\r
+\r
+\r
+typedef enum eSpiGpioTypeSel\r
+{\r
+ SPI_GPIO0_IS_GPIO = 0,\r
+ SPI_GPIO0_IS_INT,\r
+}eSpiGpioTypeSel_t;\r
+\r
+\r
+\r
+typedef enum eSpiGpioPinInt\r
+{\r
+ SPI_GPIO_INT_DISABLE = 0,\r
+ SPI_GPIO_INT_ENABLE,\r
+}eSpiGpioPinInt_t;\r
+\r
+\r
+typedef enum eSpiGpioIntType \r
+{\r
+ SPI_GPIO_EDGE_FALLING = 0,\r
+ SPI_GPIO_EDGE_RISING,\r
+}eSpiGpioIntType_t;\r
+\r
+typedef enum eSpiGpioPinDirection\r
+{\r
+ SPI_GPIO_IN = 0,\r
+ SPI_GPIO_OUT,\r
+ SPI_GPIO_DIR_ERR,\r
+}eSpiGpioPinDirection_t;\r
+\r
+\r
+typedef enum eSpiGpioPinLevel\r
+{\r
+ SPI_GPIO_LOW = 0,\r
+ SPI_GPIO_HIGH,\r
+ SPI_GPIO_LEVEL_ERR,\r
+}eSpiGpioPinLevel_t;\r
+\r
+#if (FPGA_TYPE == ICE_CC72)\r
+typedef enum eSpiGpioPinNum\r
+{\r
+ SPI_GPIO_P0_00 = 0, //GPIO0[0]\r
+ SPI_GPIO_P0_01,\r
+ SPI_GPIO_P0_02,\r
+ SPI_GPIO_P0_03,\r
+ SPI_GPIO_P0_04,\r
+ SPI_GPIO_P0_05, \r
+ \r
+ SPI_GPIO_P2_00, \r
+ SPI_GPIO_P2_01,\r
+ SPI_GPIO_P2_02,\r
+ SPI_GPIO_P2_03,\r
+ SPI_GPIO_P2_04,\r
+ SPI_GPIO_P2_05,\r
+ SPI_GPIO_P2_06,\r
+ SPI_GPIO_P2_07,\r
+ SPI_GPIO_P2_08, \r
+ SPI_GPIO_P2_09 = 15, //GPIO0[15],the last interrupt/gpio pin \r
+ \r
+ SPI_GPIO_P3_00 = 16, //GPIO1[0]\r
+ SPI_GPIO_P3_01,\r
+ SPI_GPIO_P3_02,\r
+ SPI_GPIO_P3_03,\r
+ SPI_GPIO_P3_04,\r
+ SPI_GPIO_P3_05,\r
+ SPI_GPIO_P3_06,\r
+ SPI_GPIO_P3_07,\r
+ SPI_GPIO_P3_08,\r
+ SPI_GPIO_P3_09,\r
+ SPI_GPIO_P0_06 = 26, \r
+ SPI_GPIO_I2C3_SCL,\r
+ SPI_GPIO_I2C3_SDA,\r
+ SPI_GPIO_I2C4_SCL,\r
+ SPI_GPIO_I2C4_SDA,\r
+ \r
+}eSpiGpioPinNum_t;\r
+\r
+#elif (FPGA_TYPE == ICE_CC196)\r
+\r
+typedef enum eSpiGpioPinNum\r
+{\r
+ //GPIO0/INT\r
+ SPI_GPIO_P6_00 = 0, //HS_DET input \r
+ SPI_GPIO_P6_01,\r
+ SPI_GPIO_P6_02,\r
+ SPI_GPIO_P6_03,\r
+ SPI_GPIO_P6_04, //CM3605_POUT_L_INT input\r
+ SPI_GPIO_P6_05, \r
+ SPI_GPIO_P6_06, //CHG_OK input\r
+ SPI_GPIO_P6_07, //HP_HOOK input\r
+ SPI_GPIO_P6_08,\r
+ SPI_GPIO_P6_09,\r
+ SPI_GPIO_P6_10, //DEFSEL input \r
+ SPI_GPIO_P6_11, //FLASH_WP_INT input\r
+ SPI_GPIO_P6_12, //LOW_BATT_INT input\r
+ SPI_GPIO_P6_13, //DC_DET input\r
+ SPI_GPIO_P3_08, \r
+ SPI_GPIO_P3_09 = 15,\r
+\r
+ //GPIO1\r
+ SPI_GPIO_P1_00 = 16, //LCD_ON output\r
+ SPI_GPIO_P1_01, //LCD_PWR_CTRL output\r
+ SPI_GPIO_P1_02, //SD_POW_ON output\r
+ SPI_GPIO_P1_03, //WL_RST_N/WIFI_EN output\r
+ SPI_GPIO_P1_04, //HARDO,input\r
+ SPI_GPIO_P1_05, //SENSOR_PWDN output\r
+ SPI_GPIO_P1_06, //BT_PWR_EN output\r
+ SPI_GPIO_P1_07, //BT_RST output\r
+ SPI_GPIO_P1_08, //BT_WAKE_B output\r
+ SPI_GPIO_P1_09, //LCD_DISP_ON output\r
+ SPI_GPIO_P1_10, //WM_PWR_EN output\r
+ SPI_GPIO_P1_11, //HARD1,input\r
+ SPI_GPIO_P1_12, //VIB_MOTO output\r
+ SPI_GPIO_P1_13, //KEYLED_EN output\r
+ SPI_GPIO_P1_14, //CAM_RST output\r
+ SPI_GPIO_P1_15 = 31, //WL_WAKE_B output\r
+\r
+ //GPIO2\r
+ SPI_GPIO_P2_00 = 32, //Y+YD input\r
+ SPI_GPIO_P2_01, //Y-YU input\r
+ SPI_GPIO_P2_02, //AP_TD_UNDIFED input\r
+ SPI_GPIO_P2_03, //AP_PW_EN_TD output\r
+ SPI_GPIO_P2_04, //AP_RESET_TD output\r
+ SPI_GPIO_P2_05, //AP_SHUTDOWN_TD_PMU output\r
+ SPI_GPIO_P2_06, //AP_RESET_CMMB output\r
+ SPI_GPIO_P2_07, //AP_CHECK_TD_STATUS input\r
+ SPI_GPIO_P2_08, //CHARGE_CURRENT_SEL output\r
+ SPI_GPIO_P2_09, //AP_PWD_CMMB output\r
+ SPI_GPIO_P2_10, //X-XL input\r
+ SPI_GPIO_P2_11, //X+XR input\r
+ SPI_GPIO_P2_12, //LCD_RESET output\r
+ SPI_GPIO_P2_13, //USB_PWR_EN output\r
+ SPI_GPIO_P2_14, //WL_HOST_WAKE_B output\r
+ SPI_GPIO_P2_15 = 47, //TOUCH_SCREEN_RST output\r
+\r
+ //GPIO3\r
+ SPI_GPIO_P0_00 = 48, //\r
+ SPI_GPIO_P0_01,\r
+ SPI_GPIO_P0_02,\r
+ SPI_GPIO_P0_03,\r
+ SPI_GPIO_P0_04,\r
+ SPI_GPIO_P0_05,\r
+ SPI_GPIO_P0_06,\r
+ SPI_GPIO_P0_07,\r
+ SPI_GPIO_P0_08,\r
+ SPI_GPIO_P0_09, //FPGAС°å¸ÃÒý½ÅδÒý³ö C5\r
+ SPI_GPIO_P0_10,\r
+ SPI_GPIO_P0_11,\r
+ SPI_GPIO_P0_12,\r
+ SPI_GPIO_P0_13,\r
+ SPI_GPIO_P0_14,\r
+ SPI_GPIO_P0_15 = 63,\r
+\r
+ //GPIO4\r
+ SPI_GPIO_P4_00 = 64, \r
+ SPI_GPIO_P4_01, \r
+ SPI_GPIO_P4_02,\r
+ SPI_GPIO_P4_03,\r
+ SPI_GPIO_P4_04,\r
+ SPI_GPIO_P4_05,\r
+ SPI_GPIO_P4_06, //CHARGER_INT_END input\r
+ SPI_GPIO_P4_07, //CM3605_PWD output\r
+ SPI_GPIO_P3_00, \r
+ SPI_GPIO_P3_01,\r
+ SPI_GPIO_P3_02,\r
+ SPI_GPIO_P3_03,\r
+ SPI_GPIO_P3_04,\r
+ SPI_GPIO_P3_05,\r
+ SPI_GPIO_P3_06,\r
+ SPI_GPIO_P3_07 = 79, \r
+\r
+ //GPIO5\r
+ SPI_GPIO_P4_08 = 80, //CM3605_PS_SHUTDOWN\r
+ SPI_GPIO_P0_TXD2, //temp\r
+\r
+}eSpiGpioPinNum_t;\r
+\r
+#endif\r
+\r
+\r
+typedef enum eSpiGpioPinIntIsr\r
+{\r
+ SPI_GPIO_IS_INT = 0,\r
+ SPI_GPIO_NO_INT,\r
+}eSpiGpioPinIntIsr_t;\r
+\r
+extern struct spi_fpga_port *pFpgaPort;\r
+extern unsigned int spi_in(struct spi_fpga_port *port, int reg, int type);\r
+extern void spi_out(struct spi_fpga_port *port, int reg, int value, int type);\r
+\r
+#if defined(CONFIG_SPI_UART)\r
+extern void spi_uart_handle_irq(struct spi_device *spi);\r
+extern int spi_uart_register(struct spi_fpga_port *port);\r
+extern int spi_uart_unregister(struct spi_fpga_port *port);\r
+#endif\r
+#if defined(CONFIG_SPI_GPIO)\r
+extern int spi_gpio_int_sel(eSpiGpioPinNum_t PinNum,eSpiGpioTypeSel_t type);\r
+extern int spi_gpio_set_pindirection(eSpiGpioPinNum_t PinNum,eSpiGpioPinDirection_t direction);\r
+extern int spi_gpio_set_pinlevel(eSpiGpioPinNum_t PinNum, eSpiGpioPinLevel_t PinLevel);\r
+extern eSpiGpioPinLevel_t spi_gpio_get_pinlevel(eSpiGpioPinNum_t PinNum);\r
+extern int spi_gpio_enable_int(eSpiGpioPinNum_t PinNum);\r
+extern int spi_gpio_disable_int(eSpiGpioPinNum_t PinNum);\r
+extern int spi_gpio_set_int_trigger(eSpiGpioPinNum_t PinNum,eSpiGpioIntType_t IntType);\r
+extern int spi_gpio_read_iir(void);\r
+extern int spi_request_gpio_irq(eSpiGpioPinNum_t PinNum, pSpiFunc Routine, eSpiGpioIntType_t IntType,void *dev_id);\r
+extern int spi_free_gpio_irq(eSpiGpioPinNum_t PinNum);\r
+extern int spi_gpio_handle_irq(struct spi_device *spi);\r
+extern int spi_gpio_init(void);\r
+extern int spi_gpio_register(struct spi_fpga_port *port);\r
+extern int spi_gpio_unregister(struct spi_fpga_port *port);\r
+#endif\r
+#if defined(CONFIG_SPI_I2C)\r
+extern int spi_i2c_handle_irq(struct spi_fpga_port *port,unsigned char channel);\r
+extern int spi_i2c_register(struct spi_fpga_port *port,int num);\r
+extern int spi_i2c_unregister(struct spi_fpga_port *port);\r
+#endif\r
+#if defined(CONFIG_SPI_DPRAM)\r
+extern int spi_dpram_handle_irq(struct spi_device *spi);\r
+extern int spi_dpram_register(struct spi_fpga_port *port);\r
+extern int spi_dpram_unregister(struct spi_fpga_port *port);\r
+#endif\r
+\r
+#endif\r
projects / firefly-linux-kernel-4.4.55.git / commitdiff