--- /dev/null
+obj-y += common.o
+obj-y += io.o
+obj-y += reset.o
+obj-$(CONFIG_PM) += pm.o
--- /dev/null
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+
+#include <asm/pgtable-hwdef.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <plat/sram.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+//#include <mach/iomux.h>
+#include <mach/fiq.h>
+//#include <mach/loader.h>
+//#include <mach/ddr.h>
+
+static void __init rk2928_cpu_axi_init(void)
+{
+#if 0
+ writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x0088); // cpu0
+ writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x0108); // dmac1
+ writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x0188); // cpu1r
+ writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x0388); // cpu1w
+ writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x4008); // peri
+ writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x5008); // gpu
+ writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x6008); // vpu
+ writel_relaxed(0xa, RK2928_CPU_AXI_BUS_BASE + 0x7008); // lcdc0
+ writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x7088); // cif0
+ writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x7108); // ipp
+ writel_relaxed(0xa, RK2928_CPU_AXI_BUS_BASE + 0x7188); // lcdc1
+ writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x7208); // cif1
+ writel_relaxed(0x0, RK2928_CPU_AXI_BUS_BASE + 0x7288); // rga
+#endif
+ writel_relaxed(0x3f, RK2928_CPU_AXI_BUS_BASE + 0x0014); // memory scheduler read latency
+ dsb();
+}
+
+#define L2_LY_SP_OFF (0)
+#define L2_LY_SP_MSK (0x7)
+
+#define L2_LY_RD_OFF (4)
+#define L2_LY_RD_MSK (0x7)
+
+#define L2_LY_WR_OFF (8)
+#define L2_LY_WR_MSK (0x7)
+#define L2_LY_SET(ly,off) (((ly)-1)<<(off))
+
+static void __init rk2928_l2_cache_init(void)
+{
+#ifdef CONFIG_CACHE_L2X0
+ u32 aux_ctrl, aux_ctrl_mask;
+
+ writel_relaxed(L2_LY_SET(1,L2_LY_SP_OFF)
+ |L2_LY_SET(1,L2_LY_RD_OFF)
+ |L2_LY_SET(1,L2_LY_WR_OFF), RK2928_L2C_BASE + L2X0_TAG_LATENCY_CTRL);
+ writel_relaxed(L2_LY_SET(4,L2_LY_SP_OFF)
+ |L2_LY_SET(6,L2_LY_RD_OFF)
+ |L2_LY_SET(1,L2_LY_WR_OFF), RK2928_L2C_BASE + L2X0_DATA_LATENCY_CTRL);
+
+ /* L2X0 Prefetch Control */
+ writel_relaxed(0x70000003, RK2928_L2C_BASE + L2X0_PREFETCH_CTRL);
+
+ /* L2X0 Power Control */
+ writel_relaxed(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, RK2928_L2C_BASE + L2X0_POWER_CTRL);
+
+ aux_ctrl = (
+// (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | // 16-way
+ (0x1 << 25) | // Round-robin cache replacement policy
+ (0x1 << 0) | // Full Line of Zero Enable
+ (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
+// (0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | // 32KB way-size
+ (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
+ (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
+ (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT) );
+
+ aux_ctrl_mask = ~(
+// (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | // 16-way
+ (0x1 << 25) | // Cache replacement policy
+ (0x1 << 0) | // Full Line of Zero Enable
+ (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
+// (0x7 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | // 32KB way-size
+ (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
+ (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
+ (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT) );
+
+ l2x0_init(RK2928_L2C_BASE, aux_ctrl, aux_ctrl_mask);
+#endif
+}
+
+static int boot_mode;
+static void __init rk2928_boot_mode_init(void)
+{
+#if 0
+ u32 boot_flag = readl_relaxed(RK2928_PMU_BASE + PMU_SYS_REG0);
+ boot_mode = readl_relaxed(RK2928_PMU_BASE + PMU_SYS_REG1);
+
+ if (boot_flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER)) {
+ boot_mode = BOOT_MODE_RECOVERY;
+ } else if (strstr(boot_command_line, "(parameter)")) {
+ boot_mode = BOOT_MODE_RECOVERY;
+ }
+ if (boot_mode || boot_flag)
+ printk("Boot mode: %d flag: 0x%08x\n", boot_mode, boot_flag);
+#endif
+}
+
+int board_boot_mode(void)
+{
+ return boot_mode;
+}
+EXPORT_SYMBOL(board_boot_mode);
+
+void __init rk2928_init_irq(void)
+{
+ gic_init(0, IRQ_LOCALTIMER, GIC_DIST_BASE, GIC_CPU_BASE);
+#ifdef CONFIG_FIQ
+ rk_fiq_init();
+#endif
+// rk30_gpio_init();
+}
+
+extern void __init rk2928_map_common_io(void);
+extern int __init clk_disable_unused(void);
+
+void __init rk2928_map_io(void)
+{
+ rk2928_map_common_io();
+ rk29_setup_early_printk();
+ rk2928_cpu_axi_init();
+ rk29_sram_init();
+// board_clock_init();
+ rk2928_l2_cache_init();
+// ddr_init(DDR_TYPE, DDR_FREQ);
+// clk_disable_unused();
+// rk2928_iomux_init();
+ rk2928_boot_mode_init();
+}
+
+extern u32 ddr_get_cap(void);
+static __init u32 rk2928_get_ddr_size(void)
+{
+#ifdef CONFIG_MACH_RK2928_FPGA
+ return SZ_64M;
+#endif
+}
+
+void __init rk2928_fixup(struct machine_desc *desc, struct tag *tags,
+ char **cmdline, struct meminfo *mi)
+{
+ mi->nr_banks = 1;
+ mi->bank[0].start = PLAT_PHYS_OFFSET;
+ mi->bank[0].size = rk2928_get_ddr_size();
+}
+
--- /dev/null
+#ifndef __MACH_BOARD_H
+#define __MACH_BOARD_H
+
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/types.h>
+#include <linux/timer.h>
+#include <linux/notifier.h>
+#include <asm/setup.h>
+#include <plat/board.h>
+#include <mach/sram.h>
+#include <linux/i2c-gpio.h>
+
+extern struct rk29_sdmmc_platform_data default_sdmmc0_data;
+extern struct rk29_sdmmc_platform_data default_sdmmc1_data;
+
+extern struct i2c_gpio_platform_data default_i2c_gpio_data;
+
+void __init rk2928_map_common_io(void);
+void __init rk2928_init_irq(void);
+void __init rk2928_map_io(void);
+struct machine_desc;
+void __init rk2928_fixup(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi);
+void __init rk2928_clock_data_init(unsigned long gpll,unsigned long cpll,u32 flags);
+void __init board_clock_init(void);
+void board_gpio_suspend(void);
+void board_gpio_resume(void);
+void __sramfunc board_pmu_suspend(void);
+void __sramfunc board_pmu_resume(void);
+
+extern struct sys_timer rk2928_timer;
+
+#endif
--- /dev/null
+#ifndef __MACH_GPIO_H
+#define __MACH_GPIO_H
+
+#include <mach/irqs.h>
+#include <linux/init.h>
+
+//¶¨ÒåGPIOÏà¹Ø¼Ä´æÆ÷Æ«ÒƵØÖ·
+#define GPIO_SWPORT_DR 0x00
+#define GPIO_SWPORT_DDR 0x04
+#define GPIO_INTEN 0x30
+#define GPIO_INTMASK 0x34
+#define GPIO_INTTYPE_LEVEL 0x38
+#define GPIO_INT_POLARITY 0x3c
+#define GPIO_INT_STATUS 0x40
+#define GPIO_INT_RAWSTATUS 0x44
+#define GPIO_DEBOUNCE 0x48
+#define GPIO_PORTS_EOI 0x4c
+#define GPIO_EXT_PORT 0x50
+#define GPIO_LS_SYNC 0x60
+
+#define NUM_GROUP 32
+#define MAX_BANK 4
+
+#define PIN_BASE NR_GIC_IRQS
+
+#define RK2928_TOTOL_GPIO_NUM (NUM_GROUP*MAX_BANK)
+
+#define SPI_FPGA_EXPANDER_BASE (PIN_BASE+RK2928_TOTOL_GPIO_NUM)
+
+#if defined (CONFIG_SPI_FPGA_GPIO)
+#define GPIO_EXPANDER_BASE (PIN_BASE+RK2928_TOTOL_GPIO_NUM+CONFIG_SPI_FPGA_GPIO_NUM)
+#else
+#define GPIO_EXPANDER_BASE (PIN_BASE+RK2928_TOTOL_GPIO_NUM)
+#endif
+
+#if defined(CONFIG_IOEXTEND_TCA6424)
+#define TCA6424_TOTOL_GPIO_NUM 24
+#define TCA6424_TOTOL_GPIO_IRQ_NUM 24
+#define TCA6424_GPIO_EXPANDER_BASE GPIO_EXPANDER_BASE
+#else
+#define TCA6424_TOTOL_GPIO_NUM 0
+#define TCA6424_TOTOL_GPIO_IRQ_NUM 0
+#endif
+
+#if defined(CONFIG_GPIO_WM831X)
+#define WM831X_TOTOL_GPIO_NUM 12
+#define WM831X_GPIO_EXPANDER_BASE (GPIO_EXPANDER_BASE+TCA6424_TOTOL_GPIO_NUM)
+#else
+#define WM831X_TOTOL_GPIO_NUM 0
+#define WM831X_GPIO_EXPANDER_BASE (GPIO_EXPANDER_BASE+TCA6424_TOTOL_GPIO_NUM)
+#endif
+
+#if defined (CONFIG_GPIO_WM8994)
+#define CONFIG_GPIO_WM8994_NUM 11
+#define WM8994_GPIO_EXPANDER_BASE (GPIO_EXPANDER_BASE+WM831X_TOTOL_GPIO_NUM)
+#else
+#define CONFIG_GPIO_WM8994_NUM 0
+#endif
+
+//¶¨ÒåGPIOµÄPIN¿Ú×î´óÊýÄ¿¡£CONFIG_SPI_FPGA_GPIO_NUM±íʾFPGAµÄPIN½ÅÊý¡£
+#define ARCH_NR_GPIOS (PIN_BASE + RK2928_TOTOL_GPIO_NUM + TCA6424_TOTOL_GPIO_NUM + WM831X_TOTOL_GPIO_NUM + CONFIG_SPI_FPGA_GPIO_NUM + CONFIG_GPIO_WM8994_NUM)
+
+#define INVALID_GPIO -1
+
+#define RK2928_PIN0_PA0 (0*NUM_GROUP + PIN_BASE + 0)
+#define RK2928_PIN0_PA1 (0*NUM_GROUP + PIN_BASE + 1)
+#define RK2928_PIN0_PA2 (0*NUM_GROUP + PIN_BASE + 2)
+#define RK2928_PIN0_PA3 (0*NUM_GROUP + PIN_BASE + 3)
+#define RK2928_PIN0_PA4 (0*NUM_GROUP + PIN_BASE + 4)
+#define RK2928_PIN0_PA5 (0*NUM_GROUP + PIN_BASE + 5)
+#define RK2928_PIN0_PA6 (0*NUM_GROUP + PIN_BASE + 6)
+#define RK2928_PIN0_PA7 (0*NUM_GROUP + PIN_BASE + 7)
+#define RK2928_PIN0_PB0 (0*NUM_GROUP + PIN_BASE + 8)
+#define RK2928_PIN0_PB1 (0*NUM_GROUP + PIN_BASE + 9)
+#define RK2928_PIN0_PB2 (0*NUM_GROUP + PIN_BASE + 10)
+#define RK2928_PIN0_PB3 (0*NUM_GROUP + PIN_BASE + 11)
+#define RK2928_PIN0_PB4 (0*NUM_GROUP + PIN_BASE + 12)
+#define RK2928_PIN0_PB5 (0*NUM_GROUP + PIN_BASE + 13)
+#define RK2928_PIN0_PB6 (0*NUM_GROUP + PIN_BASE + 14)
+#define RK2928_PIN0_PB7 (0*NUM_GROUP + PIN_BASE + 15)
+#define RK2928_PIN0_PC0 (0*NUM_GROUP + PIN_BASE + 16)
+#define RK2928_PIN0_PC1 (0*NUM_GROUP + PIN_BASE + 17)
+#define RK2928_PIN0_PC2 (0*NUM_GROUP + PIN_BASE + 18)
+#define RK2928_PIN0_PC3 (0*NUM_GROUP + PIN_BASE + 19)
+#define RK2928_PIN0_PC4 (0*NUM_GROUP + PIN_BASE + 20)
+#define RK2928_PIN0_PC5 (0*NUM_GROUP + PIN_BASE + 21)
+#define RK2928_PIN0_PC6 (0*NUM_GROUP + PIN_BASE + 22)
+#define RK2928_PIN0_PC7 (0*NUM_GROUP + PIN_BASE + 23)
+#define RK2928_PIN0_PD0 (0*NUM_GROUP + PIN_BASE + 24)
+#define RK2928_PIN0_PD1 (0*NUM_GROUP + PIN_BASE + 25)
+#define RK2928_PIN0_PD2 (0*NUM_GROUP + PIN_BASE + 26)
+#define RK2928_PIN0_PD3 (0*NUM_GROUP + PIN_BASE + 27)
+#define RK2928_PIN0_PD4 (0*NUM_GROUP + PIN_BASE + 28)
+#define RK2928_PIN0_PD5 (0*NUM_GROUP + PIN_BASE + 29)
+#define RK2928_PIN0_PD6 (0*NUM_GROUP + PIN_BASE + 30)
+#define RK2928_PIN0_PD7 (0*NUM_GROUP + PIN_BASE + 31)
+
+#define RK2928_PIN1_PA0 (1*NUM_GROUP + PIN_BASE + 0)
+#define RK2928_PIN1_PA1 (1*NUM_GROUP + PIN_BASE + 1)
+#define RK2928_PIN1_PA2 (1*NUM_GROUP + PIN_BASE + 2)
+#define RK2928_PIN1_PA3 (1*NUM_GROUP + PIN_BASE + 3)
+#define RK2928_PIN1_PA4 (1*NUM_GROUP + PIN_BASE + 4)
+#define RK2928_PIN1_PA5 (1*NUM_GROUP + PIN_BASE + 5)
+#define RK2928_PIN1_PA6 (1*NUM_GROUP + PIN_BASE + 6)
+#define RK2928_PIN1_PA7 (1*NUM_GROUP + PIN_BASE + 7)
+#define RK2928_PIN1_PB0 (1*NUM_GROUP + PIN_BASE + 8)
+#define RK2928_PIN1_PB1 (1*NUM_GROUP + PIN_BASE + 9)
+#define RK2928_PIN1_PB2 (1*NUM_GROUP + PIN_BASE + 10)
+#define RK2928_PIN1_PB3 (1*NUM_GROUP + PIN_BASE + 11)
+#define RK2928_PIN1_PB4 (1*NUM_GROUP + PIN_BASE + 12)
+#define RK2928_PIN1_PB5 (1*NUM_GROUP + PIN_BASE + 13)
+#define RK2928_PIN1_PB6 (1*NUM_GROUP + PIN_BASE + 14)
+#define RK2928_PIN1_PB7 (1*NUM_GROUP + PIN_BASE + 15)
+#define RK2928_PIN1_PC0 (1*NUM_GROUP + PIN_BASE + 16)
+#define RK2928_PIN1_PC1 (1*NUM_GROUP + PIN_BASE + 17)
+#define RK2928_PIN1_PC2 (1*NUM_GROUP + PIN_BASE + 18)
+#define RK2928_PIN1_PC3 (1*NUM_GROUP + PIN_BASE + 19)
+#define RK2928_PIN1_PC4 (1*NUM_GROUP + PIN_BASE + 20)
+#define RK2928_PIN1_PC5 (1*NUM_GROUP + PIN_BASE + 21)
+#define RK2928_PIN1_PC6 (1*NUM_GROUP + PIN_BASE + 22)
+#define RK2928_PIN1_PC7 (1*NUM_GROUP + PIN_BASE + 23)
+#define RK2928_PIN1_PD0 (1*NUM_GROUP + PIN_BASE + 24)
+#define RK2928_PIN1_PD1 (1*NUM_GROUP + PIN_BASE + 25)
+#define RK2928_PIN1_PD2 (1*NUM_GROUP + PIN_BASE + 26)
+#define RK2928_PIN1_PD3 (1*NUM_GROUP + PIN_BASE + 27)
+#define RK2928_PIN1_PD4 (1*NUM_GROUP + PIN_BASE + 28)
+#define RK2928_PIN1_PD5 (1*NUM_GROUP + PIN_BASE + 29)
+#define RK2928_PIN1_PD6 (1*NUM_GROUP + PIN_BASE + 30)
+#define RK2928_PIN1_PD7 (1*NUM_GROUP + PIN_BASE + 31)
+
+#define RK2928_PIN2_PA0 (2*NUM_GROUP + PIN_BASE + 0)
+#define RK2928_PIN2_PA1 (2*NUM_GROUP + PIN_BASE + 1)
+#define RK2928_PIN2_PA2 (2*NUM_GROUP + PIN_BASE + 2)
+#define RK2928_PIN2_PA3 (2*NUM_GROUP + PIN_BASE + 3)
+#define RK2928_PIN2_PA4 (2*NUM_GROUP + PIN_BASE + 4)
+#define RK2928_PIN2_PA5 (2*NUM_GROUP + PIN_BASE + 5)
+#define RK2928_PIN2_PA6 (2*NUM_GROUP + PIN_BASE + 6)
+#define RK2928_PIN2_PA7 (2*NUM_GROUP + PIN_BASE + 7)
+#define RK2928_PIN2_PB0 (2*NUM_GROUP + PIN_BASE + 8)
+#define RK2928_PIN2_PB1 (2*NUM_GROUP + PIN_BASE + 9)
+#define RK2928_PIN2_PB2 (2*NUM_GROUP + PIN_BASE + 10)
+#define RK2928_PIN2_PB3 (2*NUM_GROUP + PIN_BASE + 11)
+#define RK2928_PIN2_PB4 (2*NUM_GROUP + PIN_BASE + 12)
+#define RK2928_PIN2_PB5 (2*NUM_GROUP + PIN_BASE + 13)
+#define RK2928_PIN2_PB6 (2*NUM_GROUP + PIN_BASE + 14)
+#define RK2928_PIN2_PB7 (2*NUM_GROUP + PIN_BASE + 15)
+#define RK2928_PIN2_PC0 (2*NUM_GROUP + PIN_BASE + 16)
+#define RK2928_PIN2_PC1 (2*NUM_GROUP + PIN_BASE + 17)
+#define RK2928_PIN2_PC2 (2*NUM_GROUP + PIN_BASE + 18)
+#define RK2928_PIN2_PC3 (2*NUM_GROUP + PIN_BASE + 19)
+#define RK2928_PIN2_PC4 (2*NUM_GROUP + PIN_BASE + 20)
+#define RK2928_PIN2_PC5 (2*NUM_GROUP + PIN_BASE + 21)
+#define RK2928_PIN2_PC6 (2*NUM_GROUP + PIN_BASE + 22)
+#define RK2928_PIN2_PC7 (2*NUM_GROUP + PIN_BASE + 23)
+#define RK2928_PIN2_PD0 (2*NUM_GROUP + PIN_BASE + 24)
+#define RK2928_PIN2_PD1 (2*NUM_GROUP + PIN_BASE + 25)
+#define RK2928_PIN2_PD2 (2*NUM_GROUP + PIN_BASE + 26)
+#define RK2928_PIN2_PD3 (2*NUM_GROUP + PIN_BASE + 27)
+#define RK2928_PIN2_PD4 (2*NUM_GROUP + PIN_BASE + 28)
+#define RK2928_PIN2_PD5 (2*NUM_GROUP + PIN_BASE + 29)
+#define RK2928_PIN2_PD6 (2*NUM_GROUP + PIN_BASE + 30)
+#define RK2928_PIN2_PD7 (2*NUM_GROUP + PIN_BASE + 31)
+
+#define RK2928_PIN3_PA0 (3*NUM_GROUP + PIN_BASE + 0)
+#define RK2928_PIN3_PA1 (3*NUM_GROUP + PIN_BASE + 1)
+#define RK2928_PIN3_PA2 (3*NUM_GROUP + PIN_BASE + 2)
+#define RK2928_PIN3_PA3 (3*NUM_GROUP + PIN_BASE + 3)
+#define RK2928_PIN3_PA4 (3*NUM_GROUP + PIN_BASE + 4)
+#define RK2928_PIN3_PA5 (3*NUM_GROUP + PIN_BASE + 5)
+#define RK2928_PIN3_PA6 (3*NUM_GROUP + PIN_BASE + 6)
+#define RK2928_PIN3_PA7 (3*NUM_GROUP + PIN_BASE + 7)
+#define RK2928_PIN3_PB0 (3*NUM_GROUP + PIN_BASE + 8)
+#define RK2928_PIN3_PB1 (3*NUM_GROUP + PIN_BASE + 9)
+#define RK2928_PIN3_PB2 (3*NUM_GROUP + PIN_BASE + 10)
+#define RK2928_PIN3_PB3 (3*NUM_GROUP + PIN_BASE + 11)
+#define RK2928_PIN3_PB4 (3*NUM_GROUP + PIN_BASE + 12)
+#define RK2928_PIN3_PB5 (3*NUM_GROUP + PIN_BASE + 13)
+#define RK2928_PIN3_PB6 (3*NUM_GROUP + PIN_BASE + 14)
+#define RK2928_PIN3_PB7 (3*NUM_GROUP + PIN_BASE + 15)
+#define RK2928_PIN3_PC0 (3*NUM_GROUP + PIN_BASE + 16)
+#define RK2928_PIN3_PC1 (3*NUM_GROUP + PIN_BASE + 17)
+#define RK2928_PIN3_PC2 (3*NUM_GROUP + PIN_BASE + 18)
+#define RK2928_PIN3_PC3 (3*NUM_GROUP + PIN_BASE + 19)
+#define RK2928_PIN3_PC4 (3*NUM_GROUP + PIN_BASE + 20)
+#define RK2928_PIN3_PC5 (3*NUM_GROUP + PIN_BASE + 21)
+#define RK2928_PIN3_PC6 (3*NUM_GROUP + PIN_BASE + 22)
+#define RK2928_PIN3_PC7 (3*NUM_GROUP + PIN_BASE + 23)
+#define RK2928_PIN3_PD0 (3*NUM_GROUP + PIN_BASE + 24)
+#define RK2928_PIN3_PD1 (3*NUM_GROUP + PIN_BASE + 25)
+#define RK2928_PIN3_PD2 (3*NUM_GROUP + PIN_BASE + 26)
+#define RK2928_PIN3_PD3 (3*NUM_GROUP + PIN_BASE + 27)
+#define RK2928_PIN3_PD4 (3*NUM_GROUP + PIN_BASE + 28)
+#define RK2928_PIN3_PD5 (3*NUM_GROUP + PIN_BASE + 29)
+#define RK2928_PIN3_PD6 (3*NUM_GROUP + PIN_BASE + 30)
+#define RK2928_PIN3_PD7 (3*NUM_GROUP + PIN_BASE + 31)
+
+#if defined(CONFIG_SPI_FPGA_GPIO)
+#define FPGA_PIO0_00 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 0)
+#define FPGA_PIO0_01 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 1)
+#define FPGA_PIO0_02 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 2)
+#define FPGA_PIO0_03 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 3)
+#define FPGA_PIO0_04 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 4)
+#define FPGA_PIO0_05 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 5)
+#define FPGA_PIO0_06 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 6)
+#define FPGA_PIO0_07 (SPI_FPGA_EXPANDER_BASE + 0*NUM_GROUP + 7)
+
+#define FPGA_PIO0_08 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 0)
+#define FPGA_PIO0_09 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 1)
+#define FPGA_PIO0_10 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 2)
+#define FPGA_PIO0_11 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 3)
+#define FPGA_PIO0_12 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 4)
+#define FPGA_PIO0_13 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 5)
+#define FPGA_PIO0_14 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 6)
+#define FPGA_PIO0_15 (SPI_FPGA_EXPANDER_BASE + 1*NUM_GROUP + 7)
+
+#define FPGA_PIO1_00 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 0)
+#define FPGA_PIO1_01 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 1)
+#define FPGA_PIO1_02 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 2)
+#define FPGA_PIO1_03 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 3)
+#define FPGA_PIO1_04 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 4)
+#define FPGA_PIO1_05 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 5)
+#define FPGA_PIO1_06 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 6)
+#define FPGA_PIO1_07 (SPI_FPGA_EXPANDER_BASE + 2*NUM_GROUP + 7)
+
+#define FPGA_PIO1_08 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 0)
+#define FPGA_PIO1_09 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 1)
+#define FPGA_PIO1_10 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 2)
+#define FPGA_PIO1_11 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 3)
+#define FPGA_PIO1_12 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 4)
+#define FPGA_PIO1_13 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 5)
+#define FPGA_PIO1_14 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 6)
+#define FPGA_PIO1_15 (SPI_FPGA_EXPANDER_BASE + 3*NUM_GROUP + 7)
+
+#define FPGA_PIO2_00 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 0)
+#define FPGA_PIO2_01 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 1)
+#define FPGA_PIO2_02 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 2)
+#define FPGA_PIO2_03 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 3)
+#define FPGA_PIO2_04 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 4)
+#define FPGA_PIO2_05 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 5)
+#define FPGA_PIO2_06 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 6)
+#define FPGA_PIO2_07 (SPI_FPGA_EXPANDER_BASE + 4*NUM_GROUP + 7)
+
+#define FPGA_PIO2_08 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 0)
+#define FPGA_PIO2_09 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 1)
+#define FPGA_PIO2_10 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 2)
+#define FPGA_PIO2_11 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 3)
+#define FPGA_PIO2_12 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 4)
+#define FPGA_PIO2_13 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 5)
+#define FPGA_PIO2_14 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 6)
+#define FPGA_PIO2_15 (SPI_FPGA_EXPANDER_BASE + 5*NUM_GROUP + 7)
+
+#define FPGA_PIO3_00 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 0)
+#define FPGA_PIO3_01 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 1)
+#define FPGA_PIO3_02 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 2)
+#define FPGA_PIO3_03 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 3)
+#define FPGA_PIO3_04 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 4)
+#define FPGA_PIO3_05 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 5)
+#define FPGA_PIO3_06 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 6)
+#define FPGA_PIO3_07 (SPI_FPGA_EXPANDER_BASE + 6*NUM_GROUP + 7)
+
+#define FPGA_PIO3_08 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 0)
+#define FPGA_PIO3_09 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 1)
+#define FPGA_PIO3_10 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 2)
+#define FPGA_PIO3_11 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 3)
+#define FPGA_PIO3_12 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 4)
+#define FPGA_PIO3_13 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 5)
+#define FPGA_PIO3_14 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 6)
+#define FPGA_PIO3_15 (SPI_FPGA_EXPANDER_BASE + 7*NUM_GROUP + 7)
+
+#define FPGA_PIO4_00 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 0)
+#define FPGA_PIO4_01 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 1)
+#define FPGA_PIO4_02 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 2)
+#define FPGA_PIO4_03 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 3)
+#define FPGA_PIO4_04 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 4)
+#define FPGA_PIO4_05 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 5)
+#define FPGA_PIO4_06 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 6)
+#define FPGA_PIO4_07 (SPI_FPGA_EXPANDER_BASE + 8*NUM_GROUP + 7)
+
+#define FPGA_PIO4_08 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 0)
+#define FPGA_PIO4_09 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 1)
+#define FPGA_PIO4_10 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 2)
+#define FPGA_PIO4_11 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 3)
+#define FPGA_PIO4_12 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 4)
+#define FPGA_PIO4_13 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 5)
+#define FPGA_PIO4_14 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 6)
+#define FPGA_PIO4_15 (SPI_FPGA_EXPANDER_BASE + 9*NUM_GROUP + 7)
+
+#define FPGA_PIO5_00 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 0)
+#define FPGA_PIO5_01 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 1)
+#define FPGA_PIO5_02 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 2)
+#define FPGA_PIO5_03 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 3)
+#define FPGA_PIO5_04 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 4)
+#define FPGA_PIO5_05 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 5)
+#define FPGA_PIO5_06 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 6)
+#define FPGA_PIO5_07 (SPI_FPGA_EXPANDER_BASE + 10*NUM_GROUP + 7)
+
+#define FPGA_PIO5_08 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 0)
+#define FPGA_PIO5_09 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 1)
+#define FPGA_PIO5_10 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 2)
+#define FPGA_PIO5_11 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 3)
+#define FPGA_PIO5_12 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 4)
+#define FPGA_PIO5_13 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 5)
+#define FPGA_PIO5_14 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 6)
+#define FPGA_PIO5_15 (SPI_FPGA_EXPANDER_BASE + 11*NUM_GROUP + 7)
+
+#endif
+
+#if defined(CONFIG_IOEXTEND_TCA6424)
+#define TCA6424_P00 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 0)
+#define TCA6424_P01 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 1)
+#define TCA6424_P02 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 2)
+#define TCA6424_P03 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 3)
+#define TCA6424_P04 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 4)
+#define TCA6424_P05 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 5)
+#define TCA6424_P06 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 6)
+#define TCA6424_P07 (TCA6424_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 7)
+
+#define TCA6424_P10 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 0)
+#define TCA6424_P11 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 1)
+#define TCA6424_P12 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 2)
+#define TCA6424_P13 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 3)
+#define TCA6424_P14 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 4)
+#define TCA6424_P15 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 5)
+#define TCA6424_P16 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 6)
+#define TCA6424_P17 (TCA6424_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 7)
+
+#define TCA6424_P20 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 0)
+#define TCA6424_P21 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 1)
+#define TCA6424_P22 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 2)
+#define TCA6424_P23 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 3)
+#define TCA6424_P24 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 4)
+#define TCA6424_P25 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 5)
+#define TCA6424_P26 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 6)
+#define TCA6424_P27 (TCA6424_GPIO_EXPANDER_BASE + 2*NUM_GROUP + 7)
+#endif
+
+#if defined(CONFIG_GPIO_WM831X)
+#define WM831X_P01 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 0)
+#define WM831X_P02 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 1)
+#define WM831X_P03 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 2)
+#define WM831X_P04 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 3)
+#define WM831X_P05 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 4)
+#define WM831X_P06 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 5)
+#define WM831X_P07 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 6)
+#define WM831X_P08 (WM831X_GPIO_EXPANDER_BASE + 0*NUM_GROUP + 7)
+
+#define WM831X_P09 (WM831X_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 0)
+#define WM831X_P10 (WM831X_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 1)
+#define WM831X_P11 (WM831X_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 2)
+#define WM831X_P12 (WM831X_GPIO_EXPANDER_BASE + 1*NUM_GROUP + 3)
+#endif
+
+#include <plat/gpio.h>
+
+#ifndef __ASSEMBLY__
+static inline int gpio_to_irq(unsigned gpio)
+{
+ return gpio - PIN_BASE + NR_GIC_IRQS;
+}
+
+static inline int irq_to_gpio(unsigned irq)
+{
+ return irq - NR_GIC_IRQS + PIN_BASE;
+}
+#endif /* __ASSEMBLY__ */
+
+#endif
--- /dev/null
+#ifndef __MACH_IO_H
+#define __MACH_IO_H
+
+#include <plat/io.h>
+
+/*
+ * RK2928 IO memory map:
+ *
+ * Virt Phys Size What
+ * ---------------------------------------------------------------------------
+ * FEA00000 10000000 3M
+ * FED00000 20000000 1M
+ * FEF00000 0 8K SRAM
+ */
+
+#define RK2928_IO_TO_VIRT0(pa) IOMEM(pa + (0xFEA00000 - 0x10000000))
+#define RK2928_IO_TO_VIRT1(pa) IOMEM(pa + (0xFED00000 - 0x20000000))
+
+#define RK2928_IMEM_PHYS 0x10080000
+#define RK2928_IMEM_BASE IOMEM(0xFEF00000)
+#define RK2928_IMEM_NONCACHED RK2928_IO_TO_VIRT0(RK2928_IMEM_PHYS)
+#define RK2928_IMEM_SIZE SZ_8K
+
+#define RK2928_GPU_PHYS 0x10090000
+#define RK2928_GPU_SIZE SZ_64K
+
+#define RK2928_ROM_PHYS 0x10100000
+#define RK2928_ROM_SIZE SZ_16K
+#define RK2928_VCODEC_PHYS 0x10104000
+#define RK2928_VCODEC_SIZE SZ_16K
+
+#define RK2928_CIF_PHYS 0x1010a000
+#define RK2928_CIF_SIZE SZ_8K
+#define RK2928_RGA_PHYS 0x1010c000
+#define RK2928_RGA_SIZE SZ_8K
+#define RK2928_LCDC_PHYS 0x1010e000
+#define RK2928_LCDC_SIZE SZ_8K
+
+#define RK2928_CPU_AXI_BUS_PHYS 0x10128000
+#define RK2928_CPU_AXI_BUS_BASE RK2928_IO_TO_VIRT0(RK2928_CPU_AXI_BUS_PHYS)
+#define RK2928_CPU_AXI_BUS_SIZE SZ_32K
+
+#define RK2928_L2C_PHYS 0x10138000
+#define RK2928_L2C_BASE RK2928_IO_TO_VIRT0(RK2928_L2C_PHYS)
+#define RK2928_L2C_SIZE SZ_16K
+#define RK2928_SCU_PHYS 0x1013c000
+#define RK2928_SCU_BASE RK2928_IO_TO_VIRT0(RK2928_SCU_PHYS)
+#define RK2928_SCU_SIZE SZ_256
+#define RK2928_GICC_PHYS 0x1013c100
+#define RK2928_GICC_BASE RK2928_IO_TO_VIRT0(RK2928_GICC_PHYS)
+#define RK2928_GICC_SIZE SZ_256
+#define RK2928_GTIMER_PHYS 0x1013c200
+#define RK2928_GTIMER_BASE RK2928_IO_TO_VIRT0(RK2928_GTIMER_PHYS)
+#define RK2928_GTIMER_SIZE SZ_1K
+#define RK2928_PTIMER_PHYS 0x1013c600
+#define RK2928_PTIMER_BASE RK2928_IO_TO_VIRT0(RK2928_PTIMER_PHYS)
+#define RK2928_PTIMER_SIZE (SZ_2K + SZ_512)
+#define RK2928_GICD_PHYS 0x1013d000
+#define RK2928_GICD_BASE RK2928_IO_TO_VIRT0(RK2928_GICD_PHYS)
+#define RK2928_GICD_SIZE SZ_4K
+
+#define RK2928_CORE_PHYS RK2928_L2C_PHYS
+#define RK2928_CORE_BASE RK2928_IO_TO_VIRT0(RK2928_CORE_PHYS)
+#define RK2928_CORE_SIZE (RK2928_L2C_SIZE + SZ_8K)
+
+#define RK2928_USBOTG20_PHYS 0x10180000
+#define RK2928_USBOTG20_SIZE SZ_256K
+#define RK2928_USBHOST20_PHYS 0x101c0000
+#define RK2928_USBHOST20_SIZE SZ_256K
+
+#define RK2928_SDMMC_PHYS 0x10214000
+#define RK2928_SDMMC_SIZE SZ_16K
+#define RK2928_SDIO_PHYS 0x10218000
+#define RK2928_SDIO_SIZE SZ_16K
+#define RK2928_EMMC_PHYS 0x1021c000
+#define RK2928_EMMC_SIZE SZ_16K
+#define RK2928_I2S_PHYS 0x10220000
+#define RK2928_I2S_SIZE SZ_8K
+
+#define RK2928_AHB_ARB0_PHYS 0x10234000
+#define RK2928_AHB_ARB0_SIZE SZ_32K
+#define RK2928_AHB_ARB1_PHYS 0x1023C000
+#define RK2928_AHB_ARB1_SIZE (784 * SZ_1K)
+#define RK2928_PERI_AXI_BUS_PHYS 0x10300000
+#define RK2928_PERI_AXI_BUS_SIZE SZ_1M
+#define RK2928_GPS_PHYS 0x10400000
+#define RK2928_GPS_SIZE SZ_1M
+#define RK2928_NANDC_PHYS 0x10500000
+#define RK2928_NANDC_SIZE SZ_16K
+
+#define RK2928_CRU_PHYS 0x20000000
+#define RK2928_CRU_BASE RK2928_IO_TO_VIRT1(RK2928_CRU_PHYS)
+#define RK2928_CRU_SIZE SZ_4K
+#define RK2928_DDR_PCTL_PHYS 0x20004000
+#define RK2928_DDR_PCTL_BASE RK2928_IO_TO_VIRT1(RK2928_DDR_PCTL_PHYS)
+#define RK2928_DDR_PCTL_SIZE SZ_16K
+#define RK2928_GRF_PHYS 0x20008000
+#define RK2928_GRF_BASE RK2928_IO_TO_VIRT1(RK2928_GRF_PHYS)
+#define RK2928_GRF_SIZE SZ_4K
+#define RK2928_DDR_PHY_PHYS 0x2000a000
+#define RK2928_DDR_PHY_BASE RK2928_IO_TO_VIRT1(RK2928_DDR_PHY_PHYS)
+#define RK2928_DDR_PHY_SIZE (SZ_16K + SZ_8K)
+
+#define RK2928_DBG_PHYS 0x20020000
+#define RK2928_DBG_SIZE SZ_64K
+#define RK2928_ACODEC_PHYS 0x20030000
+#define RK2928_ACODEC_SIZE SZ_16K
+#define RK2928_HDMI_PHYS 0x20034000
+#define RK2928_HDMI_SIZE SZ_16K
+
+#define RK2928_TIMER0_PHYS 0x20044000
+#define RK2928_TIMER0_BASE RK2928_IO_TO_VIRT1(RK2928_TIMER0_PHYS)
+#define RK2928_TIMER0_SIZE SZ_4K
+#define RK2928_TIMER1_PHYS 0x20046000
+#define RK2928_TIMER1_BASE RK2928_IO_TO_VIRT1(RK2928_TIMER1_PHYS)
+#define RK2928_TIMER1_SIZE SZ_4K
+
+#define RK2928_WDT_PHYS 0x2004c000
+#define RK2928_WDT_SIZE SZ_4K
+#define RK2928_PWM_PHYS 0x20050000
+#define RK2928_PWM_BASE RK2928_IO_TO_VIRT1(RK2928_PWM_PHYS)
+#define RK2928_PWM_SIZE SZ_4K
+
+#define RK2928_I2C1_PHYS 0x20054000
+#define RK2928_I2C1_SIZE SZ_4K
+#define RK2928_RKI2C1_PHYS 0x20056000
+#define RK2928_RKI2C1_SIZE SZ_4K
+#define RK2928_I2C2_PHYS 0x20058000
+#define RK2928_I2C2_SIZE SZ_4K
+#define RK2928_RKI2C2_PHYS 0x2005a000
+#define RK2928_RKI2C2_SIZE SZ_4K
+#define RK2928_I2C3_PHYS 0x2005c000
+#define RK2928_I2C3_SIZE SZ_4K
+#define RK2928_RKI2C3_PHYS 0x2005e000
+#define RK2928_RKI2C3_SIZE SZ_4K
+
+#define RK2928_UART0_PHYS 0x20060000
+#define RK2928_UART0_BASE RK2928_IO_TO_VIRT1(RK2928_UART0_PHYS)
+#define RK2928_UART0_SIZE SZ_4K
+#define RK2928_UART1_PHYS 0x20064000
+#define RK2928_UART1_BASE RK2928_IO_TO_VIRT1(RK2928_UART1_PHYS)
+#define RK2928_UART1_SIZE SZ_4K
+#define RK2928_UART2_PHYS 0x20068000
+#define RK2928_UART2_BASE RK2928_IO_TO_VIRT1(RK2928_UART2_PHYS)
+#define RK2928_UART2_SIZE SZ_4K
+
+#define RK2928_SARADC_PHYS 0x2006c000
+#define RK2928_SARADC_SIZE SZ_4K
+#define RK2928_I2C0_PHYS 0x20070000
+#define RK2928_I2C0_SIZE SZ_4K
+#define RK2928_RKI2C0_PHYS 0x20072000
+#define RK2928_RKI2C0_SIZE SZ_4K
+#define RK2928_SPI_PHYS 0x20074000
+#define RK2928_SPI_SIZE SZ_16K
+#define RK2928_DMAC_PHYS 0x20078000
+#define RK2928_DMAC_SIZE SZ_16K
+
+#define RK2928_GPIO0_PHYS 0x2007c000
+#define RK2928_GPIO0_BASE RK2928_IO_TO_VIRT1(RK2928_GPIO0_PHYS)
+#define RK2928_GPIO0_SIZE SZ_4K
+#define RK2928_GPIO1_PHYS 0x20080000
+#define RK2928_GPIO1_BASE RK2928_IO_TO_VIRT1(RK2928_GPIO1_PHYS)
+#define RK2928_GPIO1_SIZE SZ_4K
+#define RK2928_GPIO2_PHYS 0x20084000
+#define RK2928_GPIO2_BASE RK2928_IO_TO_VIRT1(RK2928_GPIO2_PHYS)
+#define RK2928_GPIO2_SIZE SZ_4K
+#define RK2928_GPIO3_PHYS 0x20088000
+#define RK2928_GPIO3_BASE RK2928_IO_TO_VIRT1(RK2928_GPIO3_PHYS)
+#define RK2928_GPIO3_SIZE SZ_4K
+
+#define RK2928_EFUSE_PHYS 0x20090000
+#define RK2928_EFUSE_SIZE SZ_4K
+
+#if CONFIG_RK_DEBUG_UART == 0
+#define DEBUG_UART_PHYS RK2928_UART0_PHYS
+#define DEBUG_UART_BASE RK2928_UART0_BASE
+#elif CONFIG_RK_DEBUG_UART == 1
+#define DEBUG_UART_PHYS RK2928_UART1_PHYS
+#define DEBUG_UART_BASE RK2928_UART1_BASE
+#elif CONFIG_RK_DEBUG_UART == 2
+#define DEBUG_UART_PHYS RK2928_UART2_PHYS
+#define DEBUG_UART_BASE RK2928_UART2_BASE
+#endif
+
+#define GIC_DIST_BASE RK2928_GICD_BASE
+#define GIC_CPU_BASE RK2928_GICC_BASE
+
+#endif
--- /dev/null
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+#define FIQ_START 0
+
+#define IRQ_LOCALTIMER 29
+
+#define IRQ_DMAC_0 32
+#define IRQ_DMAC_1 33
+#define IRQ_DDR_PCTL 34
+#define IRQ_GPU_GP 35
+#define IRQ_GPU_MMU 36
+#define IRQ_GPU_PP 37
+#define IRQ_VEPU 38
+#define IRQ_VDPU 39
+#define IRQ_CIF 40
+#define IRQ_LCDC 41
+#define IRQ_USB_OTG 42
+#define IRQ_USB_HOST 43
+#define IRQ_GPS 44
+#define IRQ_GPS_TIMER 45
+#define IRQ_SDMMC 46
+#define IRQ_SDIO 47
+#define IRQ_EMMC 48
+#define IRQ_SARADC 49
+#define IRQ_NANDC 50
+#define IRQ_I2S 51
+#define IRQ_UART0 52
+#define IRQ_UART1 53
+#define IRQ_UART2 54
+#define IRQ_SPI 55
+#define IRQ_I2C0 56
+#define IRQ_I2C1 57
+#define IRQ_I2C2 58
+#define IRQ_I2C3 59
+#define IRQ_TIMER0 60
+#define IRQ_TIMER1 61
+#define IRQ_PWM0 62
+#define IRQ_PWM1 63
+#define IRQ_PWM2 64
+
+#define IRQ_WDT 66
+#define IRQ_OTG_BVALID 67
+#define IRQ_GPIO0 68
+#define IRQ_GPIO1 69
+#define IRQ_GPIO2 70
+#define IRQ_GPIO3 71
+
+#define IRQ_PERI_AHB_USB_ARBITER 74
+#define IRQ_PERI_AHB_EMEM_ARBITER 75
+#define IRQ_RGA 76
+#define IRQ_HDMI 77
+#define IRQ_SDMMC_DETECT 78
+#define IRQ_SDIO_DETECT 79
+
+//hhb@rock-chips.com this spi is used for fiq_debugger signal irq
+#define IRQ_UART_SIGNAL 127
+
+#define NR_GIC_IRQS (4 * 32)
+#define NR_GPIO_IRQS (4 * 32)
+#define NR_BOARD_IRQS 64
+#define NR_IRQS (NR_GIC_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
+
+#endif
#ifndef __MACH_MEMORY_H
#define __MACH_MEMORY_H
+#include <plat/memory.h>
#include <mach/io.h>
/*
--- /dev/null
+#ifndef __MACH_VMALLOC_H
+#define __MACH_VMALLOC_H
+
+#define VMALLOC_END 0xFE800000
+
+#endif
--- /dev/null
+/* arch/arm/mach-rk2928/io.c
+ *
+ * Copyright (C) 2012 ROCKCHIP, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <asm/page.h>
+#include <asm/mach/map.h>
+
+#define RK2928_DEVICE(name) { \
+ .virtual = (unsigned long) RK2928_##name##_BASE, \
+ .pfn = __phys_to_pfn(RK2928_##name##_PHYS), \
+ .length = RK2928_##name##_SIZE, \
+ .type = MT_DEVICE, \
+ }
+
+static struct map_desc rk2928_io_desc[] __initdata = {
+ RK2928_DEVICE(CORE),
+ RK2928_DEVICE(CPU_AXI_BUS),
+#if CONFIG_RK_DEBUG_UART == 0
+ RK2928_DEVICE(UART0),
+#elif CONFIG_RK_DEBUG_UART == 1
+ RK2928_DEVICE(UART1),
+#elif CONFIG_RK_DEBUG_UART == 2
+ RK2928_DEVICE(UART2),
+#endif
+ RK2928_DEVICE(GRF),
+ RK2928_DEVICE(CRU),
+ RK2928_DEVICE(GPIO0),
+ RK2928_DEVICE(GPIO1),
+ RK2928_DEVICE(GPIO2),
+ RK2928_DEVICE(GPIO3),
+ RK2928_DEVICE(TIMER0),
+ RK2928_DEVICE(TIMER1),
+ RK2928_DEVICE(PWM),
+ RK2928_DEVICE(DDR_PCTL),
+ RK2928_DEVICE(DDR_PHY),
+ {
+ .virtual = (unsigned long) RK2928_IMEM_NONCACHED,
+ .pfn = __phys_to_pfn(RK2928_IMEM_PHYS),
+ .length = RK2928_IMEM_SIZE,
+ .type = MT_MEMORY_NONCACHED,
+ },
+};
+
+void __init rk2928_map_common_io(void)
+{
+ iotable_init(rk2928_io_desc, ARRAY_SIZE(rk2928_io_desc));
+}
--- /dev/null
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pm.h>
+#include <linux/suspend.h>
+#include <linux/random.h>
+#include <linux/crc32.h>
+#include <linux/io.h>
+#include <linux/wakelock.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
+
+#include <mach/system.h>
+#include <mach/sram.h>
+#include <mach/gpio.h>
+
+void __sramfunc sram_printch(char byte)
+{
+#ifdef DEBUG_UART_BASE
+ writel_relaxed(byte, DEBUG_UART_BASE);
+ dsb();
+
+ /* loop check LSR[6], Transmitter Empty bit */
+ while (!(readl_relaxed(DEBUG_UART_BASE + 0x14) & 0x40))
+ barrier();
+
+ if (byte == '\n')
+ sram_printch('\r');
+#endif
+}
+
--- /dev/null
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <mach/system.h>
+#include <linux/string.h>
+
+static void rk2928_arch_reset(char mode, const char *cmd)
+{
+ while (1);
+}
+
+void (*arch_reset)(char, const char *) = rk2928_arch_reset;
projects / firefly-linux-kernel-4.4.55.git / commitdiff